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12/14/2004
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09916974
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07/27/2001
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08/15/2002
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11/04/2003
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09918011
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07/30/2001
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02/04/2003
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09918012
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07/30/2001
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05/13/2003
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09918021
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07/30/2001
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01/13/2004
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09918028
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07/30/2001
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03/23/2004
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09918183
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07/30/2001
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08/25/2009
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09918232
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07/30/2001
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01/22/2002
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07/30/2001
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06/28/2005
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09918736
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07/31/2001
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08/12/2003
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09919222
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07/31/2001
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07/29/2003
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09920890
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08/02/2001
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09/09/2003
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09921028
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08/02/2001
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08/16/2005
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09921350
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08/02/2001
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02/15/2005
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09922755
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08/06/2001
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MULTIPROCESSOR SYSTEM AND METHOD FOR SIMULTANEOUSLY PLACING ALL PROCESSORS INTO DEBUG MODE
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03/01/2005
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09923155
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08/06/2001
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05/20/2003
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09923526
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08/06/2001
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08/20/2002
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09923657
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08/07/2001
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DIE POWER DISTRIBUTION SYSTEM
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04/20/2004
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09925088
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08/07/2001
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COMPRESSED VIDEO EDITOR WITH TRANSITION BUFFER MATCHER
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07/22/2003
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09925089
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08/08/2001
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COMPRESSED VIDEO EDITOR WITH TRANSITION BUFFER MATCHER
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12/17/2002
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09925694
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08/09/2001
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01/25/2005
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09927139
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08/10/2001
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FLOATING POINT DIVIDE AND SQUARE ROOT PROCESSOR
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08/09/2005
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09927662
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08/10/2001
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03/18/2003
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09928071
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08/10/2001
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03/02/2004
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09928471
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08/13/2001
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06/01/2004
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09928570
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08/13/2001
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HIGH SELECTIVITY SIC ETCH IN INTEGRATED CIRCUIT FABRICATION
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03/11/2003
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09929183
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08/14/2001
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DIVIDER CIRCUIT, METHOD OF OPERATION THEREOF AND A PHASE-LOCKED LOOP CIRCUIT INCORPORATING THE SAME
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05/13/2003
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09932307
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08/17/2001
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04/20/2004
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09932527
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08/17/2001
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PROCESS FOR REDUCING DEFECTS IN COPPER-FILLED VIAS AND/OR TRENCHES FORMED IN POROUS LOW-K DIELECTRIC MATERIAL
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07/06/2004
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09932716
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08/17/2001
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CHARACTERISTIC IMPEDANCE EQUALIZER AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME
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12/06/2005
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09934051
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08/21/2001
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BZFLASH SUBCIRCUIT TO DYNAMICALLY SUPPLY BZ CODES FOR CONTROLLED IMPEDANCE BUFFER DEVELOPMENT, VERIFICATION AND SYSTEM LEVEL SIMULATIONS
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04/30/2002
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09934287
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08/21/2001
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ELECTRICAL SIGNAL SYNCHRONIZATION
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08/14/2007
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09938081
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08/23/2001
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09/16/2004
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INTERFACE CIRCUIT FOR PROVIDING A COMPUTER LOGIC CIRCUIT WITH FIRST AND SECOND VOLTAGES AND AN ASSOCIATED METHOD
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11/19/2002
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08/24/2001
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PCI-X DRIVER CONTROL
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02/18/2003
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09940130
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08/27/2001
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01/03/2006
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09940754
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08/28/2001
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PROGRAMMABLE DIGITAL FILTER IMPLEMENTATION FOR LOSS-OF-SIGNAL DETECTION FOR SERIAL COMMUNICATIONS APPLICATIONS
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07/01/2003
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08/28/2001
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OPTIMIZED METAL STACK STRATEGY
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11/29/2005
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09941540
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08/29/2001
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PROGRAMMABLE POLARITY FOR HIGH SPEED DIFFERENTIAL INTERFACES
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05/24/2005
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09942220
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08/29/2001
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SYSTEM AND METHOD FOR OPTIMIZING THE ELECTROSTATIC REMOVAL OF A WORKPIECE FROM A CHUCK
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08/25/2009
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08/29/2001
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ARRANGEMENT AND METHOD FOR ABATING EFFLUENT FROM A PROCESS
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11/22/2005
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09942390
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08/29/2001
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METHOD AND APPARATUS OF ESTABLISHING A DYNAMICALLY ADJUSTABLE LOOP OF DELAYED READ COMMANDS FOR COMPLETION IN A QUEUE BUFFER
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10/13/2009
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08/30/2001
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ARRANGEMENT AND METHOD FOR FABRICATING A SEMICONDUCTOR WAFER
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02/18/2003
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09943403
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08/30/2001
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SEMICONDUCTOR WAFER ARRANGEMENT AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER
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05/11/2004
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09946000
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09/04/2001
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SYSTEM AND METHOD TO ELIMINATE RACE CONDITIONS IN INPUT/OUTPUT OPERATIONS FOR HIGH BANDWIDTH ARCHITECTURES
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06/03/2003
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09946033
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09/04/2001
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INTEGRATED CIRCUIT HAVING DEDICATED PROBE PADS FOR USE IN TESTING DENSELY PATTERNED BONDING PADS
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11/18/2003
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09946253
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09/05/2001
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CHEMICAL MECHANICAL POLISHING PAD
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08/13/2002
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09946759
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09/04/2001
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SENSE AMPLIFIER IMBALANCE COMPENSATION FOR MEMORY SELF- TIMED CIRCUITS
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04/16/2002
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09946895
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09/05/2001
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METHOD FOR CMP ENDPOINT DETECTION
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07/15/2003
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09947740
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09/06/2001
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01/24/2006
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09948015
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09/06/2001
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05/23/2002
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APPARATUS AND METHOD FOR ACQUIRING PHASE LOCK TIMING RECOVERY IN A PARTIAL RESPONSE MAXIMUM LIKELIHOOD (PRML) CHANNEL
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11/12/2002
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09948160
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09/06/2001
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ON-CHIP MULTIPLE LAYER VERTICALLY TRANSITIONING OPTICAL WAVEGUIDE AND DAMASCENE METHOD OF FABRICATING THE SAME
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11/25/2003
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09948190
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09/07/2001
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04/27/2004
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09948808
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09/07/2001
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METHOD OF TESTING THE PROCESSING OF A SEMICONDUCTOR WAFER ON A CMP APPARATUS
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03/16/2004
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09/07/2001
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08/21/2007
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09949399
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09/07/2001
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METHOD AND SYSTEM FOR PERFORMING BUILT-IN SELF-TEST ROUTINES USING AN ACCUMULATOR TO STORE FAULT INFORMATION
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09/19/2006
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09/10/2001
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12/16/2003
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09/10/2001
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08/20/2002
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09/13/2001
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LOOP FILTER AND METHOD FOR GENERATING A CONTROL SIGNAL IN PHASE-LOCKED LOOP CIRCUITS
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10/04/2005
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09951939
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09/12/2001
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A SYSTEM AND METHOD FOR SYNCHRONIZING A SELECTED MASTER CIRCUIT WITH A SLAVE CIRCUIT BY RECEIVING AND FORWARDING A CONTROL SIGNAL BETWEEN THE CIRCUITS AND OPERATING THE CIRCUITS BASED ON THEIR RECEIVED CONTROL SIGNAL
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09/16/2003
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09/14/2001
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09/21/2004
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09952540
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09/14/2001
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11/15/2005
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09/11/2001
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04/06/2004
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09/17/2001
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07/01/2003
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09/17/2001
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04/22/2003
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09/18/2001
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STEPPED GAIN AMPLIFIER WITH IMPROVED ATTENUATION
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09/30/2003
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09/19/2001
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CELL PLACEMENT IN INTEGRATED CIRCUIT CHIPS TO REMOVE CELL OVERLAP, ROW OVERFLOW AND OPTIMAL PLACEMENT OF DUAL HEIGHT CELLS
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07/11/2006
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09/19/2001
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04/06/2004
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09/20/2001
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03/20/2003
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07/01/2003
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09957232
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09/20/2001
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03/02/2004
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09957410
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09/20/2001
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11/04/2003
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09/19/2001
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LIQUID BASED AIR FILTRATION SYSTEM
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Issue Dt:
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08/03/2004
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Application #:
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09960441
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Filing Dt:
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09/21/2001
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Title:
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ARRANGEMENT FOR MEASURING PRESSURE ON A SEMICONDUCTOR WAFER AND AN ASSOCIATED METHOD FOR FABRICATING A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
|
05/30/2006
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Application #:
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09960560
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Filing Dt:
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09/21/2001
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Title:
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DIGITALLY CALIBRATED NARROWBAND FILTER WITH ANALOG CHANNEL COMPENSATION
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Patent #:
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Issue Dt:
|
11/29/2005
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Application #:
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09960572
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Filing Dt:
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09/21/2001
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Title:
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BLOCK MOVE ENGINE WITH GAMMA AND COLOR CONVERSIONS
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Patent #:
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Issue Dt:
|
05/25/2004
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Application #:
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09960578
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Filing Dt:
|
09/21/2001
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Title:
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VIDEO SAMPLING STRUCTURE CONVERSION IN BMME
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Patent #:
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Issue Dt:
|
01/07/2003
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Application #:
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09960765
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Filing Dt:
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09/21/2001
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Title:
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INDIUM FIELD IMPLANT FOR PUNCHTHROUGH PROTECTION IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
12/27/2005
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Application #:
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09960771
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Filing Dt:
|
09/21/2001
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Title:
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INTEGRATION OF VIDEO PROCESSING INTO A BLOCK MOVE ENGINE
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|
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Patent #:
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Issue Dt:
|
03/14/2006
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Application #:
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09961596
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Filing Dt:
|
09/24/2001
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Title:
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HIGH RATE PRODUCT CODE DECODING FOR PARTIAL RESPONSE CHANNEL
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|
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Patent #:
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Issue Dt:
|
04/13/2004
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Application #:
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09962541
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Filing Dt:
|
09/24/2001
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Title:
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ALGORITHM FOR MAINTAINING MAXIMUM STREAMING PERFORMANCE OF MIRRORED DISKS
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|
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Patent #:
|
|
Issue Dt:
|
03/25/2003
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Application #:
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09962630
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Filing Dt:
|
09/24/2001
|
|
Title:
|
VARIABLE DYNAMIC RANGE ANALOG-TO-DIGITAL CONVERTER
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|
|
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Patent #:
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Issue Dt:
|
04/13/2004
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Application #:
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09962645
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Filing Dt:
|
09/25/2001
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Publication #:
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Pub Dt:
|
03/27/2003
| | | | |
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Title:
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BUFFER PARTITIONING FOR MANAGING MULTIPLE DATA STREAMS
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|
|
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Patent #:
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|
Issue Dt:
|
11/04/2003
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Application #:
|
09964011
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Filing Dt:
|
09/26/2001
|
|
Title:
|
VIRTUAL TREE-BASED NETLIST MODEL AND METHOD OF DELAY ESTIMATION FOR AN INTEGRATED CIRCUIT DESIGN
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/28/2006
|
Application #:
|
09964030
|
Filing Dt:
|
09/26/2001
|
|
Title:
|
METHOD AND APPARATUS FOR ADAPTIVE TIMING OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/16/2003
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Application #:
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09964157
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Filing Dt:
|
09/26/2001
|
|
Title:
|
METHOD AND APPARATUS FOR THE USE OF EMBEDDED RESISTANCE TO LINEARIZE AND IMPROVE THE MATCHING PROPERTIES OF TRANSISTORS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/26/2006
|
Application #:
|
09965292
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Filing Dt:
|
09/27/2001
|
|
Title:
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INFINIBAND ISOLATION BRIDGE MERGED WITH ARCHITECTURE OF AN INFINIBAND TRANSLATION BRIDGE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09965947
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Filing Dt:
|
09/28/2001
|
|
Title:
|
SYNCHRONIZING DATA OPERATIONS ACROSS A SYNCHRONIZATION BOUNDARY BETWEEN DIFFERENT CLOCK DOMAINS USING TWO-HOT ENCODING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
09966327
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Filing Dt:
|
09/28/2001
|
|
Publication #:
|
|
Pub Dt:
|
09/05/2002
| | | | |
|
Title:
|
REDUCING THE EFFECT OF SIMULTANEOUS SWITCHING NOISE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09966464
|
Filing Dt:
|
09/28/2001
|
|
Title:
|
METHOD OF FABRICATING A LOCAL INTERCONNECT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09966651
|
Filing Dt:
|
09/28/2001
|
|
Title:
|
HIGH FREQUENCY ELECTROCHEMICAL DEPOSITION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
09966867
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Filing Dt:
|
09/28/2001
|
|
Title:
|
SYSTEM AND METHOD FOR OPTIMIZING REMOTE DATA CONTENT DISTRIBUTION
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/27/2004
|
Application #:
|
09967074
|
Filing Dt:
|
09/28/2001
|
|
Title:
|
FABRICATION OF METAL CONTACTS FOR DEEP-SUBMICRON TECHNOLOGIES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09967195
|
Filing Dt:
|
09/28/2001
|
|
Title:
|
TRANSMISSION EQUALIZATION SYSTEM AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
09968008
|
Filing Dt:
|
10/02/2001
|
|
Title:
|
INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
09968009
|
Filing Dt:
|
10/02/2001
|
|
Title:
|
INTERGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
09968286
|
Filing Dt:
|
10/01/2001
|
|
Title:
|
DIE POWER DISTRIBUTION SYSTEM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09968944
|
Filing Dt:
|
10/02/2001
|
|
Title:
|
METHOD OF MAKING INTERCONNECT STRUCTURE INCLUDING DIAMOND BARRIER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
09969377
|
Filing Dt:
|
10/02/2001
|
|
Title:
|
IO BASED EMBEDDED PROCESSOR CLOCK SPEED CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
09970392
|
Filing Dt:
|
10/03/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
LATENT DEFECT CLASSIFICATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09971329
|
Filing Dt:
|
10/04/2001
|
|
Title:
|
PHOTOLITHOGRAPHY OVERLAY CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
09972100
|
Filing Dt:
|
10/05/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
SPICE TO VERILOG NETLIST TRANSLATOR AND DESIGN METHODS USING SPICE TO VERILOG AND VERILOG TO SPICE TRANSLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
09972330
|
Filing Dt:
|
10/05/2001
|
|
Title:
|
REQUEST AND COMPLETION QUEUE LOAD BALANCING
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|
