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Patent #:
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|
Issue Dt:
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11/10/1998
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Application #:
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08476434
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Filing Dt:
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06/07/1995
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Title:
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REDUCTION OF FALSE LOCKING OF CODE WORDS IN CONCATENATED DECODERS
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Patent #:
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Issue Dt:
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12/30/1997
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Application #:
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08477490
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Filing Dt:
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06/07/1995
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Title:
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CONFIGURATION MANAGEMENT AND AUTOMATED TEST SYSTEM FOR ASIC DESIGN SOFTWARE
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Patent #:
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Issue Dt:
|
09/02/1997
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Application #:
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08477827
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Filing Dt:
|
06/07/1995
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Title:
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OPTICAL CORRECTIVE TECHNIQUES WITH RETICLE FORMATION AND RETICLE STITCHING TO PROVIDE DESIGN FLEXIBILITY
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Patent #:
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Issue Dt:
|
08/26/1997
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Application #:
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08479018
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Filing Dt:
|
06/06/1995
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING PN JUNCTIONS SEPARATED BY DEPRESSIONS
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Patent #:
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Issue Dt:
|
09/16/1997
|
Application #:
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08481799
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Filing Dt:
|
06/07/1995
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Title:
|
KEYED END EFFECTOR FOR CMP PAD CONDITIONER
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Patent #:
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Issue Dt:
|
10/29/1996
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Application #:
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08482763
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Filing Dt:
|
06/07/1995
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Title:
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HIERARCHICAL CLOCK DISTRIBUTION SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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10/28/1997
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Application #:
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08484003
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Filing Dt:
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01/09/1996
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Title:
|
INPUT-OUTPUT (I/O) STRUCTURE WITH CAPACITIVELY TRIGGERED THYRISTOR FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
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Patent #:
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Issue Dt:
|
09/02/1997
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Application #:
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08484177
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Filing Dt:
|
06/07/1995
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Title:
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ENCAPSULATION OF ELECTRONIC COMPONENTS
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Patent #:
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|
Issue Dt:
|
02/24/1998
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Application #:
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08484849
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Filing Dt:
|
06/07/1995
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Title:
|
METHOD OF FABRICATING A GATE ARRAY INTERGRATED CIRCUIT INCLUDING INTER CONNECTABLE MACRO-ARRAYS
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Patent #:
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Issue Dt:
|
04/14/1998
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Application #:
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08485060
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Filing Dt:
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06/07/1995
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Title:
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MULTIPLE PIN DIE PACKAGE
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Patent #:
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Issue Dt:
|
12/09/1997
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Application #:
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08485517
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Filing Dt:
|
06/07/1995
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Title:
|
APPARATUS AND METHOD USING OPTICAL ENERGY FOR SPECIFYING AND QUANTITATIVELY CONTROLLING CHEMICALLY-REACTIVE COMPONENTS OF SEMICONDUCTOR PROCESSING PLASMA ETCHING GAS
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Patent #:
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Issue Dt:
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10/14/1997
|
Application #:
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08485865
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Filing Dt:
|
06/07/1995
|
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Title:
|
MULTI-CHIP-MODULE (MCM) MICROCIRCUIT INCLUDING MULTIPLE PROCESSORS AND ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
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Patent #:
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Issue Dt:
|
12/16/1997
|
Application #:
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08486803
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Filing Dt:
|
06/07/1995
|
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Title:
|
SILICIDATION PROCESS WITH ETCH STOP
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Patent #:
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|
Issue Dt:
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12/10/1996
|
Application #:
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08488075
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Filing Dt:
|
06/07/1995
|
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Title:
|
SELF-ALIGNED TWIN WELL PROCESS HAVING A SIO2-POLYSILICON-SIO2 BARRIER MASK
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Patent #:
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Issue Dt:
|
10/20/1998
|
Application #:
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08491433
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Filing Dt:
|
06/16/1995
|
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Title:
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METHOD FOR LOCAL RIP-UP AND REROUTE OF SIGNAL PATHS IN AN IC DESIGN
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Patent #:
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Issue Dt:
|
08/05/1997
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Application #:
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08496861
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Filing Dt:
|
06/30/1995
|
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Title:
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IMAGE SENSOR ARRAY WITH PICTURE ELEMENT SENSOR TESTABILITY
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Patent #:
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Issue Dt:
|
02/03/1998
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Application #:
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08501284
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Filing Dt:
|
07/12/1995
|
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Title:
|
ERRORS AND ERASURES CORRECTING REED-SOLOMON DECODER
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Patent #:
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Issue Dt:
|
09/23/1997
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Application #:
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08501289
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Filing Dt:
|
07/12/1995
|
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Title:
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METHOD OF MAKING COMBINED METAL OXIDE SEMICONDUCTOR AND JUNCTION FIELD EFFECT TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
|
08/25/1998
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Application #:
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08502300
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Filing Dt:
|
07/13/1995
|
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Title:
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SEMICONDUCTOR CHIP HAVING IDENTIFICATION/ENCRYPTION CODE
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Patent #:
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Issue Dt:
|
08/06/1996
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Application #:
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08502566
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Filing Dt:
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07/13/1995
|
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Title:
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COMBINED JFET & MOS TRANSISTOR DEVICE, CIRCUIT
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Patent #:
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Issue Dt:
|
12/15/1998
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Application #:
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08505044
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Filing Dt:
|
07/21/1995
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Title:
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APPARATUS AND METHOD FOR RECOVERING A CLOCK SIGNAL WHICH IS EMBEDDED IN AN INCOMING DATA STREAM
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Patent #:
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Issue Dt:
|
03/17/1998
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Application #:
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08506148
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Filing Dt:
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07/24/1995
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Title:
|
METHOD AND APPARATUS FOR ENHANCING THROUGHPUT OF DISK ARRAY DATA TRANSFERS IN A CONTROLLER
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Patent #:
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Issue Dt:
|
04/28/1998
|
Application #:
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08506164
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Filing Dt:
|
07/24/1995
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Title:
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METHOD OF IMPROVING MOLDING OF AN OVERMOLDED PACKAGE BODY ON A SUBSTRATE
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Patent #:
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Issue Dt:
|
03/31/1998
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Application #:
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08506293
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Filing Dt:
|
07/24/1995
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Title:
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METHOD AND APPARTUS FOR TRANSFERRING DATA IN A CONTROLLER HAVING CENTRALIZED MEMORY
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Patent #:
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Issue Dt:
|
05/20/1997
|
Application #:
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08506821
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Filing Dt:
|
07/25/1995
|
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Title:
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PROCESS MONITOR FOR CMOS INTEGRATED CIRCUITS
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Patent #:
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|
Issue Dt:
|
09/02/1997
|
Application #:
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08512678
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Filing Dt:
|
08/08/1995
|
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Title:
|
AUTOMATING PHOTOLITHOGRAPHY IN THE FABRICATION OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
05/05/1998
|
Application #:
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08514479
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Filing Dt:
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08/11/1995
|
|
Title:
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DUAL BUS ARCHITECTURE FOR A STORAGE DEVICE
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|
Patent #:
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|
Issue Dt:
|
06/18/2002
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Application #:
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08517142
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Filing Dt:
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08/21/1995
|
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Title:
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HEXAGONAL ARCHITECTURE
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|
Patent #:
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|
Issue Dt:
|
04/21/1998
|
Application #:
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08517153
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Filing Dt:
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08/21/1995
|
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Title:
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HEXAGONAL DRAM ARRAY
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|
Patent #:
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|
Issue Dt:
|
10/13/1998
|
Application #:
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08517171
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Filing Dt:
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08/21/1995
|
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Title:
|
CAD FOR HEXAGONAL ARCHITECTURE
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Patent #:
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|
Issue Dt:
|
02/16/1999
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Application #:
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08517189
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Filing Dt:
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08/21/1995
|
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Title:
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HEXAGONAL SENSE CELL ARCHITECTURE
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|
Patent #:
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|
Issue Dt:
|
08/04/1998
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Application #:
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08517236
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Filing Dt:
|
08/21/1995
|
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Title:
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HEXAGONAL ARCHITECTURE WITH TRIANGULAR SHAPED CELLS
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Patent #:
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Issue Dt:
|
09/01/1998
|
Application #:
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08517266
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Filing Dt:
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08/21/1995
|
|
Title:
|
HEXAGONAL SRAM ARCHITECTURE
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|
Patent #:
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|
Issue Dt:
|
03/30/1999
|
Application #:
|
08517339
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Filing Dt:
|
08/21/1995
|
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Title:
|
TRI-DIRECTIONAL INTERCONNECT ARCHITECTURE FOR SRAM
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Patent #:
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Issue Dt:
|
10/26/1999
|
Application #:
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08517406
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Filing Dt:
|
08/21/1995
|
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Title:
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ARCHITECTURE HAVING DIAMOND SHAPED OR PARALLELOGRAM SHAPED CELLS
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Patent #:
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|
Issue Dt:
|
09/15/1998
|
Application #:
|
08517441
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Filing Dt:
|
08/21/1995
|
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Title:
|
POLYDIRECTIONAL NON-ORTHOGINAL THREE LAYER INTERCONNECT ARCHITECTURE
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Patent #:
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Issue Dt:
|
01/26/1999
|
Application #:
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08517451
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Filing Dt:
|
08/21/1995
|
|
Title:
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TRIANGULAR SEMICONDUCTOR 'NAND' GATE
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|
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|
Patent #:
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|
Issue Dt:
|
09/22/1998
|
Application #:
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08517463
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Filing Dt:
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08/21/1995
|
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Title:
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TRANSISTORS HAVING DYNAMICALLY ADJUSTABLE CHARACTERISTICS
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Patent #:
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Issue Dt:
|
11/10/1998
|
Application #:
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08517479
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Filing Dt:
|
08/21/1995
|
|
Title:
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TRIANGULAR SEMICONDUCTOR "AND" GATE DEVICE
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|
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|
Patent #:
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|
Issue Dt:
|
07/07/1998
|
Application #:
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08517508
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Filing Dt:
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08/21/1995
|
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Title:
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HEXAGONAL FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE
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Patent #:
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|
Issue Dt:
|
08/01/2000
|
Application #:
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08517892
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Filing Dt:
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08/21/1995
|
|
Title:
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TRIANGULAR SEMICONDUCTOR OR GATE
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|
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|
Patent #:
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|
Issue Dt:
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03/25/1997
|
Application #:
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08520030
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Filing Dt:
|
08/28/1995
|
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Title:
|
LEAK DETECTION SYSTEM FOR A GAS MANIFOLD OF A CHEMICAL VAPOR DEPOSITION APPARATUS
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Patent #:
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Issue Dt:
|
06/03/1997
|
Application #:
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08520058
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Filing Dt:
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08/28/1995
|
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Title:
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A METHOD OF FORMING A LAYER OF MATERIAL ON A WAFER
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Patent #:
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Issue Dt:
|
12/17/1996
|
Application #:
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08521795
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Filing Dt:
|
08/31/1995
|
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Title:
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IMPLANTATION OF A SEMICONDUCTOR SUBSTRATE WITH CONTROLLED AMOUNT OF NOBLE GAS IONS TO REDUCE CHANNELING AND/OR DIFFUSION OF A BORON DOPANT SUBSEQUENTLY IMPLANTED INTO THE SUBSTRATE TO FORM P- LDD REGION OF A PMOS DEVICE
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Patent #:
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Issue Dt:
|
12/16/1997
|
Application #:
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08525839
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Filing Dt:
|
09/08/1995
|
|
Title:
|
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING MULTIWAY PARTITIONING WITH CONSTRAINTS
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Patent #:
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Issue Dt:
|
03/11/1997
|
Application #:
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08527660
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Filing Dt:
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09/13/1995
|
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Title:
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METHOD AND APPARATUS FOR DETECTING ASSERTION OF MULTIPLE SIGNALS
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|
Patent #:
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Issue Dt:
|
02/18/1997
|
Application #:
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08527704
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Filing Dt:
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09/13/1995
|
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Title:
|
FAST WORD LINE DECODER FOR MEMORY DEVICES
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|
Patent #:
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|
Issue Dt:
|
09/02/1997
|
Application #:
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08531659
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Filing Dt:
|
09/21/1995
|
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Title:
|
HIGH SURFACE AREA TRENCHES FOR AN INTEGRATED CIRCUIT DEVICE
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|
Patent #:
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|
Issue Dt:
|
06/02/1998
|
Application #:
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08531727
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Filing Dt:
|
09/21/1995
|
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Title:
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INTEGRATED CIRCUIT DEVICE FABRICATION BY PLASMA ETCHING
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|
Patent #:
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|
Issue Dt:
|
08/18/1998
|
Application #:
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08534228
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Filing Dt:
|
09/26/1995
|
|
Title:
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RECEIVER CIRCUIT HAVING ADAPTIVE EQUALIZER WITH CHARACTERISTICS DETERMINED BY SIGNAL ENVELOPE MEASUREMENT AND METHOD THEREFOR
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Patent #:
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Issue Dt:
|
04/15/1997
|
Application #:
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08536002
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Filing Dt:
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09/29/1995
|
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Title:
|
HIGH DENSITY CMOS INTEGRATED CIRCUIT WITH HEAT TRANSFER STRUCTURE FOR IMPROVED COOLING
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Patent #:
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|
Issue Dt:
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07/21/1998
|
Application #:
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08536004
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Filing Dt:
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09/29/1995
|
|
Title:
|
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING GENERALIZED ASSIGNMENT
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Patent #:
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Issue Dt:
|
12/09/1997
|
Application #:
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08538629
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Filing Dt:
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10/04/1995
|
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Title:
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METHOD OF CENTERING A HIGH PRESSURE LID SEAL
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|
Patent #:
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|
Issue Dt:
|
02/10/1998
|
Application #:
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08538630
|
Filing Dt:
|
10/04/1995
|
|
Title:
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HIGH PRESSURE LID SEAL CLIP APPARATUS
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|
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|
Patent #:
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|
Issue Dt:
|
06/10/1997
|
Application #:
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08538631
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
HIGH CONTACT DENSITY BALL GRID ARRAY PACKAGE FOR FLIP-CHIPS
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|
Patent #:
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|
Issue Dt:
|
05/27/1997
|
Application #:
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08538907
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
METHOD OF CENTERING A LID SEAL CLIP
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|
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|
Patent #:
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|
Issue Dt:
|
07/28/1998
|
Application #:
|
08539188
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
CONFIGURABLE BALL GRID ARRAY PACKAGE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/04/1997
|
Application #:
|
08539189
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
CENTERING LID SEAL CLIP APPARATUS
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|
|
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|
Patent #:
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|
Issue Dt:
|
02/11/1997
|
Application #:
|
08540336
|
Filing Dt:
|
10/06/1995
|
|
Title:
|
SUPERSCALAR MICROPROCESSOR ARCHITECTURE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/22/2002
|
Application #:
|
08540349
|
Filing Dt:
|
10/06/1995
|
|
Title:
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EXCEPTION PROCESSING IN SUPERSCALAR MICROPROCESSOR
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|
|
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|
Patent #:
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|
Issue Dt:
|
06/09/1998
|
Application #:
|
08540350
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Filing Dt:
|
10/06/1995
|
|
Title:
|
RISC PROCESSOR HAVING COPROCESSOR FOR EXECUTING CIRCULAR MASK INSTRUCTION
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|
Patent #:
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|
Issue Dt:
|
04/07/1998
|
Application #:
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08540382
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Filing Dt:
|
10/06/1995
|
|
Title:
|
CPU PIPELINE HAVING QUEUING STAGE TO FACILITATE BRANCH INSTRUCTIONS
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|
Patent #:
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|
Issue Dt:
|
01/27/1998
|
Application #:
|
08540714
|
Filing Dt:
|
10/11/1995
|
|
Title:
|
THERMAL MANAGEMENT DEVICE AND METHOD FOR A COMPUTER PROCESSOR
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|
Patent #:
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|
Issue Dt:
|
09/15/1998
|
Application #:
|
08541675
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Filing Dt:
|
10/10/1995
|
|
Title:
|
SYSTEM AND METHOD FOR CODING PARTIAL RESPONSE CHANNELS WITH NOISE PREDICTIVE VITERBI DETECTORS
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|
Patent #:
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|
Issue Dt:
|
02/04/1997
|
Application #:
|
08543740
|
Filing Dt:
|
10/16/1995
|
|
Title:
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HIGH PERFORMANCE VOLTAGE CONTROLLED OSCILLATOR
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|
Patent #:
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|
Issue Dt:
|
08/11/1998
|
Application #:
|
08543767
|
Filing Dt:
|
10/16/1995
|
|
Title:
|
BIST JITTER TOLERANCE MEASUREMENT TECHNIQUE
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|
Patent #:
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|
Issue Dt:
|
09/02/1997
|
Application #:
|
08545462
|
Filing Dt:
|
10/19/1995
|
|
Title:
|
DEFECT ISOLATION USING SCAN-PATH TESTING AND ELECTRON BEAM PROBING IN MULTI-LEVEL HIGH DENSITY ASICS
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|
Patent #:
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|
Issue Dt:
|
09/16/1997
|
Application #:
|
08545879
|
Filing Dt:
|
10/20/1995
|
|
Title:
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METHOD AND APPARATUS FOR TESTING OF SEMICONDUCTOR DEVICES
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|
|
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|
Patent #:
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|
Issue Dt:
|
09/23/1997
|
Application #:
|
08545880
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
APPARATUS AND METHOD FOR MEASURING QUIESCENT CURRENT UTILIZING TIMESET SWITCHING
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|
Patent #:
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|
Issue Dt:
|
05/20/1997
|
Application #:
|
08545954
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
PROCESS FOR PREDICTING PROPAGATION DELAY USING LINEAR INTERPOLATION
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|
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|
Patent #:
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|
Issue Dt:
|
09/23/1997
|
Application #:
|
08546003
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
I/O SYSTEM FOR REDUCING MAIN PROCESSOR OVERHEAD IN INITIATING I/O REQUESTS AND SERVICING I/O COMPLETION EVENTS
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Patent #:
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Issue Dt:
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07/07/1998
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Application #:
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08546861
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Filing Dt:
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10/23/1995
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Title:
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METHODS AND STRUCTURE TO MAINTAIN A TWO LEVEL CACHE IN A RAID CONTROLLER AND THEREBY SELECTING A PREFERRED POSTING METHOD
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Patent #:
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Issue Dt:
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03/25/1997
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Application #:
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08546921
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Filing Dt:
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10/23/1995
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Title:
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PROCESS AND STRUCTURE FOR REDUCTION OF CHANNELING DURING IMPLANTATION OF SOURCE AND DRAIN REGIONS IN FORMATION OF MOS INTEGRATED CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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05/27/1997
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Application #:
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08547038
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Filing Dt:
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10/23/1995
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Title:
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METHOD AND SYSTEM FOR PROVIDING AN INTERLACED IMAGE ON AN DISPLAY
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Patent #:
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Issue Dt:
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02/18/1997
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Application #:
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08547166
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Filing Dt:
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10/24/1995
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Title:
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STRUCTURE AND METHOD FOR A MULTISTANDARD VIDEO ENCODER
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08547177
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Filing Dt:
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10/24/1995
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Title:
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METHOD AND CIRCUIT FOR FETCHING A 2-D REFERENCE PICTURE AREA FROM AN EXTERNAL MEMORY
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Patent #:
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Issue Dt:
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07/15/1997
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Application #:
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08548369
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Filing Dt:
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11/01/1995
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Title:
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SCAN COMPATIBLE 3-STATE BUS CONTROL
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08549383
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Filing Dt:
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10/27/1995
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Title:
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METHODS AND STRUCTURE TO MAINTAIN RAID CONFIGURATION INFORMATION ON DISKS OF THE ARRAY
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08549384
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Filing Dt:
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10/27/1995
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Title:
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APPARATUS AND METHOD FOR ANALYZING AND MODIFYING DATA TRANSFER REQUESTS IN A RAID SYSTEM
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Patent #:
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Issue Dt:
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03/17/1998
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Application #:
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08550922
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Filing Dt:
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10/31/1995
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Title:
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MICROPROCESSOR SHIFTER USING ROTATION AND MASKING OPERATIONS
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Patent #:
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Issue Dt:
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09/23/1997
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Application #:
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08550944
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Filing Dt:
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10/31/1995
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Title:
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MASK DECODER CIRCUIT OPTIMIZED FOR DATA PATH
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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08551303
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Filing Dt:
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10/31/1995
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Title:
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TELEMETRY ENCODING TECHNIQUE FOR SMART STYLUS
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Patent #:
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Issue Dt:
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09/23/1997
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Application #:
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08552461
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Filing Dt:
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11/09/1995
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Title:
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PROCESS FOR MAKING INTEGRATED CIRCUIT STRUCTURE COMPRISING LOCAL AREA INTERCONNECTS FORMED OVER SEMICONDUCTOR SUBSTRATE BY SELECTIVE DEPOSITION ON SEED LAYER IN PATTERNED TRENCH
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Patent #:
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Issue Dt:
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02/17/1998
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Application #:
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08556599
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Filing Dt:
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11/13/1995
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Title:
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ESD PROTECTION FOR DEEP SUBMICRON CMOS DEVICES WITH MINIMUM TRADEOFF FOR LATCHUP BEHAVIOR
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Patent #:
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Issue Dt:
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04/28/1998
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Application #:
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08557721
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Filing Dt:
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11/13/1995
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Title:
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PROCESS FOR FORMING LOW DIELECTRIC CONSTANT LAYERS USING FULLERENES
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Patent #:
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Issue Dt:
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01/27/1998
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Application #:
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08560588
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Filing Dt:
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11/20/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING FUZZY CELL CLUSTERIZATION
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08560834
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Filing Dt:
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11/20/1995
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Title:
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COMPUTER IMPLEMENTED METHOD FOR LEVELING INTERCONNECT WIRING DENSITY IN A CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08560848
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Filing Dt:
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11/20/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING HIGHLY PARALLEL SIEVE OPTIMIZATION WITH MULTIPLE "JIGGLES"
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Patent #:
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Issue Dt:
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07/22/1997
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Application #:
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08561107
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Filing Dt:
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11/21/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR CMOS "NAND" GATE DEVICE
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Patent #:
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Issue Dt:
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06/17/1997
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Application #:
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08565766
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Filing Dt:
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11/30/1995
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Title:
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METAL INTERCONNECT STRUCTURES FOR USE WITH INTEGRATED CIRCUIT DEVICES TO FORM INTEGRATED CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
|
08/05/1997
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Application #:
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08567894
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Filing Dt:
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12/06/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR SEMICONDUCTOR "OR" GATE DEVICE
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Patent #:
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Issue Dt:
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06/30/1998
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Application #:
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08567944
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Filing Dt:
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12/06/1995
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Title:
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ENHANCED BRANCH DELAY SLOT HANDLING WITH SINGLE EXCEPTION PROGRAM COUTER
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Patent #:
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Issue Dt:
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05/20/1997
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Application #:
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08567952
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Filing Dt:
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12/06/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR SEMICONDUCTOR "AND" GATE DEVICE
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Patent #:
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Issue Dt:
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08/24/1999
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Application #:
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08570153
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Filing Dt:
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12/11/1995
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Title:
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A METHOD AND APPARATUS FOR CONTROLLING ACCESS TO A BUS IN A DATA PROCESSING SYSTEM
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|
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Patent #:
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Issue Dt:
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01/07/1997
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Application #:
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08571724
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Filing Dt:
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12/13/1995
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Title:
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OUTPUT BUFFER HAVING TRANSMISSION GATE AND ISOLATED SUPPLY TERMINALS
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|
|
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Patent #:
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|
Issue Dt:
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07/21/1998
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Application #:
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08572665
|
Filing Dt:
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12/14/1995
|
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Title:
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METHOD OF MAKING CMOS DYNAMIC RANDOM-ACCESS MEMORY STRUCTURES AND THE LIKE
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|
|
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08573211
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Filing Dt:
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12/13/1995
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Title:
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APPARATUS FOR DETECTING ELECTRO-MAGNETIC STYLUS SIGNALS BY INDUCING CURRENT INTO A PLURALITY OF SENSOR COILS USING SIGNALS TRANSMITTED BY THE TRANSMITTER COIL OF THE STYLUS
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08573892
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Filing Dt:
|
12/18/1995
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Title:
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SYSTEMS HAVING SHAPED, SELF-ALIGNING MICRO-BUMP STRUCTURES
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|
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Patent #:
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Issue Dt:
|
11/04/1997
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Application #:
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08575793
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Filing Dt:
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12/22/1995
|
|
Title:
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5 VOLT DRIVER IN A 3 VOLT CMOS PROCESS
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/07/1998
|
Application #:
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08578118
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Filing Dt:
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12/27/1995
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|
Title:
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METHOF OF FORMING A HIGH ELECTROMIGRATION RESISTANT METALLIZATION SYSTEM
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