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05/23/2006
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09973153
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10/09/2001
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07/20/2004
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09973267
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10/08/2001
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12/02/2003
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09974008
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10/10/2001
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02/04/2003
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09974251
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10/10/2001
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10/03/2006
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09975293
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10/11/2001
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04/29/2003
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09975871
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10/12/2001
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08/16/2005
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09978141
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10/15/2001
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07/01/2003
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09981154
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10/16/2001
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06/15/2004
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09981200
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10/17/2001
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03/07/2006
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10/17/2001
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07/15/2003
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11/13/2001
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07/15/2003
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09990698
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11/09/2001
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01/28/2003
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11/21/2001
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12/16/2003
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09991187
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11/14/2001
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02/21/2006
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11/14/2001
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09/02/2003
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11/09/2001
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04/26/2005
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11/09/2001
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05/15/2003
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04/15/2003
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09991574
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11/20/2001
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11/05/2002
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09992041
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11/16/2001
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02/28/2006
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11/16/2001
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09/07/2004
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09993015
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11/05/2001
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04/27/2004
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09994082
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11/21/2001
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10/31/2002
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04/15/2003
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09994083
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11/21/2001
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10/18/2005
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11/16/2001
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10/31/2002
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SELECTABLE LOGICAL IDENTIFIER MAPPING
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06/01/2004
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11/26/2001
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02/03/2004
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09994517
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11/27/2001
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05/29/2003
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COMPILED VARIABLE INTERNAL SELF TIME MEMORY
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02/08/2005
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09994556
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11/27/2001
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UNEQUAL ERROR PROTECTION REED-MULLER CODE GENERATOR AND DECODER
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12/30/2003
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09994567
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11/27/2001
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HIGH DENSITY INPUT OUTPUT
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11/09/2004
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09996118
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11/27/2001
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05/25/2004
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09996122
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11/27/2001
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METHODS AND STRUCTURE FOR USING A HIGHER FREQUENCY CLOCK TO SHORTEN A MASTER DELAY LINE
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07/27/2004
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09997071
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11/28/2001
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PROCESS FOR INHIBITING EDGE PEELING OF COATING ON SEMICONDUCTOR SUBSTRATE DURING FORMATION OF INTEGRATED CIRCUIT STRUCTURE THEREON
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06/01/2004
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09997757
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11/30/2001
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ENHANCED FAULT COVERAGE
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07/06/2004
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09997776
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11/30/2001
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06/05/2003
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METHOD AND APPARATUS FOR ACCESSING ROM PCI MEMORY ABOVE 64 K
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02/28/2006
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09997888
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11/29/2001
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DISTRIBUTED DELAY PREDICTION OF MULTI-MILLION GATE DEEP SUB-MICRON ASIC DESIGNS
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02/10/2004
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09997889
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11/30/2001
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10/31/2002
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SYSTEM AND METHOD EMPLOYING A DYNAMIC LOGICAL IDENTIFIER
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12/24/2002
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11/29/2001
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08/31/2004
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09998738
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10/31/2001
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INTEGRATED DYNAMIC LOAD BALANCING BY AN INPUT/OUTPUT INTERFACE
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01/30/2007
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09999330
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10/25/2001
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INTEGER BASED ADAPTIVE ALGORITHM FOR DE-JITTER BUFFER CONTROL
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02/07/2006
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10/31/2001
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11/02/2004
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10/31/2001
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INTEGRATED DYNAMIC MULTIPATHING FILTER
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04/22/2003
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10/24/2001
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CLOCK GATING CELL FOR USE IN A CELL LIBRARY
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05/11/2004
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10/24/2001
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SHALLOW TRENCH ISOLATION STRUCTURE FOR LASER THERMAL PROCESSING
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06/24/2003
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10/19/2001
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12/09/2003
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10/18/2001
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FAST FREE MEMORY ADDRESS CONTROLLER
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05/31/2005
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10000597
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10/24/2001
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05/10/2005
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10001518
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10/30/2001
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12/17/2002
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11/21/2001
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DIRECT ATTACH OF INTERRUPT CONTROLLER TO PROCESSOR MODULE
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12/13/2005
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11/19/2001
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05/22/2003
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MECHANISM FOR ENCODING AND DECODING UPGRADEABLE RPC/XDR STRUCTURES
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04/05/2005
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11/19/2001
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05/22/2003
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09/16/2003
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10002413
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10/23/2001
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LOW TEMPERATURE COEFFICIENT RESISTOR
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11/23/2004
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10002479
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11/15/2001
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12/13/2005
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10002499
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11/02/2001
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03/04/2003
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10002831
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10/26/2001
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PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL
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09/02/2003
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10002981
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10/26/2001
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PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE COMPRISING LAYER OF LOW K DIELECTRIC MATERIAL HAVING ANTIREFLECTIVE PROPERTIES IN AN UPPER SURFACE
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08/13/2002
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10003763
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11/01/2001
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12/23/2003
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10/31/2001
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05/24/2005
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11/01/2001
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MULTIPLE MEMORY SYSTEM SUPPORT THROUGH SEGMENT ASSIGNMENT
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05/20/2003
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11/01/2001
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07/27/2004
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12/03/2001
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09/23/2003
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10005097
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12/05/2001
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01/11/2005
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12/06/2001
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10/26/2004
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11/30/2001
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04/22/2003
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11/30/2001
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02/14/2006
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10007245
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10/22/2001
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01/20/2004
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10007247
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11/01/2001
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03/25/2003
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10007405
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12/04/2001
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PROCESS FOR TREATING POROUS LOW K DIELECTRIC MATERIAL IN DAMASCENE STRUCTURE TO FORM A NON-POROUS DIELECTRIC DIFFUSION BARRIER LAYER ON ETCHED VIA AND TRENCH SURFACES IN THE POROUS LOW K DIELECTRIC MATERIAL
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11/18/2003
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10008089
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11/13/2001
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03/16/2004
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10008170
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Filing Dt:
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10/19/2001
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Title:
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HIGH SPEED LOW NOISE TRANSISTOR
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10011153
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Filing Dt:
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12/05/2001
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Title:
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DSL LINE INTERFACE HAVING LOW-PASS FILTER CHARACTERISTIC WITH REDUCED EXTERNAL COMPONENTS
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10011796
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Filing Dt:
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12/05/2001
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Title:
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LONG PATH AT-SPEED TESTING
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Patent #:
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Issue Dt:
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01/03/2006
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Application #:
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10012257
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Filing Dt:
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11/08/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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WRITE COMPENSATION FOR DATA STORAGE AND COMMUNICATION SYSTEMS
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Patent #:
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Issue Dt:
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07/29/2003
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Application #:
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10012616
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Filing Dt:
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12/12/2001
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Title:
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METHOD AND APPARATUS FOR VARYING TARGET BEHAVIOR IN A SCSI ENVIRONMENT
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Patent #:
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Issue Dt:
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01/01/2008
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Application #:
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10012821
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Filing Dt:
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12/10/2001
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Title:
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REACTOR SYSTEM
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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10012835
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Filing Dt:
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10/22/2001
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Title:
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PROGRAMMABLE READ ONLY MEMORY IN CMOS PROCESS FLOW
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10012847
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Filing Dt:
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12/10/2001
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Title:
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METHOD AND APPARATUS FOR DETECTING PRESENCE OF RESIDUAL POLISHING SLURRY SUBSEQUENT TO POLISHING OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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10012986
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Filing Dt:
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12/05/2001
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Title:
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METHODS AND STRUCTURE FOR READ DATA SYNCHRONIZATION WITH MINIMAL LATENCY
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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10013572
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Filing Dt:
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12/11/2001
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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INTEGRATED INDUCTOR IN SEMICONDUCTOR MANUFACTURING
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10014746
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Filing Dt:
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10/24/2001
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Title:
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GRAPHICAL USER INTERFACE TO INTEGRATE THIRD PARTY TOOLS IN POWER INTEGRITY ANALYSIS
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10015076
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Filing Dt:
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10/26/2001
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Title:
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HARDWARE SEMAPHORES FOR A MULTI-PROCESSOR SYSTEM WITHIN A SHARED MEMORY ARCHITECTURE
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10015181
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Filing Dt:
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11/20/2001
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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METHOD OF REDUCING MISCORRECTIONS IN A POST-PROCESSOR USING COLUMN PARITY CHECKS
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10015194
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Filing Dt:
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11/20/2001
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING A METAMETHODOLOGY
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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10015255
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Filing Dt:
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12/11/2001
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Title:
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CONTROL OF REACTION RATE IN FORMATION OF LOW K CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL USING ORGANOSILANE, UNSUBSTITUTED SILANE, AND HYDROGEN PEROXIDE REACTANTS
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10015506
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Filing Dt:
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12/13/2001
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Publication #:
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Pub Dt:
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06/19/2003
| | | | |
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Title:
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SYSTEM AND METHOD FOR DISABLING AND RECREATING A SNAPSHOT VOLUME
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Patent #:
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Issue Dt:
|
02/10/2004
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Application #:
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10017792
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Filing Dt:
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12/12/2001
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Title:
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OPTIMIZATION OF COMPARATOR ARCHITECTURE
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10017802
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Filing Dt:
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12/12/2001
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Title:
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OPTIMIZATION OF ADDER BASED CIRCUIT ARCHITECTURE
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Patent #:
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Issue Dt:
|
02/03/2004
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Application #:
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10020084
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Filing Dt:
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12/13/2001
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Title:
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ANTI-REFLECTIVE COATINGS FOR USE AT 248 NM AND 193 NM
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10020304
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Filing Dt:
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12/13/2001
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Title:
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BURIED CHANNEL DEVICES AND A PROCESS FOR THEIR FABRICATION SIMULTANEOUSLY WITH SURFACE CHANNEL DEVICES TO PRODUCE TRANSISTORS AND CAPACITORS WITH MULTIPLE ELECTRICAL GATE OXIDES
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Patent #:
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Issue Dt:
|
12/17/2002
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Application #:
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10020327
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Filing Dt:
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12/13/2001
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Title:
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METHOD AND APPARATUS FOR MEASURING THE PHASE OF CAPTURED READ DATA
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Patent #:
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Issue Dt:
|
09/07/2004
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Application #:
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10020407
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Filing Dt:
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12/12/2001
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Title:
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METHOD OF DETECTING SPATIALLY CORRELATED VARIATIONS IN A PARAMETER OF AN INTEGRATED CIRCUIT DIE
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|
|
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Patent #:
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Issue Dt:
|
05/13/2008
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Application #:
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10020764
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Filing Dt:
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12/12/2001
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Title:
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SUBSTRATE LASER MARKING
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Patent #:
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Issue Dt:
|
11/25/2003
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Application #:
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10021414
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Filing Dt:
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10/30/2001
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Title:
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INTERSCALABLE INTERCONNECT
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Patent #:
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Issue Dt:
|
08/30/2005
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Application #:
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10021606
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Filing Dt:
|
12/10/2001
|
|
Title:
|
COMPILER INDEPENDENT BIT-FIELD MACROS
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|
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Patent #:
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Issue Dt:
|
09/14/2004
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Application #:
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10021619
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Filing Dt:
|
10/30/2001
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Title:
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SYSTEM AND METHOD FOR DESIGNING AN INTEGRATED CIRCUIT
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|
|
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Patent #:
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Issue Dt:
|
06/15/2004
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Application #:
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10021696
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Filing Dt:
|
10/30/2001
|
|
Title:
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SYSTEM AND METHOD FOR OPTIMIZING AN INTEGRATED CIRCUIT DESIGN
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|
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Patent #:
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|
Issue Dt:
|
06/03/2003
|
Application #:
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10021829
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Filing Dt:
|
12/12/2001
|
|
Title:
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SUBSTRATE SURFACE SCANNING
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|
|
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Patent #:
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|
Issue Dt:
|
05/31/2005
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Application #:
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10022051
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Filing Dt:
|
12/17/2001
|
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Title:
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METHOD AND APPARATUS FOR PROTECTION OF DATA UTILIZING CRC
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Patent #:
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|
Issue Dt:
|
05/04/2004
|
Application #:
|
10023101
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Filing Dt:
|
12/17/2001
|
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Publication #:
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Pub Dt:
|
06/19/2003
| | | | |
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Title:
|
HARDWARE SPEED SELECTION BEHIND A DISK ARRAY CONTROLLER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/08/2003
|
Application #:
|
10023311
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Filing Dt:
|
12/13/2001
|
|
Title:
|
SYSTEMS AND METHODS FOR PACKAGE DEFECT DETECTION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
10023742
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Filing Dt:
|
12/19/2001
|
|
Title:
|
PROGRAMMABLE BIT ORDERING FOR SERIAL PORT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/03/2004
|
Application #:
|
10024054
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Filing Dt:
|
12/17/2001
|
|
Publication #:
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Pub Dt:
|
06/19/2003
| | | | |
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Title:
|
FLUTED SIGNAL PIN, CAP, MEMBRANE, AND STANCHION FOR A BALL GRID ARRAY
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