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04/11/2006
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10659138
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09/10/2003
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03/10/2005
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11/17/2009
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09/12/2003
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03/17/2005
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03/14/2006
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10661013
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09/12/2003
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03/17/2005
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02/21/2006
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10662188
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09/15/2003
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03/17/2005
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11/18/2008
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10663218
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09/15/2003
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03/17/2005
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06/21/2005
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10664137
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09/17/2003
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03/24/2005
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04/20/2010
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10664636
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09/19/2003
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06/13/2006
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10665927
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09/17/2003
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03/17/2005
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12/04/2007
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10667010
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09/19/2003
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03/24/2005
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08/14/2007
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10667812
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09/22/2003
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03/24/2005
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07/15/2008
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10667911
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09/22/2003
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03/24/2005
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01/29/2008
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10667948
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09/22/2003
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03/24/2005
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07/25/2006
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10668021
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09/22/2003
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03/24/2005
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07/04/2006
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10668875
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09/23/2003
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03/24/2005
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03/11/2008
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10669930
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09/24/2003
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01/20/2005
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07/05/2005
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10671352
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09/25/2003
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03/31/2005
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08/23/2005
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10672125
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09/26/2003
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03/31/2005
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09/17/2013
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10672390
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09/26/2003
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04/14/2005
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Systems and methods for configuring ports of an SAS domain
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11/29/2005
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10672538
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09/26/2003
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03/31/2005
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ROUTING FOR REDUCING IMPEDANCE DISTORTIONS
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07/27/2004
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10672752
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09/25/2003
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04/04/2006
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10673721
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09/29/2003
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04/14/2005
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FUNCTIONALITY BASED PACKAGE DESIGN FOR INTEGRATED CIRCUIT BLOCKS
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11/21/2006
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10674165
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09/29/2003
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03/31/2005
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SINGLE VCO/LOOP FILTER TO CONTROL A WOBBLE AND READ CIRCUIT OF A DVD AND/OR CD RECORDER
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12/27/2005
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10676602
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10/01/2003
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04/21/2005
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SUBSTRATE-BIASED I/O AND POWER ESD PROTECTION CIRCUITS IN DEEP-SUBMICRON TWIN-WELL PROCESS
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01/04/2005
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10676934
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09/30/2003
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Title:
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PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER
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12/07/2004
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10678245
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10/03/2003
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METHOD OF FORMING METAL FUSES IN CMOS PROCESSES WITH COPPER INTERCONNECT
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01/03/2006
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10679004
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10/02/2003
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MECHANISM FOR IMPROVING THE STRUCTURAL INTEGRITY OF LOW-K FILMS
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09/28/2004
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10680047
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10/07/2003
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NONINTRUSIVE WAFER MARKING
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12/06/2005
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10680503
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10/06/2003
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METHOD OF REDUCING PROCESS PLASMA DAMAGE USING OPTICAL SPECTROSCOPY
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09/19/2006
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10681757
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10/08/2003
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04/14/2005
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08/21/2007
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10682012
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10/09/2003
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04/14/2005
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09/02/2008
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10682149
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10/08/2003
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04/28/2005
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10/21/2008
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10682631
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10/09/2003
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01/20/2005
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SUPPORTING MOTION VECTORS OUTSIDE PICTURE BOUNDARIES IN MOTION ESTIMATION PROCESS
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01/11/2005
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10684119
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10/10/2003
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04/29/2004
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IDDQ TEST METHODOLOGY BASED ON THE SENSITIVITY OF FAULT CURRENT TO POWER SUPPLY VARIATIONS
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01/17/2006
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10684733
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10/14/2003
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04/14/2005
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04/17/2007
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10685987
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10/15/2003
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04/21/2005
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06/13/2006
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10687991
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10/17/2003
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04/21/2005
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PAGE BOUNDARY DETECTOR
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08/30/2005
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10688023
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10/16/2003
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INTEGRATED NAND AND NOR-TYPE FLASH MEMORY DEVICE AND METHOD OF USING THE SAME
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09/19/2006
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10688460
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10/17/2003
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04/21/2005
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PROCESS AND APPARATUS FOR FAST ASSIGNMENT OF OBJECTS TO A RECTANGLE
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06/21/2005
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10690861
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10/22/2003
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04/28/2005
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COMPLIMENTARY METAL OXIDE SEMICONDUCTOR CAPACITOR AND METHOD FOR MAKING SAME
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01/29/2008
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10690884
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10/22/2003
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01/20/2005
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LOW COMPLEXITY BLOCK SIZE DECISION FOR VARIABLE BLOCK SIZE MOTION ESTIMATION
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02/14/2006
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10691078
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10/21/2003
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04/29/2004
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TURBO DECODING
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06/14/2005
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10691400
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10/22/2003
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04/28/2005
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ULTRA LOW DIELECTRIC CONSTANT THIN FILM
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03/22/2005
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10691938
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10/23/2003
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04/04/2006
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10692091
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10/23/2003
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MEMORY MODULE HAVING MIRRORED PLACEMENT OF DRAM INTEGRATED CIRCUITS UPON A FOUR-LAYER PRINTED CIRCUIT BOARD
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02/20/2007
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10692664
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10/23/2003
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04/28/2005
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FIFO MEMORY WITH SINGLE PORT MEMORY MODULES FOR ALLOWING SIMULTANEOUS READ AND WRITE OPERATIONS
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09/19/2006
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10693075
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10/23/2003
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04/28/2005
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COMPARISON OF TWO HIERARCHICAL NETLIST TO GENERATE CHANGE ORDERS FOR UPDATING AN INTEGRATED CIRCUIT LAYOUT
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05/17/2005
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10693078
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10/23/2003
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04/28/2005
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DAISY CHAIN GANG TESTING
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08/09/2005
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10693110
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10/24/2003
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04/28/2005
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CHEMICAL MECHANICAL ELECTROPOLISHING SYSTEM
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04/25/2006
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10694208
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10/27/2003
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04/28/2005
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PROCESS AND APPARATUS FOR PLACEMENT OF CELLS IN AN IC DURING FLOORPLAN CREATION
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12/20/2005
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10695929
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10/28/2003
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04/28/2005
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CMOS ISOLATION CELL FOR EMBEDDED MEMORY IN POWER FAILURE ENVIRONMENTS
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06/13/2006
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10696105
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10/29/2003
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05/05/2005
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GATE REUSE METHODOLOGY FOR DIFFUSED CELL-BASED IP BLOCKS IN PLATFORM-BASED SILICON PRODUCTS
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09/26/2006
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10696203
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10/29/2003
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05/05/2005
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PROCESS YIELD LEARNING
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03/13/2007
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10696320
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10/29/2003
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05/05/2005
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NEW METHODOLOGY TO MEASURE MANY MORE TRANSISTORS ON THE SAME TEST AREA
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03/10/2009
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10696912
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10/30/2003
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05/05/2005
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OPTIMIZED INTERLEAVER AND/OR DEINTERLEAVER DESIGN
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09/12/2006
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10697357
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10/29/2003
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05/05/2005
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METHOD OF PARTITIONING AN INTEGRATED CIRCUIT DESIGN FOR PHYSICAL DESIGN VERIFICATION
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04/11/2006
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10697446
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10/29/2003
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Title:
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METHOD OF FORMING AN ANTIFUSE ON A SEMICONDUCTOR SUBSTRATE USING WET OXIDATION OF A NITRIDED SUBSTRATE
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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10697506
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Filing Dt:
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10/29/2003
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Title:
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METHOD OF VAPORIZING AND IONIZING METALS FOR USE IN SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10697507
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Filing Dt:
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10/29/2003
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Title:
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VAPORIZATION AND IONIZATION OF METALS FOR USE IN SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10698167
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Filing Dt:
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10/30/2003
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Title:
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CALCIUM DOPED POLYSILICON GATE ELECTRODES
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10698169
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Filing Dt:
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10/31/2003
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Title:
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MEMORY DEVICE HAVING AN ELECTRON TRAPPING LAYER IN A HIGH-K DIELECTRIC GATE STACK
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10699276
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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MIXED LVR AND HVR RETICLE SET DESIGN FOR THE PROCESSING OF GATE ARRAYS, EMBEDDED ARRAYS AND RAPID CHIP PRODUCTS
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Patent #:
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Issue Dt:
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05/19/2009
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Application #:
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10700177
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Filing Dt:
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11/03/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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NEW HARD BISR SCHEME ALLOWING FIELD REPAIR AND USAGE OF RELIABILITY CONTROLLER
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10700790
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Filing Dt:
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11/03/2003
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Title:
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VDD OVER AND UNDERVOLTAGE MEASUREMENT TECHNIQUES USING MONITOR CELLS
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10700791
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Filing Dt:
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11/03/2003
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Title:
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METHOD FOR TESTING IDD AT MULTIPLE VOLTAGES
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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10701019
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Filing Dt:
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11/03/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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HDD FIRMWARE DOWNLOAD
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10701328
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Filing Dt:
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11/03/2003
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Title:
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METHOD FOR PERFORMING STATISTICAL POST PROCESSING IN SEMICONDCTOR MANUFACTRING USING ID CELLS
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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10701332
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Filing Dt:
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11/04/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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NOVEL BISR MODE TO TEST THE REDUNDANT ELEMENTS AND REGULAR FUNCTIONAL MEMORY TO AVOID TEST ESCAPES
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Patent #:
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Issue Dt:
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07/10/2007
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Application #:
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10701639
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Filing Dt:
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11/05/2003
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Title:
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LOW POWER MEMORY CONTROLLER THAT IS ADAPTABLE TO EITHER DOUBLE DATA RATE DRAM OR SINGLE DATA RATE SYNCHRONOUS DRAM CIRCUITS
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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10702165
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Filing Dt:
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11/04/2003
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Title:
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THIN FILM CMOS CALIBRATION STANDARD HAVING PROTECTIVE COVER LAYER
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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10702996
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Filing Dt:
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11/05/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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SEMICONDUCTOR PACKAGE HAVING DISCRETE NON-ACTIVE ELECTRICAL COMPONENTS INCORPORATED INTO THE PACKAGE
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10704040
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Filing Dt:
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11/07/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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DECENTRALIZED VEHICULAR TRAFFIC STATUS SYSTEM
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10704922
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Filing Dt:
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11/10/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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METHOD OF GENERATING A SCHEMATIC DRIVEN LAYOUT FOR A HIERARCHICAL INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10705638
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Filing Dt:
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11/10/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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LOW-IMPACT ANALYZER INTERFACE
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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10706110
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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METAL PROGRAMMABLE SELF-TIMED MEMORIES
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10706120
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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LOW VOLTAGE BREAKDOWN ELEMENT FOR ESD TRIGGER DEVICE
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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10706127
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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METHODOLOGY FOR DEBUGGING RTL SIMULATIONS OF PROCESSOR BASED SYSTEM ON CHIP
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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10706623
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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SERIAL PORT INITIALIZATION IN STORAGE SYSTEM CONTROLLERS
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Patent #:
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Issue Dt:
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08/17/2010
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Application #:
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10710772
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Filing Dt:
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08/02/2004
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Title:
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QUEUING SYSTEM WITH MECHANISM TO LIMIT BLOCKING OF HIGH-PRIORITY PACKETS
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Patent #:
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Issue Dt:
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01/20/2009
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Application #:
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10711783
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Filing Dt:
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10/05/2004
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Title:
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METHOD AND SYSTEM FOR ENFORCING HARDWARE/SOFTWARE COMPATIBILITY CONSTRAINTS
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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10713492
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Filing Dt:
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11/14/2003
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Publication #:
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Pub Dt:
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05/19/2005
| | | | |
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Title:
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FLEXIBLE DESIGN FOR MEMORY USE IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/23/2007
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Application #:
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10713951
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Filing Dt:
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11/14/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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INTEGRATED CIRCUIT CARRIER APPARATUS METHOD AND SYSTEM
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Patent #:
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Issue Dt:
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11/18/2008
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Application #:
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10714712
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Filing Dt:
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11/17/2003
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Publication #:
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Pub Dt:
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01/20/2005
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Title:
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HIGH QUALITY, LOW MEMORY BANDWIDTH MOTION ESTIMATION PROCESSOR
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Patent #:
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Issue Dt:
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10/13/2009
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Application #:
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10714736
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Filing Dt:
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11/17/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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ADAPTIVE REFERENCE PICTURE SELECTION BASED ON INTER-PICTURE MOTION MEASUREMENT
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10715063
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Filing Dt:
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11/17/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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PIPELINE SCSI NEXUS ASSOCIATIVITY CIRCUIT
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10715929
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Filing Dt:
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11/18/2003
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Title:
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MEMORY CELL ARCHITECTURE FOR REDUCED ROUTING CONGESTION
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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10716222
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Filing Dt:
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11/18/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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DEVICE WITH VIRTUAL TILIZED IMAGE MEMORY
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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10716259
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Filing Dt:
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11/18/2003
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Title:
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MEMORY CELL ARCHITECTURE
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10716263
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Filing Dt:
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11/18/2003
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Title:
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METHOD AND APPARATUS FOR REPLACING A DEFECTIVE CELL WITHIN A MEMORY DEVICE HAVING TWISTED BIT LINES
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10717083
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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CROSS SWITCH SUPPORTING SIMULTANEOUS DATA TRAFFIC IN OPPOSING DIRECTIONS
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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10718286
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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METHODOLOGY FOR PERFORMING REGISTER READ/WRITES TO TWO OR MORE EXPANDERS WITH A COMMON TEST PORT
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10718291
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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METHOD OF GENERATING A PHYSICAL NETLIST FOR A HIERARCHICAL INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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10718824
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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REFLECTIVITY OPTIMIZATION FOR MULTILAYER STACKS
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10718829
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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ANALYSIS OF INTEGRATED CIRCUITS FOR HIGH FREQUENCY PERFORMANCE
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Patent #:
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Issue Dt:
|
06/26/2007
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Application #:
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10718937
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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SYSTEM FOR IMPROVING PCI WRITE PERFORMANCE
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10719393
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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PROCESS AND APPARATUS FOR PLACEMENT OF MEGACELLS IN ICS DESIGN
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10719787
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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METHOD AND APPARATUS FOR FINDING OPTIMAL UNIFICATION SUBSTITUTION FOR FORMULAS IN TECHNOLOGY LIBRARY
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Patent #:
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Issue Dt:
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05/15/2007
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Application #:
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10719878
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Filing Dt:
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11/21/2003
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Title:
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DEVICE AND METHOD FOR USING A LESSENED LOAD TO MEASURE SIGNAL SKEW AT THE OUTPUT OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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10720360
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Filing Dt:
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11/24/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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METHOD AND/OR CIRCUIT FOR IMPLEMENTING A ZOOM IN A VIDEO SIGNAL
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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10720783
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Filing Dt:
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11/24/2003
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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GRAPHICAL SYMBOLS FOR H.264 BITSTREAM SYNTAX ELEMENTS
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10721843
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Filing Dt:
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11/25/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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PROGRAMMABLE PHASE-LOCKED LOOP
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