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Patent Assignment Details
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Reel/Frame:035507/0851   Pages: 68
Recorded: 04/27/2015
Attorney Dkt #:100353.00379
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 123
Page 2 of 2
Pages: 1 2
1
Patent #:
7165159
Issue Dt:
01/16/2007
Application #:
10687591
Filing Dt:
10/20/2003
Publication #:
US20040062126
Pub Dt:
04/01/2004
Title:
MEMORY SYSTEM
2
Patent #:
6972493
Issue Dt:
12/06/2005
Application #:
10694997
Filing Dt:
10/29/2003
Publication #:
US20040061140
Pub Dt:
04/01/2004
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING REDUCED CROSS-TALK NOISE
3
Patent #:
6962863
Issue Dt:
11/08/2005
Application #:
10704684
Filing Dt:
11/12/2003
Publication #:
US20040104485
Pub Dt:
06/03/2004
Title:
SEMICONDUCTOR DEVICE HAVING INTERCONNECTION LAYER WITH MULTIPLY LAYERED SIDEWALL INSULATION FILM
4
Patent #:
7724689
Issue Dt:
05/25/2010
Application #:
10725587
Filing Dt:
12/03/2003
Publication #:
US20050117511
Pub Dt:
06/02/2005
Title:
INTERFACE DEVICE AND INTERFACE DEVICE CONTROL METHOD
5
Patent #:
6949409
Issue Dt:
09/27/2005
Application #:
10772268
Filing Dt:
02/06/2004
Publication #:
US20040158700
Pub Dt:
08/12/2004
Title:
REGISTER SETTING METHOD AND SEMICONDUCTOR DEVICE
6
Patent #:
7521349
Issue Dt:
04/21/2009
Application #:
10873223
Filing Dt:
06/23/2004
Publication #:
US20040222442
Pub Dt:
11/11/2004
Title:
FUNDAMENTAL CELL, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, WIRING METHOD AND WIRING APPARATUS
7
Patent #:
7361975
Issue Dt:
04/22/2008
Application #:
10914141
Filing Dt:
08/10/2004
Publication #:
US20050006780
Pub Dt:
01/13/2005
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING REDUCED CROSS-TALK NOISE
8
Patent #:
7339250
Issue Dt:
03/04/2008
Application #:
10914163
Filing Dt:
08/10/2004
Publication #:
US20050006781
Pub Dt:
01/13/2005
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING REDUCED CROSS-TALK NOISE
9
Patent #:
7317241
Issue Dt:
01/08/2008
Application #:
11143649
Filing Dt:
06/03/2005
Publication #:
US20050218432
Pub Dt:
10/06/2005
Title:
SEMICONDUCTOR APPARATUS HAVING A LARGE-SIZE BUS CONNECTION
10
Patent #:
7304487
Issue Dt:
12/04/2007
Application #:
11247245
Filing Dt:
10/12/2005
Publication #:
US20060028223
Pub Dt:
02/09/2006
Title:
TEST METHOD OF SEMICONDUCTOR DEVICES
11
Patent #:
7474143
Issue Dt:
01/06/2009
Application #:
11480904
Filing Dt:
07/06/2006
Publication #:
US20060250176
Pub Dt:
11/09/2006
Title:
VOLTAGE GENERATOR CIRCUIT AND METHOD FOR CONTROLLING THEREOF
12
Patent #:
8886897
Issue Dt:
11/11/2014
Application #:
11505835
Filing Dt:
08/18/2006
Publication #:
US20060282608
Pub Dt:
12/14/2006
Title:
Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
13
Patent #:
7386659
Issue Dt:
06/10/2008
Application #:
11505837
Filing Dt:
08/18/2006
Publication #:
US20060282581
Pub Dt:
12/14/2006
Title:
MEMORY SYSTEM
14
Patent #:
7370141
Issue Dt:
05/06/2008
Application #:
11505838
Filing Dt:
08/18/2006
Publication #:
US20060282582
Pub Dt:
12/14/2006
Title:
MEMORY SYSTEM
15
Patent #:
7911825
Issue Dt:
03/22/2011
Application #:
11512319
Filing Dt:
08/30/2006
Publication #:
US20060294322
Pub Dt:
12/28/2006
Title:
MULTI-PORT MEMORY BASED ON DRAM CORE
16
Patent #:
7734973
Issue Dt:
06/08/2010
Application #:
11647363
Filing Dt:
12/29/2006
Publication #:
US20070168816
Pub Dt:
07/19/2007
Title:
TESTING APPARATUS AND TESTING METHOD FOR AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT
17
Patent #:
7907434
Issue Dt:
03/15/2011
Application #:
11984932
Filing Dt:
11/26/2007
Publication #:
US20080142847
Pub Dt:
06/19/2008
Title:
SEMICONDUCTOR APPARATUS HAVING A LARGE-SIZE BUS CONNECTION
18
Patent #:
7913212
Issue Dt:
03/22/2011
Application #:
12071845
Filing Dt:
02/27/2008
Publication #:
US20080301610
Pub Dt:
12/04/2008
Title:
METHOD FOR DETERMINING A LENGTH OF SHIELDING OF A SEMICONDUCTOR INTEGRATED CIRCUIT WIRING
19
Patent #:
8683165
Issue Dt:
03/25/2014
Application #:
12631240
Filing Dt:
12/04/2009
Publication #:
US20100146171
Pub Dt:
06/10/2010
Title:
MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS
20
Patent #:
8312240
Issue Dt:
11/13/2012
Application #:
12631288
Filing Dt:
12/04/2009
Publication #:
US20100146196
Pub Dt:
06/10/2010
Title:
MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS
21
Patent #:
8547776
Issue Dt:
10/01/2013
Application #:
13031080
Filing Dt:
02/18/2011
Publication #:
US20110141795
Pub Dt:
06/16/2011
Title:
MULTI-PORT MEMORY BASED ON DRAM CORE
22
Patent #:
8717842
Issue Dt:
05/06/2014
Application #:
13601406
Filing Dt:
08/31/2012
Publication #:
US20130201751
Pub Dt:
08/08/2013
Title:
MULTI-PORT MEMORY BASED ON DRAM CORE
23
Patent #:
8687456
Issue Dt:
04/01/2014
Application #:
13601475
Filing Dt:
08/31/2012
Publication #:
US20130205100
Pub Dt:
08/08/2013
Title:
MULTI-PORT MEMORY BASED ON DRAM CORE
Assignor
1
FUJITSU SEMICONDUCTOR LIMITED
Exec Dt:
03/02/2015
Assignee
1
SOCIONEXT INC.
2-10-23 SHIN-YOKOHAMA, KOHOKU-KU
YOKOHAMA-SHI, KANAGAWA, JAPAN 222-0033
Correspondence name and address
ARENT FOX LLP
1717 K STREET, N.W.
WASHINGTON, DC 20006

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