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Patent #:
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Issue Dt:
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08/04/2009
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Application #:
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11261873
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Filing Dt:
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10/28/2005
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Publication #:
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Pub Dt:
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05/03/2007
| | | | |
Title:
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INTEGRATED CIRCUIT USING COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR AND MOS TRANSISTOR IN SILICON AND SILICON ALLOYS
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Patent #:
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Issue Dt:
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07/14/2009
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Application #:
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11450112
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Filing Dt:
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06/09/2006
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Publication #:
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Pub Dt:
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12/13/2007
| | | | |
Title:
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SELF ALIGNED GATE JFET STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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11451886
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Filing Dt:
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06/12/2006
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Publication #:
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Pub Dt:
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12/13/2007
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Title:
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SCALABLE PROCESS AND STRUCTURE FOR JFET FOR SMALL AND DECREASING LINE WIDTHS
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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11452442
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Filing Dt:
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06/13/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
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CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL JFET DEVICES
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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11484402
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Filing Dt:
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07/11/2006
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Publication #:
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Pub Dt:
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01/17/2008
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Title:
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OXIDE ISOLATED METAL SILICON-GATE JFET
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Patent #:
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Issue Dt:
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01/12/2010
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Application #:
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11495908
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
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LEVEL SHIFTING CIRCUIT HAVING JUNCTION FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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07/07/2009
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Application #:
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11502172
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Filing Dt:
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08/10/2006
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Publication #:
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Pub Dt:
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02/14/2008
| | | | |
Title:
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JFET WITH BUILT IN BACK GATE IN EITHER SOI OR BULK SILICON
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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11515252
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Filing Dt:
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09/01/2006
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Publication #:
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Pub Dt:
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02/21/2008
| | | | |
Title:
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JUNCTION FIELD EFFECT TRANSISTOR INPUT BUFFER LEVEL SHIFTING CIRCUIT
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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11590265
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Filing Dt:
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10/31/2006
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Publication #:
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Pub Dt:
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05/01/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE, DESIGN METHOD AND STRUCTURE
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Patent #:
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Issue Dt:
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01/06/2009
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Application #:
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11635004
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Filing Dt:
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12/07/2006
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Publication #:
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Pub Dt:
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06/07/2007
| | | | |
Title:
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METHOD OF PRODUCING AND OPERATING A LOW POWER JUNCTION FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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04/06/2010
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Application #:
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11693441
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Filing Dt:
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03/29/2007
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Publication #:
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Pub Dt:
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10/02/2008
| | | | |
Title:
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SYSTEM AND METHOD FOR DETECTING MULTIPLE MATCHES
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Patent #:
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Issue Dt:
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01/12/2010
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Application #:
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11743973
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Filing Dt:
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05/03/2007
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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TRANSISTOR PROVIDING DIFFERENT THRESHOLD VOLTAGES AND METHOD OF FABRICATION THEREOF
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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11744080
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Filing Dt:
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05/03/2007
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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JFET DEVICE WITH IMPROVED OFF-STATE LEAKAGE CURRENT AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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11744120
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Filing Dt:
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05/03/2007
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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JFET DEVICE WITH VIRTUAL SOURCE AND DRAIN LINK REGIONS AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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11/18/2008
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Application #:
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11744617
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Filing Dt:
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05/04/2007
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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METHOD FOR APPLYING A STRESS LAYER TO A SEMICONDUCTOR DEVICE AND DEVICE FORMED THEREFROM
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11744660
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Filing Dt:
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05/04/2007
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING STRAIN-INDUCING SUBSTRATE AND FABRICATION METHODS THEREOF
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Patent #:
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Issue Dt:
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06/01/2010
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Application #:
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11799305
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Filing Dt:
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05/01/2007
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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CONTENT ADDRESSABLE MEMORY CELL INCLUDING A JUNCTION FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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06/01/2010
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Application #:
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11799571
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Filing Dt:
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05/01/2007
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Publication #:
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Pub Dt:
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11/06/2008
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Title:
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IMAGE SENSING CELL, DEVICE, METHOD OF OPERATION, AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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04/06/2010
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Application #:
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11799572
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Filing Dt:
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05/01/2007
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE STORAGE CELL STRUCTURE, METHOD OF OPERATION, AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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11804132
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Filing Dt:
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05/17/2007
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Publication #:
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Pub Dt:
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11/20/2008
| | | | |
Title:
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JUNCTION FIELD EFFECT DYNAMIC RANDOM ACCESS MEMORY CELL AND CONTENT ADDRESSABLE MEMORY CELL
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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11818388
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Filing Dt:
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06/14/2007
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Publication #:
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Pub Dt:
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12/18/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING A BIAS VOLTAGE GENERATOR
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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11824737
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Filing Dt:
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07/02/2007
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Publication #:
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Pub Dt:
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01/08/2009
| | | | |
Title:
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COMMON DATA LINE SIGNALING AND METHOD
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Patent #:
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Issue Dt:
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12/08/2009
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Application #:
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11888977
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Filing Dt:
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08/03/2007
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Publication #:
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|
Pub Dt:
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02/05/2009
| | | | |
Title:
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SWITCHING CIRCUITS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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07/27/2010
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Application #:
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11903296
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Filing Dt:
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09/21/2007
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Publication #:
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|
Pub Dt:
|
04/03/2008
| | | | |
Title:
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CIRCUIT AND METHOD FOR GENERATING ELECTRICAL SOLITONS WITH JUNCTION FIELD EFFECT TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
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Application #:
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11958032
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Filing Dt:
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12/17/2007
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Publication #:
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Pub Dt:
|
06/18/2009
| | | | |
Title:
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SWAPPED-BODY RAM ARCHITECTURE
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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11960452
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Filing Dt:
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12/19/2007
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Publication #:
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Pub Dt:
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06/25/2009
| | | | |
Title:
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SYSTEM AND METHOD FOR ROUTING CONNECTIONS
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Patent #:
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|
Issue Dt:
|
01/19/2010
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Application #:
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12033487
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Filing Dt:
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02/19/2008
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Publication #:
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|
Pub Dt:
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08/20/2009
| | | | |
Title:
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METHOD TO FABRICATE GATE ELECTRODES
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Patent #:
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Issue Dt:
|
07/05/2011
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Application #:
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12113118
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Filing Dt:
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04/30/2008
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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DOUBLE GATE JFET WITH REDUCED AREA CONSUMPTION AND FABRICATION METHOD THEREFOR
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Patent #:
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|
Issue Dt:
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08/10/2010
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Application #:
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12114183
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Filing Dt:
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05/02/2008
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Publication #:
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Pub Dt:
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11/06/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE AND FABRICATION METHOD THEREOF
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|
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Patent #:
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|
Issue Dt:
|
10/18/2011
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Application #:
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12115991
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Filing Dt:
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05/06/2008
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Publication #:
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Pub Dt:
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11/12/2009
| | | | |
Title:
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SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS
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|
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Patent #:
|
|
Issue Dt:
|
05/04/2010
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Application #:
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12156565
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Filing Dt:
|
06/02/2008
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Publication #:
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|
Pub Dt:
|
12/03/2009
| | | | |
Title:
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PROGRAMMABLE SWITCH CIRCUIT AND METHOD, METHOD OF MANUFACTURE, AND DEVICES AND SYSTEMS INCLUDING THE SAME
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Patent #:
|
|
Issue Dt:
|
07/06/2010
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Application #:
|
12171906
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Filing Dt:
|
07/11/2008
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Title:
|
VOLTAGE-LEVEL TRANSLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
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Application #:
|
12173405
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Filing Dt:
|
07/15/2008
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Title:
|
CURRENT-LIMITED OUTPUT BUFFER
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|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
12178291
|
Filing Dt:
|
07/23/2008
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Title:
|
SEMICONDUCTOR DEVICE HAVING STRAIN-INDUCING SUBSTRATE AND FABRICATION METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
12178404
|
Filing Dt:
|
07/23/2008
|
Title:
|
JFET DEVICE WITH IMPROVED OFF-STATE LEAKAGE CURRENT AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12180158
|
Filing Dt:
|
07/25/2008
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Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
Title:
|
JUNCTION FIELD EFFECT TRANSISTOR USING A SILICON ON INSULATOR ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12194651
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Filing Dt:
|
08/20/2008
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Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY HAVING JUNCTION FIELD EFFECT TRANSISTOR CELL ACCESS DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
12195725
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Filing Dt:
|
08/21/2008
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Title:
|
LEVEL-SHIFTING CIRCUIT WITH BIPOLAR JUNCTION TRANSISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
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Application #:
|
12235164
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Filing Dt:
|
09/22/2008
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Publication #:
|
|
Pub Dt:
|
01/15/2009
| | | | |
Title:
|
SELF ALIGNED GATE JFET STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
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Application #:
|
12263854
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Filing Dt:
|
11/03/2008
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Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT USING COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR AND MOS TRANSISTOR IN SILICON AND SILICON ALLOYS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
12270964
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Filing Dt:
|
11/14/2008
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Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
Title:
|
JFET WITH BUILT IN BACK GATE IN EITHER SOI OR BULK SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12276574
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Filing Dt:
|
11/24/2008
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Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
Title:
|
METHOD OF FORMING AN OXIDE ISOLATED METAL SILICON-GATE JFET
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|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
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Application #:
|
12284037
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Filing Dt:
|
09/18/2008
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Title:
|
MEMORY CELL INCLUDING AN EMITTER FOLLOWER AND EMITTER FOLLOWER SENSING SCHEME AND METHOD OF READING DATA THEREFROM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
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Application #:
|
12316944
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Filing Dt:
|
12/17/2008
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Title:
|
JUNCTION FIELD EFFECT TRANSISTOR (JFET) STRUCTURE HAVING TOP-TO-BOTTOM GATE TIE AND METHOD OF MANUFACTURE
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|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
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Application #:
|
12326415
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Filing Dt:
|
12/02/2008
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Publication #:
|
|
Pub Dt:
|
06/03/2010
| | | | |
Title:
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A METHOD FOR MANUFACTURING A JUNCTION FIELD EFFECT TRANSISTOR HAVING A DOUBLE GATE
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|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
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Application #:
|
12339584
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Filing Dt:
|
12/19/2008
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Title:
|
METHOD AND APPARATUS FOR IMPROVING SRAM WRITE OPERATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
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Application #:
|
12339618
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Filing Dt:
|
12/19/2008
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Title:
|
METHOD AND APPARATUS FOR IMPROVING SRAM WRITE OPERATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
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Application #:
|
12349747
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Filing Dt:
|
01/07/2009
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Title:
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ADVANCED JFET WITH RELIABLE CHANNEL CONTROL AND METHOD OF MANUFACTURE
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|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
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Application #:
|
12363796
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Filing Dt:
|
02/02/2009
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Publication #:
|
|
Pub Dt:
|
05/28/2009
| | | | |
Title:
|
TRANSISTOR PROVIDING DIFFERENT THRESHOLD VOLTAGES AND METHOD OF FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12366791
|
Filing Dt:
|
02/06/2009
|
Title:
|
SEMICONDUCTOR DEVICE WITH MULTIPLE TRANSISTORS FORMED IN A PARTIALLY DEPLETED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12369169
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Filing Dt:
|
02/11/2009
|
Title:
|
METHOD FOR PROVIDING TEMPERATURE UNIFORMITY OF RAPID THERMAL ANNEALING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12380490
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Filing Dt:
|
02/26/2009
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Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
SEMICONDUCTOR DEVICE, DESIGN METHOD AND STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
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Application #:
|
12380497
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Filing Dt:
|
02/26/2009
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Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
Title:
|
SEMICONDUCTOR DEVICE, DESIGN METHOD AND STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12492320
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Filing Dt:
|
06/26/2009
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT USING COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR AND MOS TRANSISTOR IN SILICON AND SILICON ALLOYS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
12506848
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Filing Dt:
|
07/21/2009
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Publication #:
|
|
Pub Dt:
|
11/12/2009
| | | | |
Title:
|
CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL JFET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
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Application #:
|
12708497
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Filing Dt:
|
02/18/2010
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Publication #:
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Pub Dt:
|
03/31/2011
| | | | |
Title:
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ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME
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Patent #:
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Issue Dt:
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07/26/2011
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Application #:
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12861659
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Filing Dt:
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08/23/2010
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Publication #:
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Pub Dt:
|
12/16/2010
| | | | |
Title:
|
CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL DEVICES
|
|
|
Patent #:
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|
Issue Dt:
|
02/19/2013
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Application #:
|
12895657
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Filing Dt:
|
09/30/2010
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Publication #:
|
|
Pub Dt:
|
04/05/2012
| | | | |
Title:
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METHOD FOR MINIMIZING DEFECTS IN A SEMICONDUCTOR SUBSTRATE DUE TO ION IMPLANTATION
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|
|
Patent #:
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|
Issue Dt:
|
02/19/2013
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Application #:
|
12895695
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Filing Dt:
|
09/30/2010
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Publication #:
|
|
Pub Dt:
|
04/05/2012
| | | | |
Title:
|
METHOD FOR REDUCING PUNCH-THROUGH IN A TRANSISTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
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Application #:
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12895730
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Filing Dt:
|
09/30/2010
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Publication #:
|
|
Pub Dt:
|
04/05/2012
| | | | |
Title:
|
METHOD FOR MINIMIZING DEFECTS IN A SEMICONDUCTOR SUBSTRATE DUE TO ION IMPLANTATION
|
|
|
Patent #:
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NONE
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Issue Dt:
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Application #:
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12895785
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09/30/2010
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04/07/2011
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04/16/2013
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09/30/2010
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05/26/2011
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12/22/2011
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03/26/2013
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12960289
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06/07/2012
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09/10/2013
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12/17/2010
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10/13/2011
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06/24/2014
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12/17/2010
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12/22/2011
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06/11/2013
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09/03/2013
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03/03/2011
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09/06/2012
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03/19/2013
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13071399
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03/24/2011
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09/27/2012
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03/31/2015
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06/23/2011
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12/27/2012
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09/11/2012
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13218600
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08/26/2011
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12/15/2011
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12/03/2013
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12/23/2011
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08/02/2016
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02/28/2012
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01/14/2014
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04/30/2012
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04/07/2015
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05/11/2012
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08/05/2014
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05/11/2012
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08/19/2014
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05/14/2012
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10/29/2013
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05/16/2012
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07/15/2014
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05/29/2012
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05/27/2014
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06/06/2012
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09/24/2013
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07/19/2012
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11/29/2012
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06/10/2014
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07/20/2012
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ANALOG TRANSISTOR
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06/10/2014
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13559554
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07/26/2012
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12/24/2013
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08/22/2012
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CMOS STRUCTURES AND PROCESSES BASED ON SELECTIVE THINNING
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02/04/2014
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13592122
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08/22/2012
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01/28/2014
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13600647
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08/31/2012
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SEMICONDUCTOR STRUCTURE WITH REDUCED JUNCTION LEAKAGE AND METHOD OF FABRICATION THEREOF
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12/10/2013
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13616053
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09/14/2012
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01/24/2013
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ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME
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12/10/2013
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13616859
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09/14/2012
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01/24/2013
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ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME
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04/29/2014
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13621698
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09/17/2012
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08/18/2015
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13622194
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09/18/2012
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02/18/2014
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13624449
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09/21/2012
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MULTIPLE TRANSISTOR TYPES FORMED IN A COMMON EPITAXIAL LAYER BY DIFFERENTIAL OUT-DIFFUSION FROM A DOPED UNDERLAYER
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01/12/2016
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13646506
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10/05/2012
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08/26/2014
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13668063
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11/02/2012
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11/25/2014
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13708983
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12/08/2012
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08/26/2014
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13716080
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12/14/2012
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11/11/2014
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13725152
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12/21/2012
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03/03/2015
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01/22/2013
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11/04/2014
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13748418
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01/23/2013
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PROCESS FOR MANUFACTURE OF INTEGRATED CIRCUITS WITH DIFFERENT CHANNEL DOPING TRANSISTOR ARCHITECTURES AND DEVICES THEREFROM
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07/28/2015
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01/31/2013
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Integrated Circuits Having a Plurality of High-K Metal Gate FETs with Various Combinations of Channel Foundation Structure and Gate Stack Structure and Methods of Making Same
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10/22/2013
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13770313
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02/19/2013
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06/27/2013
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SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS
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