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Patent Assignment Details
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Reel/Frame:035623/0001   Pages: 181
Recorded: 05/08/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 4024
Page 11 of 41
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
1
Patent #:
6473335
Issue Dt:
10/29/2002
Application #:
09898222
Filing Dt:
07/03/2001
Publication #:
US20020003720
Pub Dt:
01/10/2002
Title:
MRAM CONFIGURATION
2
Patent #:
6504751
Issue Dt:
01/07/2003
Application #:
09898224
Filing Dt:
07/03/2001
Publication #:
US20020001224
Pub Dt:
01/03/2002
Title:
INTEGRATED MEMORY HAVING MEMORY CELLS WITH A MAGNETORESISTIVE STORAGE PROPERTY AND METHOD OF OPERATING SUCH A MEMORY
3
Patent #:
6456553
Issue Dt:
09/24/2002
Application #:
09898233
Filing Dt:
07/03/2001
Publication #:
US20020053944
Pub Dt:
05/09/2002
Title:
CIRCUIT CONFIGURATION FOR SWITCHING OVER A RECEIVER CIRCUIT IN PARTICULAR IN DRAM MEMORIES AND DRAM MEMORY HAVING THE CIRCUIT CONFIGURATION
4
Patent #:
6487108
Issue Dt:
11/26/2002
Application #:
09898257
Filing Dt:
07/03/2001
Publication #:
US20020001243
Pub Dt:
01/03/2002
Title:
MRAM CONFIGURATION
5
Patent #:
6496423
Issue Dt:
12/17/2002
Application #:
09898261
Filing Dt:
07/03/2001
Publication #:
US20020021590
Pub Dt:
02/21/2002
Title:
CHIP ID REGISTER CONFIGURATION
6
Patent #:
6490191
Issue Dt:
12/03/2002
Application #:
09898262
Filing Dt:
07/03/2001
Publication #:
US20020006068
Pub Dt:
01/17/2002
Title:
METHOD AND CONFIGURATION FOR COMPENSATING FOR PARASITIC CURRENT LOSSES
7
Patent #:
6522578
Issue Dt:
02/18/2003
Application #:
09898791
Filing Dt:
07/03/2001
Publication #:
US20020001225
Pub Dt:
01/03/2002
Title:
METHOD FOR PREVENTING ELECTROMIGRATION IN AN MRAM
8
Patent #:
6908844
Issue Dt:
06/21/2005
Application #:
09898909
Filing Dt:
07/03/2001
Publication #:
US20020030278
Pub Dt:
03/14/2002
Title:
METALLIZATION ARRANGEMENT FOR SEMICONDUCTOR STRUCTURE AND CORRESPONDING FABRICATION METHOD
9
Patent #:
6438057
Issue Dt:
08/20/2002
Application #:
09900626
Filing Dt:
07/06/2001
Title:
DRAM REFRESH TIMING ADJUSTMENT DEVICE, SYSTEM AND METHOD
10
Patent #:
6548861
Issue Dt:
04/15/2003
Application #:
09900649
Filing Dt:
07/06/2001
Publication #:
US20030006428
Pub Dt:
01/09/2003
Title:
MEMORY CELL, MEMORY CELL ARRANGEMENT AND FABRICATION METHOD
11
Patent #:
6437178
Issue Dt:
08/20/2002
Application #:
09901218
Filing Dt:
07/09/2001
Publication #:
US20010056203
Pub Dt:
12/27/2001
Title:
O-AMINOPHENOLCARBOXYLIC ACID AND O-AMINOTHIOPHENOLCARBOXYLIC ACID
12
Patent #:
6605864
Issue Dt:
08/12/2003
Application #:
09901524
Filing Dt:
07/09/2001
Publication #:
US20020006688
Pub Dt:
01/17/2002
Title:
SUPPORT MATRIX FOR INTEGRATED SEMICONDUCTORS, AND METHOD FOR PRODUCING IT
13
Patent #:
6979887
Issue Dt:
12/27/2005
Application #:
09901550
Filing Dt:
07/09/2001
Publication #:
US20020003295
Pub Dt:
01/10/2002
Title:
SUPPORT MATRIX WITH BONDING CHANNEL FOR INTEGRATED SEMICONDUCTORS, AND METHOD FOR PRODUCING IT
14
Patent #:
6442100
Issue Dt:
08/27/2002
Application #:
09904358
Filing Dt:
07/12/2001
Publication #:
US20020003735
Pub Dt:
01/10/2002
Title:
INTEGRATED MEMORY
15
Patent #:
7078325
Issue Dt:
07/18/2006
Application #:
09904360
Filing Dt:
07/12/2001
Publication #:
US20020016049
Pub Dt:
02/07/2002
Title:
PROCESS FOR PRODUCING A DOPED SEMICONDUCTOR SUBSTRATE
16
Patent #:
6531377
Issue Dt:
03/11/2003
Application #:
09904799
Filing Dt:
07/13/2001
Publication #:
US20030013271
Pub Dt:
01/16/2003
Title:
METHOD FOR HIGH ASPECT RATIO GAP FILL USING SEQUENTIAL HDP-CVD
17
Patent #:
6667223
Issue Dt:
12/23/2003
Application #:
09905357
Filing Dt:
07/13/2001
Publication #:
US20030013270
Pub Dt:
01/16/2003
Title:
HIGH ASPECT RATIO HIGH DENSITY PLASMA (HDP) OXIDE GAPFILL METHOD IN A LINES AND SPACE PATTERN
18
Patent #:
6826075
Issue Dt:
11/30/2004
Application #:
09905853
Filing Dt:
07/13/2001
Publication #:
US20020012266
Pub Dt:
01/31/2002
Title:
RANDOM ACCESS SEMICONDUCTOR MEMORY WITH REDUCED SIGNAL OVERCOUPLING
19
Patent #:
6665846
Issue Dt:
12/16/2003
Application #:
09905855
Filing Dt:
07/13/2001
Publication #:
US20020016948
Pub Dt:
02/07/2002
Title:
METHOD AND CONFIGURATION FOR VERIFYING A LAYOUT OF AN INTEGRATED CIRCUIT AND APPLICATION THEREOF FOR FABRICATING THE INTEGRATED CIRCUIT
20
Patent #:
6650577
Issue Dt:
11/18/2003
Application #:
09905858
Filing Dt:
07/13/2001
Publication #:
US20020009003
Pub Dt:
01/24/2002
Title:
INTEGRATED SEMICONDUCTOR MEMORY HAVING MEMORY CELLS IN A PLURALITY OF MEMORY CELL ARRAYS AND METHOD FOR REPAIRING SUCH A MEMORY
21
Patent #:
6777960
Issue Dt:
08/17/2004
Application #:
09906270
Filing Dt:
07/16/2001
Publication #:
US20020121891
Pub Dt:
09/05/2002
Title:
METHOD OF INFERRING THE EXISTENCE OF LIGHT BY MEANS OF A MEASUREMENT OF THE ELECTRICAL CHARACTERISTICS OF A NANOTUBE BOUND WITH A DYE, AND DETECTION ARRANGEMENT
22
Patent #:
6960541
Issue Dt:
11/01/2005
Application #:
09906338
Filing Dt:
07/16/2001
Publication #:
US20020070414
Pub Dt:
06/13/2002
Title:
PROCESS FOR FABRICATION OF A SEMICONDUCTOR COMPONENT HAVING A TUNGSTEN OXIDE LAYER
23
Patent #:
6677770
Issue Dt:
01/13/2004
Application #:
09906886
Filing Dt:
07/17/2001
Publication #:
US20030016038
Pub Dt:
01/23/2003
Title:
PROGRAMMABLE TEST SOCKET
24
Patent #:
6871306
Issue Dt:
03/22/2005
Application #:
09907692
Filing Dt:
07/18/2001
Publication #:
US20020160558
Pub Dt:
10/31/2002
Title:
METHOD AND DEVICE FOR READING AND FOR CHECKING THE TIME POSITION OF DATA RESPONSE SIGNALS READ OUT FROM A MEMORY MODULE TO BE TESTED
25
Patent #:
6721904
Issue Dt:
04/13/2004
Application #:
09907693
Filing Dt:
07/18/2001
Publication #:
US20020010877
Pub Dt:
01/24/2002
Title:
SYSTEM FOR TESTING FAST INTEGRATED DIGITAL CIRCUITS, IN PARTICULAR SEMICONDUCTOR MEMORY MODULES
26
Patent #:
6895538
Issue Dt:
05/17/2005
Application #:
09907694
Filing Dt:
07/18/2001
Publication #:
US20040015313
Pub Dt:
01/22/2004
Title:
METHOD FOR TESTING A DEVICE AND A TEST CONFIGURATION INCLUDING A DEVICE WITH A TEST MEMORY
27
Patent #:
6862702
Issue Dt:
03/01/2005
Application #:
09907776
Filing Dt:
07/18/2001
Publication #:
US20020012286
Pub Dt:
01/31/2002
Title:
ADDRESS COUNTER FOR ADDRESSING SYNCHRONOUS HIGH-FREQUENCY DIGITAL CIRCUITS, IN PARTICULAR MEMORY DEVICES
28
Patent #:
7117403
Issue Dt:
10/03/2006
Application #:
09907777
Filing Dt:
07/18/2001
Publication #:
US20020009007
Pub Dt:
01/24/2002
Title:
METHOD AND DEVICE FOR GENERATING DIGITAL SIGNAL PATTERNS
29
Patent #:
6459631
Issue Dt:
10/01/2002
Application #:
09907783
Filing Dt:
07/18/2001
Publication #:
US20020012281
Pub Dt:
01/31/2002
Title:
CONFIGURATION FOR IMPLEMENTING REDUNDANCY FOR A MEMORY CHIP
30
Patent #:
6839397
Issue Dt:
01/04/2005
Application #:
09907784
Filing Dt:
07/18/2001
Publication #:
US20020010878
Pub Dt:
01/24/2002
Title:
CIRCUIT CONFIGURATION FOR GENERATING CONTROL SIGNALS FOR TESTING HIGH-FREQUENCY SYNCHRONOUS DIGITAL CIRCUITS
31
Patent #:
7062690
Issue Dt:
06/13/2006
Application #:
09907786
Filing Dt:
07/18/2001
Publication #:
US20020070748
Pub Dt:
06/13/2002
Title:
SYSTEM FOR TESTING FAST SYNCHRONOUS DIGITAL CIRCUITS, PARTICULARLY SEMICONDUCTOR MEMORY CHIPS
32
Patent #:
6580613
Issue Dt:
06/17/2003
Application #:
09907894
Filing Dt:
07/17/2001
Publication #:
US20030016503
Pub Dt:
01/23/2003
Title:
SOLDER-FREE PCB ASSEMBLY
33
Patent #:
6754869
Issue Dt:
06/22/2004
Application #:
09909390
Filing Dt:
07/19/2001
Publication #:
US20020008503
Pub Dt:
01/24/2002
Title:
METHOD AND DEVICE FOR TESTING SET-UP TIME AND HOLD TIME OF SIGNALS OF A CIRCUIT WITH CLOCKED DATA TRANSFER
34
Patent #:
6924675
Issue Dt:
08/02/2005
Application #:
09910342
Filing Dt:
07/20/2001
Publication #:
US20020016936
Pub Dt:
02/07/2002
Title:
BUFFER DEVICE
35
Patent #:
6570256
Issue Dt:
05/27/2003
Application #:
09910380
Filing Dt:
07/20/2001
Publication #:
US20030017642
Pub Dt:
01/23/2003
Title:
CARBON-GRADED LAYER FOR IMPROVED ADHESION OF LOW-K DIELECTRICS TO SILICON SUBSTRATES
36
Patent #:
6366511
Issue Dt:
04/02/2002
Application #:
09910745
Filing Dt:
07/23/2001
Publication #:
US20010040832
Pub Dt:
11/15/2001
Title:
Method for checking a semiconductor memory device
37
Patent #:
6525977
Issue Dt:
02/25/2003
Application #:
09910749
Filing Dt:
07/23/2001
Publication #:
US20020029369
Pub Dt:
03/07/2002
Title:
CIRCUIT CONFIGURATION
38
Patent #:
6599798
Issue Dt:
07/29/2003
Application #:
09910771
Filing Dt:
07/24/2001
Publication #:
US20030020110
Pub Dt:
01/30/2003
Title:
METHOD OF PREPARING BURIED LOCOS COLLAR IN TRENCH DRAMS
39
Patent #:
6548341
Issue Dt:
04/15/2003
Application #:
09912039
Filing Dt:
07/24/2001
Publication #:
US20020132420
Pub Dt:
09/19/2002
Title:
PROCESS FOR PRODUCING A FIRST ELECTRODE AND A SECOND ELECTRODE, ELECTRONIC COMPONENT AND ELECTRONIC MEMORY ELEMENT
40
Patent #:
6388917
Issue Dt:
05/14/2002
Application #:
09915983
Filing Dt:
07/25/2001
Publication #:
US20020018361
Pub Dt:
02/14/2002
Title:
METHOD FOR NONDESTRUCTIVELY READING MEMORY CELLS OF AN MRAM MEMORY
41
Patent #:
6459296
Issue Dt:
10/01/2002
Application #:
09916668
Filing Dt:
07/26/2001
Publication #:
US20020011869
Pub Dt:
01/31/2002
Title:
METHOD, SYSTEM, AND METHOD OF USING A COMPONENT FOR SETTING THE ELECTRICAL CHARACTERISTICS OF MICROELECTRONIC CIRCUIT CONFIGURATIONS
42
Patent #:
6606151
Issue Dt:
08/12/2003
Application #:
09916917
Filing Dt:
07/27/2001
Publication #:
US20030020901
Pub Dt:
01/30/2003
Title:
GRATING PATTERNS AND METHOD FOR DETERMINATION OF AZIMUTHAL AND RADIAL ABERRATION
43
Patent #:
6538950
Issue Dt:
03/25/2003
Application #:
09917553
Filing Dt:
07/27/2001
Publication #:
US20020044493
Pub Dt:
04/18/2002
Title:
INTEGRATED MEMORY AND CORRESPONDING OPERATING METHOD
44
Patent #:
6673693
Issue Dt:
01/06/2004
Application #:
09917554
Filing Dt:
07/27/2001
Publication #:
US20020022338
Pub Dt:
02/21/2002
Title:
METHOD FOR FORMING A TRENCH IN A SEMICONDUCTOR SUBSTRATE
45
Patent #:
6686242
Issue Dt:
02/03/2004
Application #:
09917867
Filing Dt:
07/26/2001
Publication #:
US20020132430
Pub Dt:
09/19/2002
Title:
METHOD FOR PRODUCING METALLIC BIT LINES FOR MEMORY CELL ARRAYS, METHOD FOR PRODUCING MEMORY CELL ARRAYS AND MEMORY CELL ARRAY
46
Patent #:
6768826
Issue Dt:
07/27/2004
Application #:
09918353
Filing Dt:
07/30/2001
Publication #:
US20030021517
Pub Dt:
01/30/2003
Title:
DELIVERING DATA OPTICALLY TO AN INTEGRATED CIRCUIT
47
Patent #:
6713364
Issue Dt:
03/30/2004
Application #:
09918428
Filing Dt:
07/27/2001
Publication #:
US20020022339
Pub Dt:
02/21/2002
Title:
METHOD FOR FORMING AN INSULATOR HAVING A LOW DIELECTRIC CONSTANT ON A SEMICONDUCTOR SUBSTRATE
48
Patent #:
6961880
Issue Dt:
11/01/2005
Application #:
09918933
Filing Dt:
07/30/2001
Publication #:
US20030023902
Pub Dt:
01/30/2003
Title:
RECORDING TEST INFORMATION TO IDENTIFY MEMORY CELL ERRORS
49
Patent #:
6645683
Issue Dt:
11/11/2003
Application #:
09919230
Filing Dt:
07/31/2001
Publication #:
US20020012861
Pub Dt:
01/31/2002
Title:
CONTROL SYSTEM AND METHODS FOR PHOTOLITHOGRAPHIC PROCESSES
50
Patent #:
6803156
Issue Dt:
10/12/2004
Application #:
09920504
Filing Dt:
08/01/2001
Publication #:
US20030031934
Pub Dt:
02/13/2003
Title:
ELECTROSTATIC DAMAGE (ESD) PROTECTED PHOTOMASK
51
Patent #:
6639829
Issue Dt:
10/28/2003
Application #:
09922471
Filing Dt:
08/03/2001
Publication #:
US20020021543
Pub Dt:
02/21/2002
Title:
CONFIGURATION AND METHOD FOR THE LOW-LOSS WRITING OF AN MRAM
52
Patent #:
6466495
Issue Dt:
10/15/2002
Application #:
09922476
Filing Dt:
08/03/2001
Publication #:
US20020015343
Pub Dt:
02/07/2002
Title:
ELECTRONIC CIRCUIT, TEST-APPARATUS ASSEMBLY, AND METHOD FOR OUTPUTTING A DATA ITEM
53
Patent #:
6692898
Issue Dt:
02/17/2004
Application #:
09923266
Filing Dt:
08/03/2001
Publication #:
US20020098281
Pub Dt:
07/25/2002
Title:
SELF-ALIGNED CONDUCTIVE LINE FOR CROSS-POINT MAGNETIC MEMORY INTEGRATED CIRCUITS
54
Patent #:
6552331
Issue Dt:
04/22/2003
Application #:
09923703
Filing Dt:
08/06/2001
Publication #:
US20020017621
Pub Dt:
02/14/2002
Title:
DEVICE AND METHOD FOR COMBINING SCANNING AND IMAGING METHODS IN CHECKING PHOTOMASKS
55
Patent #:
6784678
Issue Dt:
08/31/2004
Application #:
09923720
Filing Dt:
08/06/2001
Publication #:
US20020024354
Pub Dt:
02/28/2002
Title:
TEST APPARATUS FOR SEMICONDUCTOR CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR CIRCUITS
56
Patent #:
6559005
Issue Dt:
05/06/2003
Application #:
09924072
Filing Dt:
08/07/2001
Publication #:
US20020022316
Pub Dt:
02/21/2002
Title:
METHOD FOR FABRICATING CAPACITOR ELECTRODES
57
Patent #:
6570793
Issue Dt:
05/27/2003
Application #:
09925168
Filing Dt:
08/08/2001
Publication #:
US20020021604
Pub Dt:
02/21/2002
Title:
SEMICONDUCTOR MEMORY HAVING A REDUNDANCY CIRCUIT FOR WORD LINES AND METHOD FOR OPERATING THE MEMORY
58
Patent #:
6477106
Issue Dt:
11/05/2002
Application #:
09925170
Filing Dt:
08/08/2001
Publication #:
US20020027827
Pub Dt:
03/07/2002
Title:
CIRCUIT CONFIGURATION FOR DEACTIVATING WORD LINES IN A MEMORY MATRIX
59
Patent #:
6674132
Issue Dt:
01/06/2004
Application #:
09927554
Filing Dt:
08/09/2001
Publication #:
US20020020890
Pub Dt:
02/21/2002
Title:
MEMORY CELL AND PRODUCTION METHOD
60
Patent #:
6501686
Issue Dt:
12/31/2002
Application #:
09927556
Filing Dt:
08/09/2001
Publication #:
US20020050448
Pub Dt:
05/02/2002
Title:
ELECTRONIC DRIVER CIRCUIT FOR WORD LINES IN A MEMORY MATRIX, AND MEMORY APPARATUS
61
Patent #:
6844584
Issue Dt:
01/18/2005
Application #:
09927573
Filing Dt:
08/09/2001
Publication #:
US20030015752
Pub Dt:
01/23/2003
Title:
MEMORY CELL, MEMORY CELL CONFIGURATION AND FABRICATION METHOD
62
Patent #:
6531412
Issue Dt:
03/11/2003
Application #:
09928209
Filing Dt:
08/10/2001
Publication #:
US20030032306
Pub Dt:
02/13/2003
Title:
METHOD FOR LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION OF LOW-K FILMS USING SELECTED CYCLOSILOXANE AND OZONE GASES FOR SEMICONDUCTOR APPLICATIONS
63
Patent #:
6618303
Issue Dt:
09/09/2003
Application #:
09929303
Filing Dt:
08/13/2001
Publication #:
US20020020854
Pub Dt:
02/21/2002
Title:
INTEGRATED CIRCUIT, TEST STRUCTURE AND METHOD FOR TESTING INTEGRATED CIRCUITS
64
Patent #:
6724055
Issue Dt:
04/20/2004
Application #:
09930409
Filing Dt:
08/15/2001
Publication #:
US20020066932
Pub Dt:
06/06/2002
Title:
SEMICONDUCTOR STRUCTURE HAVING AN INTERCONNECT AND METHOD OF PRODUCING THE SEMICONDUCTOR STRUCTURE
65
Patent #:
6534376
Issue Dt:
03/18/2003
Application #:
09930690
Filing Dt:
08/15/2001
Publication #:
US20030036241
Pub Dt:
02/20/2003
Title:
PROCESS FLOW FOR SACRIFICIAL COLLAR SCHEME WITH VERTICAL NITRIDE MASK
66
Patent #:
7051253
Issue Dt:
05/23/2006
Application #:
09931125
Filing Dt:
08/16/2001
Publication #:
US20030084387
Pub Dt:
05/01/2003
Title:
PSEUDO FAIL BIT MAP GENERATION FOR RAMS DURING COMPONENT TEST AND BURN-IN IN A MANUFACTURING ENVIRONMENT
67
Patent #:
6522588
Issue Dt:
02/18/2003
Application #:
09932893
Filing Dt:
08/20/2001
Publication #:
US20020105836
Pub Dt:
08/08/2002
Title:
METHOD AND DEVICE FOR STORING AND OUTPUTTING DATA WITH A VIRTUAL CHANNEL
68
Patent #:
6596625
Issue Dt:
07/22/2003
Application #:
09932899
Filing Dt:
08/20/2001
Publication #:
US20020022342
Pub Dt:
02/21/2002
Title:
METHOD AND DEVICE FOR PRODUCING A METAL/METAL CONTACT IN A MULTILAYER METALLIZATION OF AN INTEGRATED CIRCUIT
69
Patent #:
6821894
Issue Dt:
11/23/2004
Application #:
09933304
Filing Dt:
08/20/2001
Publication #:
US20020036181
Pub Dt:
03/28/2002
Title:
CMP PROCESS
70
Patent #:
6656647
Issue Dt:
12/02/2003
Application #:
09935353
Filing Dt:
08/22/2001
Publication #:
US20020090747
Pub Dt:
07/11/2002
Title:
METHOD FOR EXAMINING STRUCTURES ON A WAFER
71
Patent #:
6442065
Issue Dt:
08/27/2002
Application #:
09935356
Filing Dt:
08/22/2001
Publication #:
US20020075723
Pub Dt:
06/20/2002
Title:
METHOD FOR OPERATING A MEMORY CELL CONFIGURATION HAVING DYNAMIC GAIN MEMORY CELLS
72
Patent #:
6545625
Issue Dt:
04/08/2003
Application #:
09935503
Filing Dt:
08/23/2001
Publication #:
US20020024457
Pub Dt:
02/28/2002
Title:
METHOD AND DEVICE FOR DATA EXCHANGE BETWEEN MEMORY AND LOGIC MODULES
73
Patent #:
6421271
Issue Dt:
07/16/2002
Application #:
09935622
Filing Dt:
08/23/2001
Publication #:
US20020039308
Pub Dt:
04/04/2002
Title:
MRAM CONFIGURATION
74
Patent #:
6603170
Issue Dt:
08/05/2003
Application #:
09935623
Filing Dt:
08/23/2001
Publication #:
US20020047167
Pub Dt:
04/25/2002
Title:
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Title:
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Title:
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Title:
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Title:
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Assignor
1
QIMONDA AG
Exec Dt:
10/09/2014
Assignee
1
INFINEON TECHNOLOGIES AG
AM CAMPEON 1-12
NEUBIBERG, GERMANY 85579
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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