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Reel/Frame:035623/0001   Pages: 181
Recorded: 05/08/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 4024
Page 12 of 41
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
1
Patent #:
6504200
Issue Dt:
01/07/2003
Application #:
09951243
Filing Dt:
09/12/2001
Publication #:
US20020079527
Pub Dt:
06/27/2002
Title:
DRAM CELL CONFIGURATION AND FABRICATION METHOD
2
Patent #:
6815613
Issue Dt:
11/09/2004
Application #:
09951823
Filing Dt:
09/13/2001
Publication #:
US20020053467
Pub Dt:
05/09/2002
Title:
ELECTRONIC COMPONENT WITH EXTERNAL CONNECTION ELEMENTS
3
Patent #:
6509208
Issue Dt:
01/21/2003
Application #:
09952839
Filing Dt:
09/14/2001
Title:
METHOD FOR FORMING STRUCTURES ON A WAFER
4
Patent #:
6583020
Issue Dt:
06/24/2003
Application #:
09953614
Filing Dt:
09/11/2001
Publication #:
US20020086478
Pub Dt:
07/04/2002
Title:
METHOD FOR FABRICATING A TRENCH ISOLATION FOR ELECTRICALLY ACTIVE COMPONENTS
5
Patent #:
6456522
Issue Dt:
09/24/2002
Application #:
09953729
Filing Dt:
09/17/2001
Publication #:
US20020036916
Pub Dt:
03/28/2002
Title:
INTEGRATED MEMORY HAVING MEMORY CELLS AND BUFFER CAPACITORS
6
Patent #:
6562734
Issue Dt:
05/13/2003
Application #:
09954414
Filing Dt:
09/17/2001
Publication #:
US20020042186
Pub Dt:
04/11/2002
Title:
METHOD OF FILLING GAPS ON A SEMICONDUCTOR WAFER
7
Patent #:
6579729
Issue Dt:
06/17/2003
Application #:
09956164
Filing Dt:
09/19/2001
Publication #:
US20020064069
Pub Dt:
05/30/2002
Title:
MEMORY CELL CONFIGURATION AND METHOD FOR FABRICATING IT
8
Patent #:
6864175
Issue Dt:
03/08/2005
Application #:
09957363
Filing Dt:
09/20/2001
Publication #:
US20020076572
Pub Dt:
06/20/2002
Title:
METHOD FOR FABRICATING INTEGRATED CIRCUIT ARRANGEMENTS, AND ASSOCIATED CIRCUIT ARRANGEMENTS, IN PARTICULAR TUNNEL CONTACT ELEMENTS
9
Patent #:
6542430
Issue Dt:
04/01/2003
Application #:
09957390
Filing Dt:
09/20/2001
Publication #:
US20020034118
Pub Dt:
03/21/2002
Title:
INTEGRATED MEMORY AND MEMORY CONFIGURATION WITH A PLURALITY OF MEMORIES AND METHOD OF OPERATING SUCH A MEMORY CONFIGURATION
10
Patent #:
6566219
Issue Dt:
05/20/2003
Application #:
09957937
Filing Dt:
09/21/2001
Publication #:
US20020068400
Pub Dt:
06/06/2002
Title:
METHOD OF FORMING A SELF ALIGNED TRENCH IN A SEMICONDUCTOR USING A PATTERNED SACRIFICIAL LAYER FOR DEFINING THE TRENCH OPENING
11
Patent #:
6466510
Issue Dt:
10/15/2002
Application #:
09962410
Filing Dt:
09/24/2001
Publication #:
US20020036945
Pub Dt:
03/28/2002
Title:
1-OUT-OF-N DECODER CIRCUIT
12
Patent #:
6487128
Issue Dt:
11/26/2002
Application #:
09962411
Filing Dt:
09/24/2001
Publication #:
US20020027816
Pub Dt:
03/07/2002
Title:
INTEGRATED MEMORY HAVING MEMORY CELLS AND REFERENCE CELLS, AND OPERATING METHOD FOR SUCH A MEMORY
13
Patent #:
6656787
Issue Dt:
12/02/2003
Application #:
09962694
Filing Dt:
09/24/2001
Publication #:
US20020005536
Pub Dt:
01/17/2002
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR COMPONENT
14
Patent #:
6459626
Issue Dt:
10/01/2002
Application #:
09962703
Filing Dt:
09/24/2001
Publication #:
US20020071317
Pub Dt:
06/13/2002
Title:
INTEGRATED MEMORY HAVING MEMORY CELLS AND REFERENCE CELLS, AND CORRESPONDING OPERATING METHOD
15
Patent #:
6623231
Issue Dt:
09/23/2003
Application #:
09963005
Filing Dt:
09/25/2001
Publication #:
US20020102865
Pub Dt:
08/01/2002
Title:
PLANT FOR PRODUCING SEMICONDUCTOR PRODUCTS
16
Patent #:
6560732
Issue Dt:
05/06/2003
Application #:
09963006
Filing Dt:
09/25/2001
Publication #:
US20020046385
Pub Dt:
04/18/2002
Title:
OPERATING METHOD FOR AN INTEGRATED MEMORY HAVING WRITEABLE MEMORY CELLS AND CORRESPONDING INTEGRATED MEMORY
17
Patent #:
6709475
Issue Dt:
03/23/2004
Application #:
09963956
Filing Dt:
09/26/2001
Publication #:
US20020074025
Pub Dt:
06/20/2002
Title:
INSTALLATION FOR PROCESSING WAFERS
18
Patent #:
6602127
Issue Dt:
08/05/2003
Application #:
09963957
Filing Dt:
09/26/2001
Publication #:
US20020040568
Pub Dt:
04/11/2002
Title:
PLANT FOR PRODUCING SEMICONDUCTOR PRODUCTS
19
Patent #:
6992394
Issue Dt:
01/31/2006
Application #:
09964205
Filing Dt:
09/26/2001
Publication #:
US20030210103
Pub Dt:
11/13/2003
Title:
MULTI-LEVEL CONDUCTIVE LINES WITH REDUCED PITCH
20
Patent #:
6680857
Issue Dt:
01/20/2004
Application #:
09964208
Filing Dt:
09/26/2001
Publication #:
US20030058028
Pub Dt:
03/27/2003
Title:
UNIT-ARCHITECTURE WITH IMPLEMENTED LIMITED BANK-COLUMN-SELECT REPAIRABILITY
21
Patent #:
6430076
Issue Dt:
08/06/2002
Application #:
09964209
Filing Dt:
09/26/2001
Title:
MULTI-LEVEL SIGNAL LINES WITH VERTICAL TWISTS
22
Patent #:
6584006
Issue Dt:
06/24/2003
Application #:
09965086
Filing Dt:
09/27/2001
Publication #:
US20020097597
Pub Dt:
07/25/2002
Title:
MRAM BIT LINE WORD LINE ARCHITECTURE
23
Patent #:
6716734
Issue Dt:
04/06/2004
Application #:
09965092
Filing Dt:
09/28/2001
Publication #:
US20030064576
Pub Dt:
04/03/2003
Title:
LOW TEMPERATURE SIDEWALL OXIDATION OF W/WN/POLY-GATESTACK
24
Patent #:
6708559
Issue Dt:
03/23/2004
Application #:
09965093
Filing Dt:
09/28/2001
Publication #:
US20030061890
Pub Dt:
04/03/2003
Title:
DIRECT, NON-DESTRUCTIVE MEASUREMENT OF RECESS DEPTH IN A WAFER
25
Patent #:
6734097
Issue Dt:
05/11/2004
Application #:
09965094
Filing Dt:
09/28/2001
Publication #:
US20030068894
Pub Dt:
04/10/2003
Title:
LINER WITH POOR STEP COVERAGE TO IMPROVE CONTACT RESISTANCE IN W CONTACTS
26
Patent #:
6656798
Issue Dt:
12/02/2003
Application #:
09965919
Filing Dt:
09/28/2001
Publication #:
US20030067035
Pub Dt:
04/10/2003
Title:
GATE PROCESSING METHOD WITH REDUCED GATE OXIDE CORNER AND EDGE THINNING
27
Patent #:
6465282
Issue Dt:
10/15/2002
Application #:
09966332
Filing Dt:
09/28/2001
Title:
METHOD OF FORMING A SELF-ALIGNED ANTIFUSE LINK
28
Patent #:
6432725
Issue Dt:
08/13/2002
Application #:
09966496
Filing Dt:
09/28/2001
Title:
METHODS FOR CRYSTALLIZING METALLIC OXIDE DIELECTRIC FILMS AT LOW TEMPERATURE
29
Patent #:
6842235
Issue Dt:
01/11/2005
Application #:
09966506
Filing Dt:
09/28/2001
Publication #:
US20030063272
Pub Dt:
04/03/2003
Title:
OPTICAL MEASUREMENT OF PLANARIZED FEATURES
30
Patent #:
6677205
Issue Dt:
01/13/2004
Application #:
09966644
Filing Dt:
09/28/2001
Publication #:
US20030062568
Pub Dt:
04/03/2003
Title:
INTEGRATED SPACER FOR GATE/SOURCE/DRAIN ISOLATION IN A VERTICAL ARRAY STRUCTURE
31
Patent #:
6981175
Issue Dt:
12/27/2005
Application #:
09967008
Filing Dt:
09/28/2001
Publication #:
US20030065973
Pub Dt:
04/03/2003
Title:
MEMORY AND METHOD FOR EMPLOYING A CHECKSUM FOR ADDRESSES OF REPLACED STORAGE ELEMENTS
32
Patent #:
6724479
Issue Dt:
04/20/2004
Application #:
09967176
Filing Dt:
09/28/2001
Publication #:
US20030063278
Pub Dt:
04/03/2003
Title:
METHOD FOR OVERLAY METROLOGY OF LOW CONTRAST FEATURES
33
Patent #:
6951822
Issue Dt:
10/04/2005
Application #:
09967225
Filing Dt:
09/28/2001
Publication #:
US20030064589
Pub Dt:
04/03/2003
Title:
METHOD FOR FORMING INSIDE NITRIDE SPACER FOR DEEP TRENCH DEVICE DRAM CELL
34
Patent #:
6620699
Issue Dt:
09/16/2003
Application #:
09967226
Filing Dt:
09/28/2001
Publication #:
US20030062557
Pub Dt:
04/03/2003
Title:
METHOD FOR FORMING INSIDE NITRIDE SPACER FOR DEEP TRENCH DEVICE DRAM CELL
35
Patent #:
6801314
Issue Dt:
10/05/2004
Application #:
09967299
Filing Dt:
09/28/2001
Publication #:
US20030064306
Pub Dt:
04/03/2003
Title:
ALIGNMENT SYSTEM AND METHOD USING BRIGHT SPOT AND BOX STRUCTURE
36
Patent #:
6660637
Issue Dt:
12/09/2003
Application #:
09967318
Filing Dt:
09/28/2001
Publication #:
US20030064594
Pub Dt:
04/03/2003
Title:
PROCESS FOR CHEMICAL MECHANICAL POLISHING
37
Patent #:
6490194
Issue Dt:
12/03/2002
Application #:
09967662
Filing Dt:
09/27/2001
Publication #:
US20020097598
Pub Dt:
07/25/2002
Title:
SERIAL MRAM DEVICE
38
Patent #:
6620559
Issue Dt:
09/16/2003
Application #:
09967698
Filing Dt:
09/28/2001
Publication #:
US20020039691
Pub Dt:
04/04/2002
Title:
PHOTOMASK, METHOD OF LITHOGRAPHICALLY STRUCTURING A PHOTORESIST LAYER WITH THE PHOTOMASK, AND METHOD OF PRODUCING MAGNETIC MEMORY ELEMENTS
39
Patent #:
6815364
Issue Dt:
11/09/2004
Application #:
09967795
Filing Dt:
09/28/2001
Publication #:
US20030064602
Pub Dt:
04/03/2003
Title:
TUNGSTEN HARD MASK
40
Patent #:
6512688
Issue Dt:
01/28/2003
Application #:
09968287
Filing Dt:
10/01/2001
Publication #:
US20020093848
Pub Dt:
07/18/2002
Title:
DEVICE FOR EVALUATING CELL RESISTANCES IN A MAGNETORESISTIVE MEMORY
41
Patent #:
6518613
Issue Dt:
02/11/2003
Application #:
09968304
Filing Dt:
10/01/2001
Publication #:
US20020071320
Pub Dt:
06/13/2002
Title:
MEMORY CELL CONFIGURATION WITH CAPACITOR ON OPPOSITE SURFACE OF SUBSTRATE AND METHOD FOR FABRICATION THE SAME
42
Patent #:
6490192
Issue Dt:
12/03/2002
Application #:
09968575
Filing Dt:
10/01/2001
Publication #:
US20020071306
Pub Dt:
06/13/2002
Title:
DEVICE FOR EVALUATING CELL RESISTANCES IN A MAGNETORESISTIVE MEMORY
43
Patent #:
6531378
Issue Dt:
03/11/2003
Application #:
09968576
Filing Dt:
10/01/2001
Publication #:
US20020086532
Pub Dt:
07/04/2002
Title:
METHOD FOR PROCESSING WAFER BY APPLYING LAYER TO PROTECT THE BACKSIDE DURING A TEMPERING STEP AND REMOVING CONTAMINATED PORTIONS OF THE LAYER
44
Patent #:
6724475
Issue Dt:
04/20/2004
Application #:
09968587
Filing Dt:
10/01/2001
Publication #:
US20020101585
Pub Dt:
08/01/2002
Title:
APPARATUS FOR RAPIDLY MEASURING ANGLE-DEPENDENT DIFFRACTION EFFECTS ON FINELY PATTERNED SURFACES
45
Patent #:
6521512
Issue Dt:
02/18/2003
Application #:
09970977
Filing Dt:
10/04/2001
Publication #:
US20020048955
Pub Dt:
04/25/2002
Title:
METHOD FOR FABRICATING A THIN, FREE-STANDING SEMICONDUCTOR DEVICE LAYER AND FOR MAKING A THREE-DIMENSIONALLY INTEGRATED CIRCUIT
46
Patent #:
6525416
Issue Dt:
02/25/2003
Application #:
09970979
Filing Dt:
10/04/2001
Publication #:
US20020041017
Pub Dt:
04/11/2002
Title:
ELECTRONIC DEVICES AND A SHEET STRIP FOR PACKAGING BONDING WIRE CONNECTIONS OF ELECTRONIC DEVICES AND METHOD FOR PRODUCING THEM
47
Patent #:
6510079
Issue Dt:
01/21/2003
Application #:
09975058
Filing Dt:
10/11/2001
Publication #:
US20020044482
Pub Dt:
04/18/2002
Title:
MRAM CONFIGURATION
48
Patent #:
6617096
Issue Dt:
09/09/2003
Application #:
09976233
Filing Dt:
10/12/2001
Publication #:
US20020086241
Pub Dt:
07/04/2002
Title:
METHOD OF PRODUCING AN INTEGRATED CIRCUIT CONFIGURATION
49
Patent #:
6620701
Issue Dt:
09/16/2003
Application #:
09977004
Filing Dt:
10/12/2001
Publication #:
US20030073282
Pub Dt:
04/17/2003
Title:
VERTICAL/HORIZONTAL MIMCAP METHOD
50
Patent #:
6635496
Issue Dt:
10/21/2003
Application #:
09977027
Filing Dt:
10/12/2001
Publication #:
US20030073251
Pub Dt:
04/17/2003
Title:
PLATE-THROUGH HARD MASK FOR MRAM DEVICES
51
Patent #:
6968483
Issue Dt:
11/22/2005
Application #:
09977787
Filing Dt:
10/15/2001
Publication #:
US20020056062
Pub Dt:
05/09/2002
Title:
CIRCUIT AND METHOD FOR TESTING A DATA MEMORY
52
Patent #:
6614706
Issue Dt:
09/02/2003
Application #:
09977805
Filing Dt:
10/15/2001
Publication #:
US20020080675
Pub Dt:
06/27/2002
Title:
VOLTAGE REGULATING CIRCUIT, IN PARTICULAR FOR SEMICONDUCTOR MEMORIES
53
Patent #:
6543045
Issue Dt:
04/01/2003
Application #:
09978396
Filing Dt:
10/16/2001
Publication #:
US20020046392
Pub Dt:
04/18/2002
Title:
METHOD FOR DETECTING AND AUTOMATICALLY ELIMINATING PHASE CONFLICTS ON ALTERNATING PHASE MASKS
54
Patent #:
6603699
Issue Dt:
08/05/2003
Application #:
09978398
Filing Dt:
10/16/2001
Publication #:
US20020044492
Pub Dt:
04/18/2002
Title:
CONFIGURATION FOR FUSE INITIALIZATION
55
Patent #:
6625065
Issue Dt:
09/23/2003
Application #:
09978399
Filing Dt:
10/16/2001
Publication #:
US20020076872
Pub Dt:
06/20/2002
Title:
METHOD FOR MASKING DQ BITS
56
Patent #:
6670662
Issue Dt:
12/30/2003
Application #:
09980386
Filing Dt:
03/19/2002
Title:
SEMICONDUCTOR STORAGE COMPONENT WITH STORAGE CELLS, LOGIC AREAS AND FILLING STRUCTURES
57
Patent #:
6599797
Issue Dt:
07/29/2003
Application #:
09980811
Filing Dt:
03/11/2002
Title:
SOI DRAM WITHOUT FLOATING BODY EFFECT
58
Patent #:
6507528
Issue Dt:
01/14/2003
Application #:
09981855
Filing Dt:
10/18/2001
Publication #:
US20020075741
Pub Dt:
06/20/2002
Title:
CIRCUIT CONFIGURATION FOR GENERATING SENSE AMPLIFIER CONTROL SIGNALS
59
Patent #:
6586308
Issue Dt:
07/01/2003
Application #:
09981856
Filing Dt:
10/18/2001
Publication #:
US20020061614
Pub Dt:
05/23/2002
Title:
METHOD FOR PRODUCING CIRCUIT STRUCTURES ON A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR CONFIGURATION WITH FUNCTIONAL CIRCUIT STRUCTURES AND DUMMY CIRCUIT STRUCTURES
60
Patent #:
6696206
Issue Dt:
02/24/2004
Application #:
09982200
Filing Dt:
10/17/2001
Publication #:
US20020081498
Pub Dt:
06/27/2002
Title:
LITHOGRAPHY MASK CONFIGURATION
61
Patent #:
6596580
Issue Dt:
07/22/2003
Application #:
09982574
Filing Dt:
10/18/2001
Publication #:
US20030077858
Pub Dt:
04/24/2003
Title:
RECESS PT STRUCTURE FOR HIGH K STACKED CAPACITOR IN DRAM AND FRAM, AND THE METHOD TO FORM THIS STRUCTURE
62
Patent #:
6548344
Issue Dt:
04/15/2003
Application #:
09987956
Filing Dt:
11/16/2001
Title:
SPACER FORMATION PROCESS USING OXIDE SHIELD
63
Patent #:
6867087
Issue Dt:
03/15/2005
Application #:
09988183
Filing Dt:
11/19/2001
Publication #:
US20030096471
Pub Dt:
05/22/2003
Title:
FORMATION OF DUAL WORK FUNCTION GATE ELECTRODE
64
Patent #:
6614704
Issue Dt:
09/02/2003
Application #:
09991791
Filing Dt:
11/19/2001
Publication #:
US20020080674
Pub Dt:
06/27/2002
Title:
CIRCUIT AND METHOD FOR REFRESHING MEMORY CELLS IN A DRAM
65
Patent #:
6579786
Issue Dt:
06/17/2003
Application #:
09992977
Filing Dt:
11/19/2001
Publication #:
US20020086527
Pub Dt:
07/04/2002
Title:
METHOD FOR DEPOSITING A TWO-LAYER DIFFUSION BARRIER
66
Patent #:
6649531
Issue Dt:
11/18/2003
Application #:
09994340
Filing Dt:
11/26/2001
Publication #:
US20030100190
Pub Dt:
05/29/2003
Title:
PROCESS FOR FORMING A DAMASCENE STRUCTURE
67
Patent #:
6645809
Issue Dt:
11/11/2003
Application #:
09995209
Filing Dt:
11/27/2001
Publication #:
US20020081790
Pub Dt:
06/27/2002
Title:
PROCESS FOR PRODUCING A CAPACITOR CONFIGURATION
68
Patent #:
6645855
Issue Dt:
11/11/2003
Application #:
09995210
Filing Dt:
11/27/2001
Publication #:
US20020064960
Pub Dt:
05/30/2002
Title:
METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR PRODUCT
69
Patent #:
6515891
Issue Dt:
02/04/2003
Application #:
09996260
Filing Dt:
11/28/2001
Publication #:
US20020089884
Pub Dt:
07/11/2002
Title:
RANDOM ACCESS MEMORY WITH HIDDEN BITS
70
Patent #:
6864129
Issue Dt:
03/08/2005
Application #:
09996279
Filing Dt:
11/28/2001
Publication #:
US20020081791
Pub Dt:
06/27/2002
Title:
DOUBLE GATE MOSFET TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF
71
Patent #:
6469571
Issue Dt:
10/22/2002
Application #:
09996280
Filing Dt:
11/28/2001
Publication #:
US20020075065
Pub Dt:
06/20/2002
Title:
CHARGE PUMP WITH CHARGE EQUALIZATION FOR IMPROVED EFFICIENCY
72
Patent #:
6649483
Issue Dt:
11/18/2003
Application #:
09996959
Filing Dt:
11/20/2001
Publication #:
US20020155675
Pub Dt:
10/24/2002
Title:
METHOD FOR FABRICATING A CAPACITOR CONFIGURATION
73
Patent #:
6757187
Issue Dt:
06/29/2004
Application #:
09997983
Filing Dt:
11/29/2001
Publication #:
US20020066002
Pub Dt:
05/30/2002
Title:
INTEGRATED MAGNETORESISTIVE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE MEMORY
74
Patent #:
6515514
Issue Dt:
02/04/2003
Application #:
09998723
Filing Dt:
11/30/2001
Publication #:
US20020079924
Pub Dt:
06/27/2002
Title:
METHOD AND CIRCUIT CONFIGURATION FOR CONTROLLING A DATA DRIVER
75
Patent #:
6556486
Issue Dt:
04/29/2003
Application #:
09998725
Filing Dt:
11/30/2001
Publication #:
US20020071335
Pub Dt:
06/13/2002
Title:
CIRCUIT CONFIGURATION AND METHOD FOR SYNCHRONIZATION
76
Patent #:
6746821
Issue Dt:
06/08/2004
Application #:
09999323
Filing Dt:
10/31/2001
Publication #:
US20020058425
Pub Dt:
05/16/2002
Title:
METHOD OF STRUCTURING A PHOTORESIST LAYER
77
Patent #:
6996187
Issue Dt:
02/07/2006
Application #:
09999382
Filing Dt:
10/31/2001
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Title:
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Assignor
1
QIMONDA AG
Exec Dt:
10/09/2014
Assignee
1
INFINEON TECHNOLOGIES AG
AM CAMPEON 1-12
NEUBIBERG, GERMANY 85579
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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