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Patent Assignment Details
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Reel/Frame:035623/0001   Pages: 181
Recorded: 05/08/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 4024
Page 13 of 41
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
1
Patent #:
6756655
Issue Dt:
06/29/2004
Application #:
10013298
Filing Dt:
12/10/2001
Publication #:
US20020084508
Pub Dt:
07/04/2002
Title:
FUSE FOR A SEMICONDUCTOR CONFIGURATION AND METHOD FOR ITS PRODUCTION
2
Patent #:
6670568
Issue Dt:
12/30/2003
Application #:
10014245
Filing Dt:
11/07/2001
Publication #:
US20020060172
Pub Dt:
05/23/2002
Title:
INSTALLATION FOR PROCESSING WAFERS
3
Patent #:
6560134
Issue Dt:
05/06/2003
Application #:
10014776
Filing Dt:
11/07/2001
Publication #:
US20020062430
Pub Dt:
05/23/2002
Title:
MEMORY CONFIGURATION WITH A CENTRAL CONNECTION AREA
4
Patent #:
6809510
Issue Dt:
10/26/2004
Application #:
10015150
Filing Dt:
11/07/2001
Publication #:
US20020064954
Pub Dt:
05/30/2002
Title:
CONFIGURATION IN WHICH WAFERS ARE INDIVIDUALLY SUPPLIED TO FABRICATION UNITS AND MEASURING UNITS LOCATED IN A FABRICATION CELL
5
Patent #:
6548314
Issue Dt:
04/15/2003
Application #:
10015212
Filing Dt:
12/10/2001
Title:
METHOD FOR ENABLING ACCESS TO MICRO-SECTIONS OF INTEGRATED CIRCUITS ON A WAFER
6
Patent #:
6594188
Issue Dt:
07/15/2003
Application #:
10015829
Filing Dt:
12/13/2001
Publication #:
US20020097620
Pub Dt:
07/25/2002
Title:
INTEGRATED MEMORY HAVING A CELL ARRAY AND CHARGE EQUALIZATION DEVICES, AND METHOD FOR THE ACCELERATED WRITING OF A DATUM TO THE INTEGRATED MEMORY
7
Patent #:
6613642
Issue Dt:
09/02/2003
Application #:
10016075
Filing Dt:
12/13/2001
Publication #:
US20030114005
Pub Dt:
06/19/2003
Title:
METHOD FOR SURFACE ROUGHNESS ENHANCEMENT IN SEMICONDUCTOR CAPACITOR MANUFACTURING
8
Patent #:
6914006
Issue Dt:
07/05/2005
Application #:
10016633
Filing Dt:
10/30/2001
Publication #:
US20030109141
Pub Dt:
06/12/2003
Title:
WAFER SCRIBING METHOD AND WAFER SCRIBING DEVICE
9
Patent #:
6910161
Issue Dt:
06/21/2005
Application #:
10016863
Filing Dt:
12/14/2001
Publication #:
US20020087926
Pub Dt:
07/04/2002
Title:
DEVICE AND METHOD FOR REDUCING THE NUMBER OF ADDRESSES OF FAULTY MEMORY CELLS
10
Patent #:
6642602
Issue Dt:
11/04/2003
Application #:
10017036
Filing Dt:
12/14/2001
Publication #:
US20030112016
Pub Dt:
06/19/2003
Title:
SELF-TERMINATING BLOW PROCESS OF ELECTRICAL ANTI-FUSES
11
Patent #:
6956287
Issue Dt:
10/18/2005
Application #:
10022226
Filing Dt:
12/17/2001
Publication #:
US20020089058
Pub Dt:
07/11/2002
Title:
ELECTRONIC COMPONENT WITH FLEXIBLE BONDING PADS AND METHOD OF PRODUCING SUCH A COMPONENT
12
Patent #:
7276781
Issue Dt:
10/02/2007
Application #:
10022605
Filing Dt:
12/17/2001
Publication #:
US20020079559
Pub Dt:
06/27/2002
Title:
MULTICHIP MODULE FOR LOC MOUNTING AND METHOD FOR PRODUCING THE MULTICHIP MODULE
13
Patent #:
6555415
Issue Dt:
04/29/2003
Application #:
10022606
Filing Dt:
12/17/2001
Publication #:
US20020094707
Pub Dt:
07/18/2002
Title:
ELECTRONIC CONFIGURATION WITH FLEXIBLE BONDING PADS
14
Patent #:
6661053
Issue Dt:
12/09/2003
Application #:
10022654
Filing Dt:
12/18/2001
Publication #:
US20030111687
Pub Dt:
06/19/2003
Title:
MEMORY CELL WITH TRENCH TRANSISTOR
15
Patent #:
6713884
Issue Dt:
03/30/2004
Application #:
10026347
Filing Dt:
12/20/2001
Publication #:
US20030119274
Pub Dt:
06/26/2003
Title:
METHOD OF FORMING AN ALIGNMENT MARK STRUCTURE USING STANDARD PROCESS STEPS FOR FORMING VERTICAL GATE TRANSISTORS
16
Patent #:
6521935
Issue Dt:
02/18/2003
Application #:
10027524
Filing Dt:
12/26/2001
Publication #:
US20020096699
Pub Dt:
07/25/2002
Title:
MOS TRANSISTOR AND DRAM CELL CONFIGURATION
17
Patent #:
6495415
Issue Dt:
12/17/2002
Application #:
10027532
Filing Dt:
12/26/2001
Publication #:
US20020086511
Pub Dt:
07/04/2002
Title:
METHOD FOR FABRICATING A PATTERNED LAYER
18
Patent #:
6677197
Issue Dt:
01/13/2004
Application #:
10032040
Filing Dt:
12/31/2001
Publication #:
US20030124805
Pub Dt:
07/03/2003
Title:
HIGH ASPECT RATIO PBL SIN BARRIER FORMATION
19
Patent #:
6559002
Issue Dt:
05/06/2003
Application #:
10032041
Filing Dt:
12/31/2001
Title:
ROUGH OXIDE HARD MASK FOR DT SURFACE AREA ENHANCEMENT FOR DT DRAM
20
Patent #:
6767674
Issue Dt:
07/27/2004
Application #:
10032389
Filing Dt:
10/26/2001
Publication #:
US20030082461
Pub Dt:
05/01/2003
Title:
METHOD FOR OBTAINING ELLIPTICAL AND ROUNDED SHAPES USING BEAM SHAPING
21
Patent #:
6782331
Issue Dt:
08/24/2004
Application #:
10032876
Filing Dt:
10/24/2001
Publication #:
US20030078748
Pub Dt:
04/24/2003
Title:
GRAPHICAL USER INTERFACE FOR TESTING INTEGRATED CIRCUITS
22
Patent #:
6888256
Issue Dt:
05/03/2005
Application #:
10032941
Filing Dt:
10/31/2001
Publication #:
US20030080425
Pub Dt:
05/01/2003
Title:
COMPLIANT RELIEF WAFER LEVEL PACKAGING
23
Patent #:
6762630
Issue Dt:
07/13/2004
Application #:
10033123
Filing Dt:
10/22/2001
Publication #:
US20020067192
Pub Dt:
06/06/2002
Title:
INTEGRATED CIRCUIT HAVING A SYNCHRONOUS AND AN ASYNCHRONOUS CIRCUIT AND METHOD FOR OPERATING SUCH AN INTEGRATED CIRCUIT
24
Patent #:
6670802
Issue Dt:
12/30/2003
Application #:
10033131
Filing Dt:
10/22/2001
Publication #:
US20020133750
Pub Dt:
09/19/2002
Title:
INTEGRATED CIRCUIT HAVING A TEST OPERATING MODE AND METHOD FOR TESTING A MULTIPLICITY OF SUCH CIRCUITS
25
Patent #:
6657422
Issue Dt:
12/02/2003
Application #:
10033877
Filing Dt:
12/27/2001
Publication #:
US20020089319
Pub Dt:
07/11/2002
Title:
CURRENT MIRROR CIRCUIT
26
Patent #:
6784445
Issue Dt:
08/31/2004
Application #:
10033950
Filing Dt:
12/28/2001
Publication #:
US20020089677
Pub Dt:
07/11/2002
Title:
APPARATUS FOR MONITORING INTENTIONAL OR UNAVOIDABLE LAYER DEPOSITIONS AND METHOD
27
Patent #:
6767581
Issue Dt:
07/27/2004
Application #:
10034053
Filing Dt:
12/20/2001
Publication #:
US20020127338
Pub Dt:
09/12/2002
Title:
PROCESS FOR THE DEPOSITION OF THIN LAYERS BY CHEMICAL VAPOR DEPOSITION
28
Patent #:
7047454
Issue Dt:
05/16/2006
Application #:
10034070
Filing Dt:
12/20/2001
Publication #:
US20020083380
Pub Dt:
06/27/2002
Title:
INTEGRATED CIRCUIT HAVING A DATA PROCESSING UNIT AND A BUFFER MEMORY
29
Patent #:
6608783
Issue Dt:
08/19/2003
Application #:
10034625
Filing Dt:
12/27/2001
Publication #:
US20030133320
Pub Dt:
07/17/2003
Title:
TWISTED BIT-LINE COMPENSATION
30
Patent #:
6570794
Issue Dt:
05/27/2003
Application #:
10034626
Filing Dt:
12/27/2001
Title:
TWISTED BIT-LINE COMPENSATION FOR DRAM HAVING REDUNDANCY
31
Patent #:
6505314
Issue Dt:
01/07/2003
Application #:
10034920
Filing Dt:
11/21/2001
Publication #:
US20020066057
Pub Dt:
05/30/2002
Title:
METHOD AND APPARATUS FOR PROCESSING DEFECT ADDRESSES
32
Patent #:
6628409
Issue Dt:
09/30/2003
Application #:
10034930
Filing Dt:
11/21/2001
Publication #:
US20020149783
Pub Dt:
10/17/2002
Title:
METHOD FOR DETERMINING THE DISTANCE BETWEEN PERIODIC STRUCTURES ON AN INTEGRATED CIRCUIT OR A PHOTOMASK
33
Patent #:
6664158
Issue Dt:
12/16/2003
Application #:
10034931
Filing Dt:
11/21/2001
Publication #:
US20020123203
Pub Dt:
09/05/2002
Title:
FERROELECTRIC MEMORY CONFIGURATION AND A METHOD FOR PRODUCING THE CONFIGURATION
34
Patent #:
6661718
Issue Dt:
12/09/2003
Application #:
10035866
Filing Dt:
12/31/2001
Publication #:
US20020149975
Pub Dt:
10/17/2002
Title:
TESTING DEVICE FOR TESTING A MEMORY
35
Patent #:
6544855
Issue Dt:
04/08/2003
Application #:
10041779
Filing Dt:
10/19/2001
Publication #:
US20030077872
Pub Dt:
04/24/2003
Title:
PROCESS FLOW FOR SACRIFICIAL COLLAR WITH POLYSILICON VOID
36
Patent #:
6727576
Issue Dt:
04/27/2004
Application #:
10044000
Filing Dt:
10/31/2001
Publication #:
US20030080399
Pub Dt:
05/01/2003
Title:
TRANSFER WAFER LEVEL PACKAGING
37
Patent #:
6638870
Issue Dt:
10/28/2003
Application #:
10044136
Filing Dt:
01/10/2002
Publication #:
US20030129841
Pub Dt:
07/10/2003
Title:
FORMING A STRUCTURE ON A WAFER
38
Patent #:
6480024
Issue Dt:
11/12/2002
Application #:
10046395
Filing Dt:
10/19/2001
Publication #:
US20020079925
Pub Dt:
06/27/2002
Title:
CIRCUIT CONFIGURATION FOR PROGRAMMING A DELAY IN A SIGNAL PATH
39
Patent #:
6686648
Issue Dt:
02/03/2004
Application #:
10047028
Filing Dt:
01/16/2002
Publication #:
US20020094607
Pub Dt:
07/18/2002
Title:
ELECTRONIC COMPONENT WITH STACKED SEMICONDUCTOR CHIPS AND METHOD OF PRODUCING THE COMPONENT
40
Patent #:
6716748
Issue Dt:
04/06/2004
Application #:
10047814
Filing Dt:
01/15/2002
Publication #:
US20020092840
Pub Dt:
07/18/2002
Title:
REACTION CHAMBER FOR PROCESSING A SUBSTRATE WAFER, AND METHOD FOR OPERATING THE CHAMBER
41
Patent #:
6538895
Issue Dt:
03/25/2003
Application #:
10047815
Filing Dt:
01/15/2002
Publication #:
US20030012002
Pub Dt:
01/16/2003
Title:
TSOP MEMORY CHIP HOUSING CONFIGURATION
42
Patent #:
6584021
Issue Dt:
06/24/2003
Application #:
10047824
Filing Dt:
01/15/2002
Publication #:
US20020093855
Pub Dt:
07/18/2002
Title:
SEMICONDUCTOR MEMORY HAVING A DELAY LOCKED LOOP
43
Patent #:
6716643
Issue Dt:
04/06/2004
Application #:
10048192
Filing Dt:
06/03/2002
Title:
METHOD FOR PRODUCING A SEMICONDUCTOR MEMORY ELEMENT
44
Patent #:
6787831
Issue Dt:
09/07/2004
Application #:
10050246
Filing Dt:
01/15/2002
Publication #:
US20030132469
Pub Dt:
07/17/2003
Title:
BARRIER STACK WITH IMPROVED BARRIER PROPERTIES
45
Patent #:
6687014
Issue Dt:
02/03/2004
Application #:
10050737
Filing Dt:
01/16/2002
Publication #:
US20030133127
Pub Dt:
07/17/2003
Title:
METHOD FOR MONITORING THE RATE OF ETCHING OF A SEMICONDUCTOR
46
Patent #:
6724030
Issue Dt:
04/20/2004
Application #:
10051544
Filing Dt:
01/18/2002
Publication #:
US20030136993
Pub Dt:
07/24/2003
Title:
SYSTEM AND METHOD FOR BACK-SIDE CONTACT FOR TRENCH SEMICONDUCTOR DEVICE CHARACTERIZATION
47
Patent #:
6541387
Issue Dt:
04/01/2003
Application #:
10052201
Filing Dt:
01/17/2002
Title:
PROCESS FOR IMPLEMENTATION OF A HARDMASK
48
Patent #:
6589832
Issue Dt:
07/08/2003
Application #:
10053145
Filing Dt:
01/17/2002
Publication #:
US20030060006
Pub Dt:
03/27/2003
Title:
SPACER FORMATION IN A DEEP TRENCH MEMORY CELL
49
Patent #:
6711047
Issue Dt:
03/23/2004
Application #:
10053970
Filing Dt:
01/22/2002
Publication #:
US20020097619
Pub Dt:
07/25/2002
Title:
TEST CIRCUIT FOR AN ANALOG MEASUREMENT OF BIT LINE SIGNALS OF FERROELECTRIC MEMORY CELLS
50
Patent #:
6704676
Issue Dt:
03/09/2004
Application #:
10053983
Filing Dt:
01/22/2002
Publication #:
US20020099512
Pub Dt:
07/25/2002
Title:
METHOD AND CIRCUIT CONFIGURATION FOR IDENTIFYING AN OPERATING PROPERTY OF AN INTEGRATED CIRCUIT
51
Patent #:
6657916
Issue Dt:
12/02/2003
Application #:
10054195
Filing Dt:
01/22/2002
Publication #:
US20020116591
Pub Dt:
08/22/2002
Title:
INTEGRATED MEMORY WITH MEMORY CELL ARRAY
52
Patent #:
6614069
Issue Dt:
09/02/2003
Application #:
10054440
Filing Dt:
01/22/2002
Publication #:
US20020125525
Pub Dt:
09/12/2002
Title:
NONVOLATILE SEMICONDUCTOR MEMORY CELL AND METHOD FOR FABRICATING THE MEMORY CELL
53
Patent #:
6696349
Issue Dt:
02/24/2004
Application #:
10054452
Filing Dt:
11/13/2001
Publication #:
US20030089961
Pub Dt:
05/15/2003
Title:
STI LEAKAGE REDUCTION
54
Patent #:
6700831
Issue Dt:
03/02/2004
Application #:
10054613
Filing Dt:
01/22/2002
Publication #:
US20020110043
Pub Dt:
08/15/2002
Title:
INTEGRATED MEMORY HAVING A PLURALITY OF MEMORY CELL ARRAYS AND METHOD FOR OPERATING THE INTEGRATED MEMORY
55
Patent #:
6800817
Issue Dt:
10/05/2004
Application #:
10055522
Filing Dt:
01/23/2002
Publication #:
US20020097616
Pub Dt:
07/25/2002
Title:
SEMICONDUCTOR COMPONENT FOR CONNECTION TO A TEST SYSTEM
56
Patent #:
6858799
Issue Dt:
02/22/2005
Application #:
10056356
Filing Dt:
01/24/2002
Publication #:
US20020096349
Pub Dt:
07/25/2002
Title:
ELECTRONIC COMPONENT WITH A SEMICONDUCTOR CHIP AND METHOD OF PRODUCING THE ELECTRONIC COMPONENT
57
Patent #:
6617213
Issue Dt:
09/09/2003
Application #:
10057065
Filing Dt:
01/25/2002
Publication #:
US20030143809
Pub Dt:
07/31/2003
Title:
METHOD FOR ACHIEVING HIGH SELF-ALIGNING VERTICAL GATE STUDS RELATIVE TO THE SUPPORT ISOLATION LEVEL
58
Patent #:
6701492
Issue Dt:
03/02/2004
Application #:
10057125
Filing Dt:
01/25/2002
Publication #:
US20020133793
Pub Dt:
09/19/2002
Title:
METHOD FOR THE DETERMINATION OF RESISTANCES AND CAPACITANCES OF A CIRCUIT DIAGRAM, WHICH REPRESENTS AN ELECTRICAL CIRCUIT
59
Patent #:
6976247
Issue Dt:
12/13/2005
Application #:
10057500
Filing Dt:
01/25/2002
Title:
GENERATING AN EXECUTABLE FILE
60
Patent #:
6877897
Issue Dt:
04/12/2005
Application #:
10060445
Filing Dt:
01/30/2002
Publication #:
US20020101906
Pub Dt:
08/01/2002
Title:
METHOD FOR DETERMINING THE TEMPERATURE OF A MEMORY CELL FROM THRESHOLD VOLTAGE SEMICONDUCTOR COMPONENT
61
Patent #:
6914328
Issue Dt:
07/05/2005
Application #:
10060447
Filing Dt:
01/30/2002
Publication #:
US20020103318
Pub Dt:
08/01/2002
Title:
ELECTRONIC COMPONENT WITH AN INSULATING LAYER FORMED FROM FLUORINATED NORBORNENE POLYMER AND METHOD FOR MANUFACTURING THE INSULATING LAYERS
62
Patent #:
6970589
Issue Dt:
11/29/2005
Application #:
10060450
Filing Dt:
01/30/2002
Publication #:
US20020103607
Pub Dt:
08/01/2002
Title:
METHOD FOR INSPECTING DEFECTS ON A MASK
63
Patent #:
6534369
Issue Dt:
03/18/2003
Application #:
10062755
Filing Dt:
01/31/2002
Publication #:
US20020072179
Pub Dt:
06/13/2002
Title:
FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
64
Patent #:
6709953
Issue Dt:
03/23/2004
Application #:
10062942
Filing Dt:
01/31/2002
Publication #:
US20030143818
Pub Dt:
07/31/2003
Title:
METHOD OF APPLYING A BOTTOM SURFACE PROTECTIVE COATING TO A WAFER, AND WAFER DICING METHOD
65
Patent #:
6687150
Issue Dt:
02/03/2004
Application #:
10064955
Filing Dt:
09/04/2002
Title:
REFERENCE VOLTAGE GENERATION FOR MEMORY CIRCUITS
66
Patent #:
6885597
Issue Dt:
04/26/2005
Application #:
10065011
Filing Dt:
09/10/2002
Publication #:
US20040047171
Pub Dt:
03/11/2004
Title:
SENSING TEST CIRCUIT
67
Patent #:
6614642
Issue Dt:
09/02/2003
Application #:
10065122
Filing Dt:
09/19/2002
Title:
CAPACITOR OVER PLUG STRUCTURE
68
Patent #:
6724026
Issue Dt:
04/20/2004
Application #:
10065123
Filing Dt:
09/19/2002
Publication #:
US20040056286
Pub Dt:
03/25/2004
Title:
MEMORY ARCHITECTURE WITH MEMORY CELL GROUPS
69
Patent #:
6639824
Issue Dt:
10/28/2003
Application #:
10065126
Filing Dt:
09/19/2002
Title:
MEMORY ARCHITECTURE
70
Patent #:
6621683
Issue Dt:
09/16/2003
Application #:
10065127
Filing Dt:
09/19/2002
Title:
MEMORY CELLS WITH IMPROVED RELIABILITY
71
Patent #:
6611449
Issue Dt:
08/26/2003
Application #:
10065166
Filing Dt:
09/24/2002
Title:
CONTACT FOR MEMORY CELLS
72
Patent #:
6707699
Issue Dt:
03/16/2004
Application #:
10065167
Filing Dt:
09/24/2002
Publication #:
US20040057273
Pub Dt:
03/25/2004
Title:
HISTORICAL INFORMATION STORAGE FOR INTEGRATED CIRCUITS
73
Patent #:
6903959
Issue Dt:
06/07/2005
Application #:
10065168
Filing Dt:
09/24/2002
Publication #:
US20040057275
Pub Dt:
03/25/2004
Title:
SENSING OF MEMORY INTEGRATED CIRCUITS
74
Patent #:
6806720
Issue Dt:
10/19/2004
Application #:
10065920
Filing Dt:
11/29/2002
Publication #:
US20040104731
Pub Dt:
06/03/2004
Title:
METHOD OF RELIABILITY TESTING
75
Patent #:
6940111
Issue Dt:
09/06/2005
Application #:
10065922
Filing Dt:
11/29/2002
Publication #:
US20040104754
Pub Dt:
06/03/2004
Title:
RADIATION PROTECTION IN INTEGRATED CIRCUITS
76
Patent #:
6579768
Issue Dt:
06/17/2003
Application #:
10066184
Filing Dt:
01/31/2002
Publication #:
US20020094650
Pub Dt:
07/18/2002
Title:
FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
77
Patent #:
6602745
Issue Dt:
08/05/2003
Application #:
10066206
Filing Dt:
01/31/2002
Publication #:
US20020094618
Pub Dt:
07/18/2002
Title:
FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
78
Patent #:
6841480
Issue Dt:
01/11/2005
Application #:
10067587
Filing Dt:
02/04/2002
Publication #:
US20030148614
Pub Dt:
08/07/2003
Title:
POLYELECTROLYTE DISPENSING POLISHING PAD, PRODUCTION THEREOF AND METHOD OF POLISHING A SUBSTRATE
79
Patent #:
6603694
Issue Dt:
08/05/2003
Application #:
10068789
Filing Dt:
02/05/2002
Publication #:
US20030147295
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Pub Dt:
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Title:
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Assignor
1
QIMONDA AG
Exec Dt:
10/09/2014
Assignee
1
INFINEON TECHNOLOGIES AG
AM CAMPEON 1-12
NEUBIBERG, GERMANY 85579
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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