|
|
|
|
|
Patent #:
|
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Issue Dt:
|
02/24/2004
|
Application #:
|
10135471
|
Filing Dt:
|
04/30/2002
|
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Publication #:
|
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Pub Dt:
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03/20/2003
| | | | |
|
Title:
|
METHOD FOR EXPERIMENTALLY VERIFYING IMAGING ERRORS IN OPTICAL EXPOSURE UNITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10135580
|
Filing Dt:
|
04/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
|
INTEGRATED CIRCUIT HAVING AN ANTIFUSE AND A METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
|
Application #:
|
10135684
|
Filing Dt:
|
04/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
METHOD FOR EXPERIMENTALLY VERIFYING IMAGING ERRORS IN PHOTOMASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10135686
|
Filing Dt:
|
04/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
METHOD AND DEVICE FOR INITIALISING AN ASYNCHRONOUS LATCH CHAIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
10137125
|
Filing Dt:
|
05/02/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
TEST CIRCUIT FOR TESTING A CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10137142
|
Filing Dt:
|
05/02/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
METHOD FOR SEMICONDUCTOR YIELD LOSS CALCULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10137906
|
Filing Dt:
|
05/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
SHEET-LIKE ELECTROOPTICAL COMPONENT, LIGHT-GUIDE CONFIGURATION FOR SERIAL, BIDIRECTIONAL SIGNAL TRANSMISSION AND OPTICAL PRINTED CIRCUIT BOARD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2004
|
Application #:
|
10138396
|
Filing Dt:
|
05/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
LAYOUT FOR THERMALLY SELECTED CROSS-POINT MRAM CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10138655
|
Filing Dt:
|
05/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/07/2002
| | | | |
|
Title:
|
LIGHT GUIDE CONFIGURATION FOR SERIAL BI-DIRECTIONAL SIGNAL TRANSMISSION, OPTICAL CIRCUIT BOARD, AND FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10139165
|
Filing Dt:
|
05/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
METHOD FOR IMPROVING A DOPING PROFILE FOR GAS PHASE DOPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
10139166
|
Filing Dt:
|
05/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/07/2002
| | | | |
|
Title:
|
METHOD FOR THE HYBRID-AUTOMATED MONITORING OF PRODUCTION MACHINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10139167
|
Filing Dt:
|
05/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
PRODUCTION MACHINE WITH CAPABILITY OF TRANSMITTING PRODUCTION INFORMATION AND METHOD FOR GENERATING EVENTS REGARDING PRODUCTION INFORMATION WHILE OPERATING THE PRODUCTION MACHINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2003
|
Application #:
|
10139168
|
Filing Dt:
|
05/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/07/2002
| | | | |
|
Title:
|
MEMORY CIRCUIT HAVING A PLURALITY OF MEMORY AREAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10139835
|
Filing Dt:
|
05/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CALIBRATING A TEST SYSTEM FOR AN INTEGRATED SEMICONDUCTOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10140393
|
Filing Dt:
|
05/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY CELL AND SEMICONDUCTOR COMPONENT AS WELL AS MANUFACTURING METHODS THEREFORE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
10142518
|
Filing Dt:
|
05/09/2002
|
|
Title:
|
LOW RESISTIVITY DEEP TRENCH FILL FOR DRAM AND EDRAM APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
10142537
|
Filing Dt:
|
05/09/2002
|
|
Title:
|
TRANSISTOR AND METHOD OF MANUFACTURING A TRANSISTOR HAVING A SHALLOW JUNCTION FORMATION USING A TWO STEP EPI LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10143600
|
Filing Dt:
|
05/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR GENERATING A SECOND SIGNAL HAVING A CLOCK BASED ON A SECOND CLOCK FROM A FIRST SIGNAL HAVING A FIRST CLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10143627
|
Filing Dt:
|
05/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/14/2002
| | | | |
|
Title:
|
CIRCUIT MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10143673
|
Filing Dt:
|
05/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
METHOD OF FORMING SURFACE-SMOOTHING LAYER FOR SEMICONDUCTOR DEVICES WITH MAGNETIC MATERIAL LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10144572
|
Filing Dt:
|
05/13/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
USE OF AN ON-DIE TEMPERATURE SENSING SCHEME FOR THERMAL PROTECTION OF DRAMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10144579
|
Filing Dt:
|
05/13/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
USE OF DQ PINS ON A RAM MEMORY CHIP FOR A TEMPERATURE SENSING PROTOCOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10144597
|
Filing Dt:
|
05/13/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
IMPLEMENTATION OF A TEMPERATURE SENSOR TO CONTROL INTERNAL CHIP VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10145393
|
Filing Dt:
|
05/14/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
|
Title:
|
WIRING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
10145579
|
Filing Dt:
|
05/14/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR REDUCING REFLEXIONS IN A MEMORY BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
10146582
|
Filing Dt:
|
05/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
|
INTEGRATED SEMICONDUCTOR CIRCUIT HAVING TRANSISTORS THAT ARE SWITCHED WITH DIFFERENT FREQUENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2003
|
Application #:
|
10146976
|
Filing Dt:
|
05/16/2002
|
|
Title:
|
METHOD OF MANUFACTURING MRAM OFFSET CELLS IN A DAMASCENE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10147543
|
Filing Dt:
|
05/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
|
Title:
|
METHOD FOR FABRICATING A LITHOGRAPHIC REFLECTION MASK IN PARTICULAR FOR THE PATTERNING OF A SEMICONDUCTOR WAFER, AND A REFLECTION MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10147545
|
Filing Dt:
|
05/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
|
METHOD OF MATCHING DIFFERENT SIGNAL PROPAGATION TIMES BETWEEN A CONTROLLER AND AT LEAST TWO PROCESSING UNITS, AND A COMPUTER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10148241
|
Filing Dt:
|
10/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
| | | | |
|
Title:
|
METHOD FOR CHEMICAL-MECHANICAL POLISHING OF LAYERS MADE FROM METALS FROM THE PLATINUM GROUP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10149892
|
Filing Dt:
|
10/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
CASING CONFIGURATION OF A SEMICODUCTOR COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
10150340
|
Filing Dt:
|
05/17/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
METHOD AND CIRCUIT ARRANGEMENT FOR READING OUT AND FOR STORING BINARY MEMORY CELL SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10151088
|
Filing Dt:
|
05/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
|
INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10151090
|
Filing Dt:
|
05/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10151989
|
Filing Dt:
|
05/21/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
|
METHOD AND DEVICE FOR TESTING A MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10151990
|
Filing Dt:
|
05/21/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
METHOD FOR TESTING SEMICONDUCTOR CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10152950
|
Filing Dt:
|
05/21/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2003
| | | | |
|
Title:
|
METHOD FOR READING AND STORING BINARY MEMORY CELL SIGNALS AND CIRCUIT ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10153045
|
Filing Dt:
|
05/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
|
Title:
|
METHOD FOR FABRICATING AN INSULATION COLLAR IN A TRENCH CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10153766
|
Filing Dt:
|
05/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY WITH JOINTLY USABLE FUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10154297
|
Filing Dt:
|
05/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
ANTIREFLECTIVE, LAYER-FORMING COMPOSITION, LAYER CONFIGURATION CONTAINING THE ANTIREFLECTIVE LAYER, AND PROCESS FOR PRODUCING THE ANTIREFLECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
10154340
|
Filing Dt:
|
05/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR CIRCUIT HAVING A STRONGLY POLARIZABLE DIELECTRIC OR FERROELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10154343
|
Filing Dt:
|
05/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
SEMICONDUCTOR CHIP WITH TRIMMABLE OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
10154476
|
Filing Dt:
|
05/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
BUILT OFF SELF TEST (BOST) IN THE KERF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10154597
|
Filing Dt:
|
05/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10155337
|
Filing Dt:
|
05/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
SELF-ADHERING CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
10156482
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
SEMICONDUCTOR SUBSTRATE HOLDER FOR CHEMICAL-MECHANICAL POLISHING CONTAINING A MOVABLE PLATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2003
|
Application #:
|
10156484
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
|
METALLIZING METHOD FOR DIELECTRICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10156536
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
MEMORY MODULE HAVING A MEMORY CELL AND METHOD FOR FABRICATING THE MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10156538
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
IMAGING SYSTEM AND METHOD FOR POSITIONING A MEASURING TIP ONTO A CONTACT REGION OF A MICROCHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10157175
|
Filing Dt:
|
05/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
|
Title:
|
ELECTRONIC STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
10157726
|
Filing Dt:
|
05/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
|
Title:
|
DATA OUTPUT INTERFACE, IN PARTICULAR FOR SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
10158031
|
Filing Dt:
|
05/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
|
Title:
|
MEMORY CHIP HAVING A TEST MODE AND METHOD FOR CHECKING MEMORY CELLS OF A REPAIRED MEMORY CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
10158267
|
Filing Dt:
|
05/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
|
Title:
|
METHOD AND DEVICE FOR MEASURING THE PHASE SHIFT BETWEEN A PERIODIC SIGNAL AND AN OUTPUT SIGNAL AT AN OUTPUT OF AN ELECTRONIC COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2003
|
Application #:
|
10158271
|
Filing Dt:
|
05/30/2002
|
|
Publication #:
|
|
Pub Dt:
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12/05/2002
| | | | |
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Title:
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METHOD AND DEVICE FOR MEASURING A TEMPERATURE IN AN ELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
|
04/27/2004
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Application #:
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10158275
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
|
12/05/2002
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Title:
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SEMICONDUCTOR MEMORY WITH A SIGNAL PATH
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Patent #:
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Issue Dt:
|
02/25/2003
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Application #:
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10158465
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD FOR FABRICATING AN INTEGRATED CIRCUIT WITH UNDERCUT ETCHING
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|
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Patent #:
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Issue Dt:
|
12/09/2003
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Application #:
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10158733
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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ALTERNATING PHASE MASK
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Patent #:
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Issue Dt:
|
06/03/2003
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Application #:
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10158982
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Filing Dt:
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05/30/2002
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Title:
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ISOLATING A VERTICAL GATE CONTACT STRUCTURE
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Patent #:
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Issue Dt:
|
04/20/2004
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Application #:
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10159155
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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02/20/2003
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Title:
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METHOD FOR FABRICATING A GATE STACK IN VERY LARGE SCALE INTEGRATED SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
|
09/02/2003
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Application #:
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10159156
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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MEMORY ELEMENT WITH MOLECULAR OR POLYMERIC LAYERS, MEMORY CELL, MEMORY ARRAY, AND SMART CARD
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|
|
|
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Patent #:
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Issue Dt:
|
09/16/2003
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Application #:
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10159169
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Filing Dt:
|
05/31/2002
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Title:
|
SUPPORT LINER FOR ISOLATION TRENCH HEIGHT CONTROL IN VERTICAL DRAM PROCESSING
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/28/2004
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Application #:
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10159262
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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PLASMA-ETCHING PROCESS FOR MOLYBDENUM SILICON NITRIDE LAYERS ON HALF-TONE PHASE MASKS BASED ON GAS MIXTURES CONTAINING MONOFLUOROMETHANE AND OXYGEN
|
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Patent #:
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Issue Dt:
|
06/01/2004
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Application #:
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10159848
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Filing Dt:
|
05/31/2002
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Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
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Title:
|
SEMICONDUCTOR CHIP, MEMORY MODULE AND METHOD FOR TESTING THE SEMICONDUCTOR CHIP
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Patent #:
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|
Issue Dt:
|
01/16/2007
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Application #:
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10159849
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
|
12/05/2002
| | | | |
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Title:
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TEST DEVICE FOR DYNAMIC MEMORY MODULES
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Patent #:
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Issue Dt:
|
10/21/2003
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Application #:
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10159858
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Filing Dt:
|
05/31/2002
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Publication #:
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Pub Dt:
|
12/05/2002
| | | | |
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Title:
|
MEMORY MODULE, METHOD FOR ACTIVATING A MEMORY CELL, AND METHOD FOR REPAIRING A DEFECTIVE MEMORY CELL
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|
|
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Patent #:
|
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Issue Dt:
|
06/15/2004
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Application #:
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10159861
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Filing Dt:
|
05/31/2002
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|
Publication #:
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Pub Dt:
|
03/13/2003
| | | | |
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Title:
|
MATERIAL AND ADDITIVE FOR HIGHLY CROSSLINKED CHEMICALLY AND THERMALLY STABLE POLYHYDROXYAMIDE POLYMERS
|
|
|
|
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Patent #:
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|
Issue Dt:
|
08/24/2004
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Application #:
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10160446
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Filing Dt:
|
05/30/2002
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Publication #:
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Pub Dt:
|
02/13/2003
| | | | |
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Title:
|
PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR MEMORY DEVICE
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|
|
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Patent #:
|
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Issue Dt:
|
12/27/2005
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Application #:
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10161867
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Filing Dt:
|
06/03/2002
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Publication #:
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Pub Dt:
|
12/04/2003
| | | | |
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Title:
|
LITHOGRAPHY ALIGNMENT AND OVERLAY MEASUREMENT MARKS FORMED BY RESIST MASK BLOCKING FOR MRAMS
|
|
|
|
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Patent #:
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|
Issue Dt:
|
02/22/2005
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Application #:
|
10161908
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Filing Dt:
|
06/04/2002
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|
Publication #:
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Pub Dt:
|
12/04/2003
| | | | |
|
Title:
|
FERROELECTRIC MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY
|
|
|
|
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Patent #:
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Issue Dt:
|
02/24/2004
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Application #:
|
10163007
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Filing Dt:
|
06/05/2002
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Publication #:
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Pub Dt:
|
12/05/2002
| | | | |
|
Title:
|
METHOD FOR FABRICATING POSITIONALLY EXACT SURFACE-WIDE MEMBRANE MASKS
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
06/07/2005
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Application #:
|
10163054
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Filing Dt:
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06/05/2002
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Publication #:
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Pub Dt:
|
12/05/2002
| | | | |
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Title:
|
METHOD FOR CARRYING OUT A RULE-BASED OPTICAL PROXIMITY CORRECTION WITH SIMULTANEOUS SCATTER BAR INSERTION
|
|
|
|
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Patent #:
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|
Issue Dt:
|
01/06/2004
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Application #:
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10164213
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Filing Dt:
|
06/06/2002
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Publication #:
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Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
METHOD FOR RECOGNIZING AND REPLACING DEFECTIVE MEMORY CELLS IN A MEMORY
|
|
|
|
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Patent #:
|
|
Issue Dt:
|
03/30/2004
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Application #:
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10164453
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Filing Dt:
|
06/06/2002
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Publication #:
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Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
METHOD FOR COMBINING LOGIC-BASED CIRCUIT UNITS AND MEMORY-BASED CIRCUIT UNITS AND CIRCUIT ARRANGEMENT
|
|
|
|
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Patent #:
|
|
Issue Dt:
|
02/08/2005
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Application #:
|
10164549
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Filing Dt:
|
06/07/2002
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|
Publication #:
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Pub Dt:
|
11/21/2002
| | | | |
|
Title:
|
METHOD FOR FABRICATING A HARD MASK
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2004
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Application #:
|
10164550
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Filing Dt:
|
06/07/2002
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|
Publication #:
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Pub Dt:
|
01/09/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING RESIST STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
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Application #:
|
10164770
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Filing Dt:
|
06/07/2002
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|
Publication #:
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Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
DEVICE FOR AND METHOD OF EXAMINING THE SIGNAL PERFORMANCE OF SEMICONDUCTOR CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2003
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Application #:
|
10165171
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Filing Dt:
|
06/07/2002
|
|
Title:
|
STRUCTURE AND METHOD FOR DUAL WORK FUNCTION LOGIC DEVICES IN VERTICAL DRAM PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10165277
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Filing Dt:
|
06/10/2002
|
|
Publication #:
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Pub Dt:
|
12/11/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
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Application #:
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10165911
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Filing Dt:
|
06/10/2002
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|
Publication #:
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Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING SCATTER LINES IN MASK STRUCTURES FOR FABRICATING INTEGRATED ELECTRICAL CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
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Application #:
|
10166837
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Filing Dt:
|
06/11/2002
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Publication #:
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Pub Dt:
|
12/11/2003
| | | | |
|
Title:
|
AUTO-ADJUSTMENT OF SELF-REFRESH FREQUENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
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Application #:
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10166962
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Filing Dt:
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06/11/2002
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|
Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
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Title:
|
INTEGRATED MEMORY HAVING A MEMORY CELL ARRAY WITH A PLURALITY OF SEGMENTS AND METHOD FOR OPERATING THE INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
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Application #:
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10166963
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Filing Dt:
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06/11/2002
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Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT AND METHOD FOR MANUFACTURING THE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
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Application #:
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10166981
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Filing Dt:
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06/11/2002
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Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
OUTPUT DRIVERS FOR IC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10167785
|
Filing Dt:
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06/12/2002
|
|
Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
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Title:
|
METHOD FOR PRODUCING AND/OR RENEWING AN ETCHING MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10171098
|
Filing Dt:
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06/13/2002
|
|
Publication #:
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Pub Dt:
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01/16/2003
| | | | |
|
Title:
|
TRANSMITTING DATA INTO A MEMORY CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
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Application #:
|
10171255
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Filing Dt:
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06/12/2002
|
|
Publication #:
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Pub Dt:
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12/18/2003
| | | | |
|
Title:
|
VERTICAL ACCESS TRANSISTOR WITH CURVED CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10171643
|
Filing Dt:
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06/14/2002
|
|
Publication #:
|
|
Pub Dt:
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12/18/2003
| | | | |
|
Title:
|
INTEGRATED MEMORY CIRCUIT AND METHOD OF FORMING AN INTEGRATED MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
10171668
|
Filing Dt:
|
06/14/2002
|
|
Publication #:
|
|
Pub Dt:
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11/14/2002
| | | | |
|
Title:
|
DATA MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10173285
|
Filing Dt:
|
06/17/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR TESTING A DEVICE FOR STORING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2004
|
Application #:
|
10174646
|
Filing Dt:
|
06/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
|
Title:
|
ALTERNATING PHASE MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10174727
|
Filing Dt:
|
06/19/2002
|
|
Publication #:
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|
Pub Dt:
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12/25/2003
| | | | |
|
Title:
|
FUSE CONFIGURATION WITH MODIFIED CAPACITOR BORDER LAYOUT FOR A SEMICONDUCTOR STORAGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10175591
|
Filing Dt:
|
06/19/2002
|
|
Publication #:
|
|
Pub Dt:
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02/27/2003
| | | | |
|
Title:
|
METHOD FOR CONTROLLING THE QUALITY OF A LITHOGRAPHIC STRUCTURING STEP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10178249
|
Filing Dt:
|
06/24/2002
|
|
Publication #:
|
|
Pub Dt:
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01/16/2003
| | | | |
|
Title:
|
DELAY LOCKED LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10178251
|
Filing Dt:
|
06/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
|
Title:
|
DELAY LOCKED LOOP FOR GENERATING COMPLEMENTARY CLOCK SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10178252
|
Filing Dt:
|
06/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR BIDIRECTIONAL SIGNAL TRANSMISSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
10179002
|
Filing Dt:
|
06/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
MEMORY CHIP AND APPARATUS FOR TESTING A MEMORY CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10180254
|
Filing Dt:
|
06/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2004
| | | | |
|
Title:
|
CURRENT MEASUREMENT CIRCUIT AND METHOD FOR VOLTAGE REGULATED SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10180438
|
Filing Dt:
|
06/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
COMPOSITION AND PROCESS FOR THE PRODUCTION OF A POROUS LAYER USING THE COMPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10180440
|
Filing Dt:
|
06/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
PROCESS AND DEVICE FOR THE ABRASIVE MACHINING OF SURFACES, IN PARTICULAR SEMICONDUCTOR WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10180818
|
Filing Dt:
|
06/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
|
Title:
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DEVICE FOR DRIVING A MEMORY CELL OF A MEMORY MODULE BY MEANS OF A CHARGE STORE
|
|
