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11/04/2003
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10210645
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07/31/2002
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04/20/2004
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10210665
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08/01/2002
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02/06/2003
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08/09/2005
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08/01/2002
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02/06/2003
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02/24/2004
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10210735
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07/31/2002
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03/27/2003
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08/29/2006
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10210741
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07/31/2002
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02/06/2003
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01/20/2004
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07/31/2002
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02/05/2004
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02/08/2005
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07/31/2002
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02/05/2004
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01/25/2005
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10210962
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08/02/2002
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02/05/2004
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08/09/2005
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10211234
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08/05/2002
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07/31/2003
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06/13/2006
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10211235
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08/05/2002
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07/31/2003
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MASS STORAGE DEVICE ARCHITECTURE AND OPERATION
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12/13/2005
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08/05/2002
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07/31/2003
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02/22/2005
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08/05/2002
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02/06/2003
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05/06/2003
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08/08/2002
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02/13/2003
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03/23/2004
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08/08/2002
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02/13/2003
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12/28/2004
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08/08/2002
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02/13/2003
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05/09/2006
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08/08/2002
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02/13/2003
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05/10/2005
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10215453
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08/09/2002
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02/13/2003
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02/13/2007
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08/09/2002
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02/12/2004
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07/27/2004
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08/12/2002
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02/13/2003
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TRANSISTOR CONFIGURATION FOR A BANDGAP CIRCUIT
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07/27/2004
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08/12/2002
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02/13/2003
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04/13/2004
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08/13/2002
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02/27/2003
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04/06/2004
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08/13/2002
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02/19/2004
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ATOMIC FORCE MICROSCOPY SCANNING METHODS
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11/25/2003
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08/14/2002
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02/06/2003
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05/17/2005
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08/15/2002
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05/15/2003
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12/20/2005
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10/24/2002
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01/29/2004
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FIN FIELD-EFFECT TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF
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03/09/2004
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08/16/2002
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02/19/2004
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07/01/2003
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10223034
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08/16/2002
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03/13/2003
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07/15/2003
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10223038
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08/16/2002
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01/30/2003
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11/16/2004
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08/19/2002
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02/19/2004
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06/15/2004
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08/19/2002
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02/20/2003
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08/31/2004
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08/20/2002
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02/20/2003
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03/28/2006
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08/22/2002
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02/27/2003
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07/20/2004
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08/23/2002
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03/27/2003
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05/30/2006
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08/23/2002
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02/26/2004
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02/01/2005
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08/23/2002
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02/27/2003
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02/17/2004
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08/23/2002
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01/23/2003
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05/10/2005
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08/26/2002
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02/27/2003
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10/24/2006
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08/27/2002
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02/27/2003
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11/11/2003
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08/29/2002
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03/13/2003
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SEMICONDUCTOR DEVICE HAVING CAVITIES WITH SUBMICROMETER DIMENSIONS GENERATED BY A SWELLING PROCESS
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05/11/2004
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08/29/2002
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03/06/2003
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02/24/2004
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10231785
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08/29/2002
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05/01/2003
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04/12/2005
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10231882
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08/30/2002
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03/06/2003
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05/24/2005
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08/30/2002
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03/06/2003
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08/09/2005
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08/28/2002
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03/04/2004
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METHOD OF FORMING A GATE CONTACT IN A SEMICONDUCTOR DEVICE
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06/22/2004
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09/03/2002
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03/06/2003
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02/17/2004
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09/03/2002
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03/06/2003
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06/01/2004
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09/03/2002
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03/06/2003
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03/01/2005
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09/03/2002
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03/13/2003
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METHOD FOR PRODUCING A STRUCTURED LAYER ON A SEMICONDUCTOR SUBSTRATE
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12/14/2004
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09/03/2002
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04/03/2003
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02/21/2006
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09/03/2002
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03/06/2003
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08/16/2005
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09/03/2002
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03/13/2003
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12/13/2005
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09/03/2002
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08/07/2003
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SILICON RESIST FOR PHOTOLITHOGRAPHY AT SHORT EXPOSURE WAVELENGTHS AND PROCESS FOR MAKING PHOTORESISTS
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06/15/2004
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10233968
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09/03/2002
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03/06/2003
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VOLATILE SEMICONDUCTOR MEMORY AND MOBILE DEVICE
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11/23/2004
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10233970
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09/03/2002
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Pub Dt:
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03/06/2003
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Title:
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06/08/2004
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10234077
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09/03/2002
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04/10/2003
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06/01/2004
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10234078
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09/03/2002
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03/13/2003
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Title:
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ELECTRONIC CIRCUIT FOR GENERATING AN OUTPUT VOLTAGE HAVING A DEFINED TEMPERATURE DEPENDENCE
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06/29/2004
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10234079
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09/03/2002
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04/17/2003
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Title:
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05/11/2004
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10234547
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09/04/2002
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04/10/2003
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Title:
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02/22/2005
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10234864
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09/04/2002
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03/04/2004
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Title:
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MRAM MTJ STACK TO CONDUCTIVE LINE ALIGNMENT METHOD
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04/27/2004
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10235050
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09/05/2002
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03/06/2003
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Title:
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OUTPUT DRIVER CIRCUIT AND METHOD FOR ADJUSTING A DRIVER DEVICE
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05/16/2006
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10236448
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09/06/2002
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03/11/2004
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OPTICAL MEASUREMENT SYSTEM AND METHOD
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10/19/2004
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10236895
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09/06/2002
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04/10/2003
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Title:
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ELECTRONIC COMPONENT WITH AT LEAST ONE SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING THE ELECTRONIC COMPONENT
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09/09/2003
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10237410
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09/09/2002
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02/27/2003
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Title:
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DIGITAL MEMORY CIRCUIT AND METHOD OF MANUFACTURING THE CIRCUIT
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07/18/2006
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10237543
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09/09/2002
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03/20/2003
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Title:
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Method for fabricating an integrated semiconductor circuit to prefent formation of voids
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11/20/2007
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10238819
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09/10/2002
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03/27/2003
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Title:
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METHOD OF TESTING A MAPPING OF AN ELECTRICAL CIRCUIT
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08/31/2004
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10238940
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09/10/2002
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03/27/2003
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Title:
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ELECTRONIC DEVICE HAVING A TRIMMING POSSIBILITY AND AT LEAST ONE SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING THE ELECTRONIC DEVICE
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01/30/2007
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10241032
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09/11/2002
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03/11/2004
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CIRCUIT AND METHOD FOR TESTING EMBEDDED DRAM CIRCUITS THROUGH DIRECT ACCESS MODE
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08/09/2005
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10241546
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09/11/2002
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03/13/2003
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METHOD OF CONNECTING A DEVICE TO A SUPPORT, AND PAD FOR ESTABLISHING A CONNECTION BETWEEN A DEVICE AND A SUPPORT
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05/03/2005
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10242894
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09/12/2002
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03/18/2004
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SEMICONDUCTOR WAFER TESTING SYSTEM
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06/29/2004
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10243067
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09/13/2002
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03/27/2003
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INTEGRATED CIRCUIT HAVING A CURRENT MEASURING UNIT
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10/10/2006
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10243544
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09/12/2002
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03/18/2004
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Title:
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SYSTEM AND METHOD FOR TESTING ONE OR MORE DIES ON A SEMICONDUCTOR WAFER
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02/24/2004
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10244256
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09/16/2002
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05/08/2003
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METHOD OF ATTACHING SEMICONDUCTOR DEVICES ON A SWITCHING DEVICE AND SUCH AN ATTACHED DEVICE
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04/26/2005
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10244257
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09/16/2002
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05/29/2003
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Title:
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PHOTOSENSITIVE FORMULATION FOR BUFFER COATINGS, FILM CONTAINING THE PHOTOSENSITIVE FORMULATION, AND METHOD FOR FABRICATING ELECTRONICS WITH THE PHOTOSENSITIVE FORMULATION
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10/19/2004
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10244258
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09/16/2002
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03/20/2003
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Title:
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EVALUATION CONFIGURATION FOR SEMICONDUCTOR MEMORIES
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06/15/2004
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10244281
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09/16/2002
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03/20/2003
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Title:
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MARK CONFIGURATION, WAFER WITH AT LEAST ONE MARK CONFIGURATION AND METHOD FOR THE FABRICATION OF AT LEAST ONE MARK CONFIGURATION
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10/24/2006
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10244301
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09/16/2002
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Pub Dt:
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05/29/2003
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Title:
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BIS-O-NITROPHENOLS DERIVATIVES AND POLY-O-HYDROXYAMIDES, POLYBENZOXAZOLES, MATERIALS, AND MICROELECTRONIC DEVICES MADE THEREFROM
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08/09/2005
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10244766
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09/16/2002
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03/18/2004
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Title:
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TECHNIQUES FOR ELECTRICALLY CHARACTERIZING TUNNEL JUNCTION FILM STACKS WITH LITTLE OR NO PROCESSING
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07/04/2006
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10244802
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09/16/2002
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07/17/2003
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Title:
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POLYBENZOXAZOLES FROM POLY-O-HYDROXYAMIDE, NOVEL POLY-O-HYDROXYAMIDES, PREPARATION PROCESSES THEREFOR, AND THEIR APPLICATION IN MICROELECTRONICS
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03/15/2005
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10244839
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09/16/2002
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06/05/2003
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BIS-O-AMINOPHENOL DERIVATIVES, POLY-O-HYDROXYAMIDES, AND POLYBENZOXAZOLES, USABLE IN PHOTOSENSITIVE COMPOSITIONS, DIELECTRICS, BUFFER COATINGS, AND MICROELECTRONICS
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01/10/2006
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10245622
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09/17/2002
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06/05/2003
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METHOD AND APPARATUS FOR REDUCING THE CURRENT CONSUMPTION OF AN ELECTRONIC CIRCUIT
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06/15/2004
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10245626
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09/17/2002
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03/20/2003
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METHOD FOR TESTING INTEGRATED SEMICONDUCTOR MEMORY DEVICES
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05/09/2006
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10245629
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09/17/2002
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03/20/2003
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INTEGRATED CIRCUIT AND METHOD FOR OPERATING THE INTEGRATED CIRCUIT
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08/24/2004
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10247572
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09/19/2002
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03/20/2003
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METHOD FOR OPERATING A SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY
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09/07/2004
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10247574
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09/19/2002
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04/10/2003
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WAFER WITH ADDITIONAL CIRCUIT PARTS IN THE KERF AREA FOR TESTING INTEGRATED CIRCUITS ON THE WAFER
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03/15/2005
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10247575
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09/19/2002
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03/20/2003
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METHOD FOR REWIRING PADS IN A WAFER-LEVEL PACKAGE
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02/08/2005
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10247576
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09/19/2002
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03/27/2003
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METHOD OF INSULATING INTERCONNECTS, AND MEMORY CELL ARRAY WITH INSULATED INTERCONNECTS
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02/05/2008
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10247577
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09/19/2002
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03/20/2003
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CIRCUIT CONFIGURATION FOR RECEIVING A DATA SIGNAL
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08/15/2006
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10248232
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12/30/2002
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07/01/2004
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PATTERN TRANSFER IN DEVICE FABRICATION
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11/23/2004
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10248233
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12/30/2002
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07/01/2004
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IMPROVED DEEP ISOLATION TRENCHES
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11/09/2004
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10248253
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12/31/2002
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07/01/2004
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REDUCING STRESS IN INTEGRATED CIRCUITS
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02/08/2005
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10248801
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02/20/2003
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08/26/2004
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TRENCH CAPACITOR WITH BURIED STRAP
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02/22/2005
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10248861
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02/25/2003
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08/26/2004
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FERROELECTRIC MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY
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04/06/2004
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10248874
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02/26/2003
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08/28/2003
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CONTROL CIRCUIT FOR AN S-DRAM
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05/24/2005
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10248897
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02/28/2003
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09/02/2004
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AVOIDING SHORTING IN CAPACITORS
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12/07/2004
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10248949
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03/05/2003
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09/23/2004
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METHOD OF PLANARIZING SUBSTRATES
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08/23/2005
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10248950
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03/05/2003
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09/09/2004
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03/29/2005
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10248985
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03/06/2003
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09/09/2004
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NONVOLATILE MEMORY CELL
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11/16/2004
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10249029
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03/11/2003
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09/18/2003
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LATENCY TIME CIRCUIT FOR AN S-DRAM
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12/23/2003
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10249228
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03/24/2003
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SELF-ALIGNED BURIED STRAP PROCESS USING DOPED HDP OXIDE
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01/30/2007
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10249528
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04/17/2003
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Pub Dt:
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10/21/2004
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Title:
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MAGNETICALLY LINED CONDUCTORS
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