|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10249531
|
Filing Dt:
|
04/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/21/2004
| | | | |
|
Title:
|
LOW SWITCHING FIELD MAGNETIC ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10249532
|
Filing Dt:
|
04/17/2003
|
|
Title:
|
MAGNETIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10250133
|
Filing Dt:
|
06/05/2003
|
|
Title:
|
MASKLESS ARRAY PROTECTION PROCESS FLOW FOR FORMING INTERCONNECT VIAS IN MAGNETIC RANDOM ACCESS MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2004
|
Application #:
|
10250201
|
Filing Dt:
|
06/12/2003
|
|
Title:
|
ERROR DETECTION AND CORRECTION METHOD AND APPARATUS IN A MAGNETORESISTIVE RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10250209
|
Filing Dt:
|
06/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
ELEMENT STORAGE LAYER IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10250211
|
Filing Dt:
|
06/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
|
Title:
|
REDUCING MEMORY FAILURES IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
10252331
|
Filing Dt:
|
09/23/2002
|
|
Title:
|
DELAY LOCKED LOOP COMPENSATING FOR EFFECTIVE LOADS OF OFF-CHIP DRIVERS AND METHODS FOR LOCKING A DELAY LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10252449
|
Filing Dt:
|
09/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
SEMICONDUCTOR COMPONENT AND METHOD FOR ITS PRODUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10252453
|
Filing Dt:
|
09/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CONNECTING AT LEAST ONE CHIP TO AN EXTERNAL WIRING CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10252995
|
Filing Dt:
|
09/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
DIGITAL MAGNETIC MEMORY CELL DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10253001
|
Filing Dt:
|
09/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
ELECTRONIC CIRCUIT WITH A DRIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10253148
|
Filing Dt:
|
09/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
TOPOGRAPHY CORRECTION FOR TESTING OF REDUNDANT ARRAY ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10253196
|
Filing Dt:
|
09/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
METHOD OF ETCHING A LAYER IN A TRENCH AND METHOD OF FABRICATING A TRENCH CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10253465
|
Filing Dt:
|
09/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
METHOD FOR REPLACING DEFECTIVE MEMORY CELLS IN DATA PROCESSING APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10253793
|
Filing Dt:
|
09/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
APPARATUS FOR SIGNALING THAT A PREDETERMINED TIME VALUE HAS ELAPSED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10254305
|
Filing Dt:
|
09/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
DQS POSTAMBLE NOISE SUPPRESSION BY FORCING A MINIMUM PULSE LENGTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10254405
|
Filing Dt:
|
09/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
PRODUCTION METHOD FOR A HALFTONE PHASE MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10254467
|
Filing Dt:
|
09/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR ENABLING A VENDOR MODE ON AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
10254470
|
Filing Dt:
|
09/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2003
| | | | |
|
Title:
|
FLUORESCENT NAPHTHALENE -1,4,5,8-TETRACARBOXYLIC BISIMIDES WITH AN ELECTRON-DONATING SUBSTITUENT ON THE NUCLEUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
10254692
|
Filing Dt:
|
09/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
TRENCH CAPACITOR AND METHOD FOR MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2004
|
Application #:
|
10254694
|
Filing Dt:
|
09/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
METHOD FOR INTEGRATING IMPERFECT SEMICONDUCTOR MEMORY DEVICES IN DATA PROCESSING APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10255015
|
Filing Dt:
|
09/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
RAPID DEPOSITION OF BOROSILICATE GLASS FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2005
|
Application #:
|
10255767
|
Filing Dt:
|
09/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR MONITORING INTERNAL VOLTAGES ON AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
10256181
|
Filing Dt:
|
09/26/2002
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF USING ROW COMPRESSION TEST MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10256463
|
Filing Dt:
|
09/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
METHOD OF SELF-REPAIRING DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
10256539
|
Filing Dt:
|
09/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
INDICATION OF THE SYSTEM OPERATION FREQUENCY TO A DRAM DURING POWER-UP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10258354
|
Filing Dt:
|
02/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
|
Title:
|
FIELD EFFECT TRANSISTOR AND METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10259100
|
Filing Dt:
|
09/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
BITLINE EQUALIZATION SYSTEM FOR A DRAM INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10260872
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
ELECTRONIC COMPONENT WITH FLEXIBLE CONTACTING PADS AND METHOD FOR PRODUCING THE ELECTRONIC COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10260899
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10260919
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
ON-DIE DETECTION OF THE SYSTEM OPERATION FREQUENCY IN A DRAM TO ADJUST DRAM OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10261034
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2003
| | | | |
|
Title:
|
POLY-O-HYDROXYAMIDES, POLYBENZOXAZOLES, PROCESSES FOR PRODUCING POLY-O-HYDROXYAMIDES, PROCESSES FOR PRODUCING POLYBENZOXAZOLES, DIELECTRICS INCLUDING A POLYBENZOXAZOLE, ELECTRONIC COMPONENTS INCLUDING THE DIELECTRICS, AND PROCESSES FOR MANUFACTURING THE ELECTRONIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10261194
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
DATA PROCESSING SYSTEM FOR DESIGNING A LAYOUT OF AN INTEGRATED ELECTRONIC CIRCUIT HAVING A MULTIPLICITY OF ELECTRONIC COMPONENTS AND METHOD OF DESIGNING A LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10261200
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
SCALABLE DRIVER DEVICE AND RELATED INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
10261219
|
Filing Dt:
|
09/30/2002
|
|
Title:
|
PROCESS FLOW FOR THICK ISOLATION COLLAR WITH REDUCED LENGTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10261709
|
Filing Dt:
|
10/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
SPACER INTEGRATION SCHEME IN MRAM TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10261849
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING A SEMICONDUCTOR STRUCTURE, AND USE OF THE METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10262117
|
Filing Dt:
|
10/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
METHOD OF FABRICATING A MICROSTRUCTURE AND PHOTOLITHOGRAPHY TRIMMING MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10262172
|
Filing Dt:
|
10/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
INTEGRATED MEMORY DEVICE, METHOD OF OPERATING AN INTEGRATED MEMORY, AND MEMORY SYSTEM HAVING A PLURALITY OF INTEGRATED MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
10262179
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
METHOD OF PRODUCING BIOCOMPATIBLE STRUCTURES AND BIOCOMPATIBLE MICROCHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10262181
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
SEMICONDUCTOR WAFER POD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10265964
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/08/2004
| | | | |
|
Title:
|
BANK ADDRESS MAPPING ACCORDING TO BANK RETENTION TIME IN DYNAMIC RANDOM ACCESS MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2004
|
Application #:
|
10266187
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
APPARATUS FOR GENERATING MEMORY-INTERNAL COMMAND SIGNALS FROM A MEMORY OPERATION COMMAND
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10266188
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
STORAGE CELL FIELD AND METHOD OF PRODUCING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
10266190
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
DIGITAL MEMORY CIRCUIT HAVING A PLURALITY OF SEGMENTED MEMORY AREAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10266295
|
Filing Dt:
|
10/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
INTEGRABLE, CONTROLLABLE DELAY DEVICE, DELAY DEVICE IN A CONTROL LOOP, AND METHOD FOR DELAYING A CLOCK SIGNAL USING A DELAY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
10266296
|
Filing Dt:
|
10/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
DELAY LOCKED LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10266322
|
Filing Dt:
|
10/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MODULE HAVING A CONFIGURABLE DATA WIDTH OF AN OUTPUT BUS, AND A HOUSING CONFIGURATION HAVING A SEMICONDUCTOR MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10266353
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10266354
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR PROCESSING DATA, AND METHOD FOR IDENTIFYING AN OPERATING STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
10266355
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
DIGITAL MEMORY CIRCUIT HAVING A PLURALITY OF MEMORY AREAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
10267224
|
Filing Dt:
|
10/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING A MICROCONTACT SPRING ON A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10267262
|
Filing Dt:
|
10/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
VOLTAGE REGULATOR WITH DISTRIBUTED OUTPUT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10267335
|
Filing Dt:
|
10/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
PROCESS FOR ETCHING A METAL LAYER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10268148
|
Filing Dt:
|
10/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2003
| | | | |
|
Title:
|
DEFECT-MINIMIZING, TOPOLOGY-INDEPENDENT PLANARIZATION OF PROCESS SURFACES IN SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10268203
|
Filing Dt:
|
10/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
TEST WAFER AND METHOD FOR PRODUCING THE TEST WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10269834
|
Filing Dt:
|
10/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10271097
|
Filing Dt:
|
10/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
DEVICE FOR FIXING A HEAT DISTRIBUTION COVERING ON A PRINTED CIRCUIT BOARD AND CIRCUIT BOARD WITH HEAT DISTRIBUTION COVERING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10271955
|
Filing Dt:
|
10/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2004
| | | | |
|
Title:
|
DELAY ADJUSTMENT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10272344
|
Filing Dt:
|
10/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD FOR TESTING SEMICONDUCTOR CIRCUIT DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10272386
|
Filing Dt:
|
10/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD OF FORMING A VERTICAL FIELD-EFFECT TRANSISTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10272848
|
Filing Dt:
|
10/17/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD FOR DETERMINING STATISTICAL FLUCTUATIONS OF VALUES OF GEOMETRICAL PROPERTIES OF STRUCTURES REQUIRED FOR THE FABRICATION OF SEMICONDUCTOR COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10273520
|
Filing Dt:
|
10/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
METHOD AND COMPUTER SYSTEM FOR STRUCTURAL ANALYSIS AND CORRECTION OF A SYSTEM OF DIFFERENTIAL EQUATIONS DESCRIBED BY A COMPUTER LANGUAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10273521
|
Filing Dt:
|
10/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
APPARATUS FOR ASSESSING A SILICON DIOXIDE CONTENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10273524
|
Filing Dt:
|
10/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10273531
|
Filing Dt:
|
10/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
CIRCUIT FOR AN ELECTRONIC SEMICONDUCTOR MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10274245
|
Filing Dt:
|
10/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
LOW-POWER INDICATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10275337
|
Filing Dt:
|
12/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2003
| | | | |
|
Title:
|
FIELD EFFECT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10275598
|
Filing Dt:
|
04/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
|
Title:
|
MEMORY ELEMENT AND METHOD FOR FABRICATING A MEMORY ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10277387
|
Filing Dt:
|
10/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
Memory cell, wafer, semiconductor component with memory cell having insulation collars and method for fabricating an insulating collar for a memory cell
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10278227
|
Filing Dt:
|
10/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
METHOD FOR TESTING A PLURALITY OF DEVICES DISPOSED ON A WAFER AND CONNECTED BY A COMMON DATA LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10278232
|
Filing Dt:
|
10/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
INFORMATION CONTAINING MEANS FOR MEMORY MODULES AND MEMORY CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10281031
|
Filing Dt:
|
10/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
DEVICE AND METHOD FOR CLOCK GENERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10281697
|
Filing Dt:
|
10/28/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
FABRICATION METHOD AND APPARATUS FOR FABRICATING A SPATIAL STRUCTURE IN A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10283483
|
Filing Dt:
|
10/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
METHOD FOR FABRICATING A TRENCH CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10283857
|
Filing Dt:
|
10/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
CHARGE TRAPPING MEMORY CELL, METHOD FOR FABRICATING IT, AND SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10283913
|
Filing Dt:
|
10/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
FLOATING GATE MEMORY CELL, METHOD FOR FABRICATING IT, AND SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10283992
|
Filing Dt:
|
10/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
DYNAMIC MEMORY DEVICE AND METHOD FOR CONTROLLING SUCH A DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10284508
|
Filing Dt:
|
10/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
ORIENTATION INDEPENDENT OXIDATION OF NITRIDED SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10284649
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
PROCESS FOR PRODUCING A SEMICONDUCTOR CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
10284773
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
CONFIGURATION FOR DATA TRANSMISSION IN A SEMICONDUCTOR MEMORY SYSTEM, AND RELEVANT DATA TRANSMISSION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10284774
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
DEVICE FOR ACCESSING REGISTERED CIRCUIT UNITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10284775
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
CONFIGURATION FOR MINIMIZING THE NEEL INTERACTION BETWEEN TWO FERROMAGNETIC LAYERS ON BOTH SIDES OF A NON-FERROMAGNETIC SEPARATING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10284778
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
| | | | |
|
Title:
|
MARK CONFIGURATION, WAFER WITH AT LEAST ONE MARK CONFIGURATION, AND A METHOD OF PRODUCING AT LEAST ONE MARK CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10284806
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR REFRESHING MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10284995
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
METHOD AND CIRCUIT FOR CONTROLLING FUSE BLOW
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10285027
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
MEMORY DEVICE WITH COLUMN SELECT BEING VARIABLY DELAYED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10285049
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
| | | | |
|
Title:
|
METHOD FOR REDUCING THE CONTACT RESISTANCE IN ORGANIC FIELD-EFFECT TRANSISTORS BY APPLYING A REACTIVE INTERMEDIATE LAYER WHICH DOPES THE ORGANIC SEMICONDUCTOR LAYER REGION-SELECTIVELY IN THE CONTACT REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10285050
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/03/2003
| | | | |
|
Title:
|
PROCESS FOR SILYLATING PHOTORESISTS IN THE UV RANGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10285051
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
METHOD FOR PROCESSING DATA REPRESENTING PARAMETERS RELATING TO A PLURALITY OF COMPONENTS OF AN ELECTRICAL CIRCUIT, COMPUTER READABLE STORAGE MEDIUM AND DATA PROCESSING SYSTEM CONTAINING COMPUTER-EXECUTABLE INSTRUCTIONS FOR PERFORMING THE METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10285052
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
PROCESS FOR STRUCTURING A PHOTORESIST BY UV AT LESS THAN 160 NM AND THEN AROMATIC AND/OR ALICYCLIC AMPLIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10285090
|
Filing Dt:
|
10/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
INTERCONNECT STRUCTURE FOR AN INTEGRATED CIRCUIT AND CORRESPONDING FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10285924
|
Filing Dt:
|
11/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING AN ELECTRONIC COMPONENT HAVING A PLURALITY OF CHIPS THAT ARE STACKED ONE ABOVE THE OTHER AND CONTACT-CONNECTED TO ONE ANOTHER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10287501
|
Filing Dt:
|
11/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
INTEGRATED MEMORY, AND A METHOD OF OPERATING AN INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10288387
|
Filing Dt:
|
11/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
LINE CONFIGURATION FOR BIT LINES FOR CONTACT-CONNECTING AT LEAST ONE MEMORY CELL, SEMICONDUCTOR COMPONENT WITH A LINE CONFIGURATION AND METHOD FOR FABRICATING A LINE CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10288911
|
Filing Dt:
|
11/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
METHOD FOR RECONFIGURING A MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10289075
|
Filing Dt:
|
11/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
USING ISOLATED P-WELL TRANSISTOR ARRANGEMENTS TO AVOID LEAKAGE CAUSED BY WORD LINE/BIT LINE SHORTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10289488
|
Filing Dt:
|
11/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
BILAYER CMP PROCESS TO IMPROVE SURFACE ROUGHNESS OF MAGNETIC STACK IN MRAM TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10289826
|
Filing Dt:
|
11/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
INTEGRATED CIRCUIT HAVING A TEST CIRCUIT AND METHOD OF DECOUPLING A TEST CIRCUIT IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10289913
|
Filing Dt:
|
11/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
METHOD FOR PRECHARGING MEMORY CELLS OF A DYNAMIC SEMICONDUCTOR MEMORY DURING POWER-UP AND SEMICONDUCTOR MEMORY
|
|
