|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10429158
|
Filing Dt:
|
05/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
STORAGE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10429577
|
Filing Dt:
|
05/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2003
| | | | |
|
Title:
|
METHOD OF INCREASING AN INTERNAL OPERATING VOLTAGE FOR AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10429578
|
Filing Dt:
|
05/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
|
Title:
|
TEST CONFIGURATION WITH AUTOMATIC TEST MACHINE AND INTEGRATED CIRCUIT AND METHOD FOR DETERMINING THE TIME BEHAVIOR OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10429579
|
Filing Dt:
|
05/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2003
| | | | |
|
Title:
|
METHOD AND AUXILIARY DEVICE FOR TESTING A RAM MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10431368
|
Filing Dt:
|
05/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR QUANTIFYING ERRORS IN AN ALTERNATING PHASE SHIFT MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10431422
|
Filing Dt:
|
05/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
MEMORY CIRCUIT, METHOD FOR MANUFACTURING AND METHOD FOR OPERATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10431425
|
Filing Dt:
|
05/06/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING A TRANSISTOR WITH A GATE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10431849
|
Filing Dt:
|
05/08/2003
|
|
Title:
|
MEMORY CELL ARRAY AND METHOD FOR MANFACTURING IT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10431900
|
Filing Dt:
|
05/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
METHOD FOR TESTING AN ELECTRONIC COMPONENT; COMPUTER PROGRAM PRODUCT, COMPUTER READABLE MEDIUM, AND COMPUTER EMBODYING THE METHOD; AND METHOD FOR DOWNLOADING THE PROGRAM EMBODYING THE METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10432767
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
SUBSTRATE WITH SEMICONDUCTOR LAYER, ELECTRONIC COMPONENT, ELECTRONIC CIRCUIT, PRINTABLE COMPOSITION AND METHOD FOR PRODUCTION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10432770
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
Compact semiconductor structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10435449
|
Filing Dt:
|
05/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
METHOD FOR EXPOSING A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10436723
|
Filing Dt:
|
05/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
|
Title:
|
MRAM CONFIGURATION HAVING SELECTION TRANSISTORS WITH A LARGE CHANNEL WIDTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10438362
|
Filing Dt:
|
05/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR GENERATING A CONTROLLABLE OUTPUT VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10438370
|
Filing Dt:
|
05/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2004
| | | | |
|
Title:
|
PHOTOLITHOGRAPHIC MASK AND METHODS FOR PRODUCING A STRUCTURE AND OF EXPOSING A WAFER IN A PROJECTION APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10439085
|
Filing Dt:
|
05/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10439193
|
Filing Dt:
|
05/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING A MASK SET FOR LITHOGRAPHY INCLUDING AT LEAST ONE MASK AND METHODS FOR IMAGING STRUCTURES OF A PREDETERMINED LAYOUT INTO A COMMON EXPOSURE PLANE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10440480
|
Filing Dt:
|
05/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
METHOD FOR CONNECTING CIRCUIT DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
10441609
|
Filing Dt:
|
05/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
TESTING MEMORY UNITS IN A DIGITAL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10442739
|
Filing Dt:
|
05/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2003
| | | | |
|
Title:
|
PHOTOLITHOGRAPHIC MASK HAVING A STRUCTURE REGION COVERED BY A THIN PROTECTIVE COATING OF ONLY A FEW ATOMIC LAYERS AND METHODS FOR THE FABRICATION OF THE MASK INCLUDING ALCVD TO FORM THE THIN PROTECTIVE COATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10444542
|
Filing Dt:
|
05/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
|
Title:
|
INTEGRATED MEMORY HAVING AN ACCELERATED WRITE CYCLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10444546
|
Filing Dt:
|
05/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
INTEGRATED MEMORY WITH A CONFIGURATION OF NON-VOLATILE MEMORY CELLS AND METHOD FOR FABRICATING AND FOR OPERATING THE INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10445550
|
Filing Dt:
|
05/27/2003
|
|
Title:
|
CIRCUIT CONFIGURATION FOR A CURRENT SWITCH OF A BIT/WORD LINE OF A MRAM DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10446396
|
Filing Dt:
|
05/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
CONNECTION OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10446601
|
Filing Dt:
|
05/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2003
| | | | |
|
Title:
|
INTEGRATED MEMORY USING PREFETCH ARCHITECTURE AND METHOD FOR OPERATING AN INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
10446995
|
Filing Dt:
|
05/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION HAVING A FLOW CONTROLLER, INTEGRATED MEMORY DEVICE, AND TEST CONFIGURATION HAVING SUCH A CIRCUIT CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10447018
|
Filing Dt:
|
05/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR PROVIDING AN ANTIFUSE FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10447065
|
Filing Dt:
|
05/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
VERTICAL 8F2 CELL DRAM WITH ACTIVE AREA SELF-ALIGNED TO BIT LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
10447358
|
Filing Dt:
|
05/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2004
| | | | |
|
Title:
|
CIRCUIT FOR NON-DESTRUCTIVE, SELF-NORMALIZING READING-OUT OF MRAM MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10447386
|
Filing Dt:
|
05/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
METHOD FOR CLASSIFYING ERRORS IN THE LAYOUT OF A SEMICONDUCTOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10452477
|
Filing Dt:
|
06/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR SETTING THE INPUT RESISTANCE AND THE INPUT CAPACITANCE OF AN INTEGRATED SEMICONDUCTOR CIRCUIT CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
10452482
|
Filing Dt:
|
06/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
MEMORY MODULE WITH TEST STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10452485
|
Filing Dt:
|
06/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2003
| | | | |
|
Title:
|
TEST DEVICE, TEST SYSTEM AND METHOD FOR TESTING A MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10453858
|
Filing Dt:
|
06/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2004
| | | | |
|
Title:
|
METHOD AND DEVICE FOR MINIMIZING MULTI-LAYER MICROSCOPIC AND MACROSCOPIC ALIGNMENT ERRORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10454518
|
Filing Dt:
|
06/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
SEMICONDUCTOR CONFIGURATION AND PROCESS FOR ETCHING A LAYER OF THE SEMICONDUCTOR CONFIGURATION USING A SILICON-CONTAINING ETCHING MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10454522
|
Filing Dt:
|
06/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
METHODS OF USING ADHESION ENHANCING LAYERS AND MICROELECTRONIC INTEGRATED MODULES INCLUDING ADHESION ENHANCING LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10455764
|
Filing Dt:
|
06/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/11/2003
| | | | |
|
Title:
|
METHOD FOR ELIMINATING PHASE CONFLICT CENTERS IN ALTERNATING PHASE MASKS, AND METHOD FOR PRODUCING ALTERNATING PHASE MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10456648
|
Filing Dt:
|
06/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
AREA-EFFICIENT STACK CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10457706
|
Filing Dt:
|
06/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR DETECTING AN AMOUNT OF DEPOLARIZATION OF A LINEARLY POLARIZED BEAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10460714
|
Filing Dt:
|
06/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2003
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH VOLTAGE DIVIDER AND BUFFERED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10460715
|
Filing Dt:
|
06/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2004
| | | | |
|
Title:
|
ZIPPER CONNECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
10460791
|
Filing Dt:
|
06/11/2003
|
|
Title:
|
MULTI-BANK CHIP COMPATIBLE WITH A CONTROLLER DESIGNED FOR A LESSER NUMBER OF BANKS AND METHOD OF OPERATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10461029
|
Filing Dt:
|
06/13/2003
|
|
Title:
|
MRAM CELL HAVING FRUSTRATED MAGNETIC RESERVOIRS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10461367
|
Filing Dt:
|
06/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
|
Title:
|
FERROELECTRIC MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10462419
|
Filing Dt:
|
06/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY WITH ADDRESS DECODING UNIT, AND ADDRESS LOADING METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10462512
|
Filing Dt:
|
06/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2003
| | | | |
|
Title:
|
METHOD FOR PATTERNING A LAYER OF SILICON, AND METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10463023
|
Filing Dt:
|
06/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
|
Title:
|
AN ACTIVE SOI STRUCTURE WITH A BODY CONTACT THROUGH AN INSULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
10463565
|
Filing Dt:
|
06/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
METHOD FOR STRUCTURING A SILICON LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10464226
|
Filing Dt:
|
06/18/2003
|
|
Title:
|
INTEGRATION SCHEME FOR AVOIDING PLASMA DAMAGE IN MRAM TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10464382
|
Filing Dt:
|
06/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT AND METHOD FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10464429
|
Filing Dt:
|
06/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2004
| | | | |
|
Title:
|
CONNECTION OF INTEGRATED CIRCUIT TO A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10464611
|
Filing Dt:
|
06/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
VOLTAGE REGULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10465103
|
Filing Dt:
|
06/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
METHOD FOR STRUCTURING A LITHOGRAPHY MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10465144
|
Filing Dt:
|
06/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
COMBINATION OF INTRINSIC AND SHAPE ANISOTROPY FOR REDUCED SWITCHING FIELD FLUCTUATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10465488
|
Filing Dt:
|
06/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
METHOD FOR FABRICATING A DEEP TRENCH CAPACITOR FOR DYNAMIC MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10472772
|
Filing Dt:
|
02/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
COATING MATERIAL FOR ELECTRONIC COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10473434
|
Filing Dt:
|
09/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
METHOD FOR ADJUSTING THE OVERLAY OF TWO MASK PLANES IN A PHOTOLITHOGRAPHIC PROCESS FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10476355
|
Filing Dt:
|
10/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/29/2004
| | | | |
|
Title:
|
METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10476579
|
Filing Dt:
|
05/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
MICROELECTRONIC STRUCTURE HAVING A HYDROGEN BARRIER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2009
|
Application #:
|
10476663
|
Filing Dt:
|
05/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
NANOTUBE ARRAY AND METHOD FOR PRODUCING A NANOTUBE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10477620
|
Filing Dt:
|
11/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/29/2004
| | | | |
|
Title:
|
PRODUCTION METHOD FOR A SEMICONDUCTOR COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
10477967
|
Filing Dt:
|
05/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
METHOD FOR PRODUCING AN ELECTRONIC COMPONENT, ESPECIALLY A MEMORY CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
10478403
|
Filing Dt:
|
11/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
TESTING A DATA STORE USING AN EXTERNAL TEST UNIT FOR GENERATING TEST SEQUENCE AND RECEIVING COMPRESSED TEST RESULTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10478441
|
Filing Dt:
|
05/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
DYNAMIC MEMORY AND METHOD FOR TESTING A DYNAMIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10479519
|
Filing Dt:
|
04/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/02/2004
| | | | |
|
Title:
|
DIGITAL MEMORY CELL DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10479521
|
Filing Dt:
|
04/19/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
DIGITAL MAGNETIC STORAGE CELL DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10479522
|
Filing Dt:
|
06/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2004
| | | | |
|
Title:
|
DRAM MEMORY CELL WITH A TRENCH CAPACITOR AND METHOD FOR PRODUCTION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
10479733
|
Filing Dt:
|
06/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/21/2004
| | | | |
|
Title:
|
METHOD FOR THE FORMATION OF CONTACT HOLES FOR A NUMBER OF CONTACT REGIONS FOR COMPONENTS INTEGRATED IN A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10479735
|
Filing Dt:
|
06/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
ELECTRONIC CHIP AND ELECTRONIC CHIP ASSEMBLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10480807
|
Filing Dt:
|
05/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
ARRANGEMENT AND METHOD FOR CONDITIONING A POLISHING PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10480999
|
Filing Dt:
|
07/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
MEMORY FOR PRODUCING A MEMORY COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10482331
|
Filing Dt:
|
10/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING IT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
10482719
|
Filing Dt:
|
06/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
MOLECULAR ELECTRONICS ARRANGEMENT AND METHOD FOR PRODUCING A MOLECULAR ELECTRONICS ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10483423
|
Filing Dt:
|
05/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
|
METHOD OF FORMING AN ISOLATION LAYER AND METHOD OF MANUFACTURING A TRENCH CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10484562
|
Filing Dt:
|
08/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
METHOD FOR FABRICATING A VERTICAL TRANSISTOR IN A TRENCH, AND VERTICAL TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
10485308
|
Filing Dt:
|
08/03/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR PRODUCT WITH A MEMORY AREA AND A LOGIC AREA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
10485984
|
Filing Dt:
|
10/07/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
TRENCH ISOLATION HAVING A SELF-ADJUSTING SURFACE SEAL AND METHOD FOR PRODUCING ONE SUCH TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10486184
|
Filing Dt:
|
10/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY ELEMENT, SEMICONDUCTOR MEMORY ELEMENT ARRANGEMENT, METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY ELEMENT AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10486758
|
Filing Dt:
|
07/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
MEMORY CELL WITH TRENCH CAPACITOR AND VERTICAL SELECT TRANSISTOR AND AN ANNULAR CONTACT-MAKING REGION FORMED BETWEEN THEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10487255
|
Filing Dt:
|
10/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
|
Title:
|
METHOD AND DEVICE FOR TESTING SEMICONDUCTOR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
10487911
|
Filing Dt:
|
08/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
PHOTOLITHOGRAPHIC MASK HAVING HALF TONE MAIN FEATURES AND PERPENDICULAR HALF TONE ASSIST FEATURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
10491143
|
Filing Dt:
|
10/19/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
BIOCOMPATIBLE MICROCHIP AND A METHOD FOR PRODUCING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10494063
|
Filing Dt:
|
01/07/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
PHOTOLITHOGRAPHIC PATTERNING PROCESS USING A CARBON HARD MASK LAYER OF DIAMOND-LIKE HARDNESS PRODUCED BY A PLASMA-ENHANCED DEPOSITION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10495301
|
Filing Dt:
|
12/15/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR HOMOGENEOUSLY MAGNETIZING AN EXCHANGE-COUPLED LAYER SYSTEM OF A DIGITAL MAGNETIC MEMORY CELL DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10495614
|
Filing Dt:
|
11/15/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
SEMICONDUCTOR ARRANGEMENT COMPRISING TRANSISTORS BASED ON ORGANIC SEMICONDUCTORS AND NON-VOLATILE READ-WRITE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10497007
|
Filing Dt:
|
12/15/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
|
Title:
|
MAGNETORESISTIVE MEMORY CELL WITH DYNAMIC REFERENCE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
10498421
|
Filing Dt:
|
01/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/08/2005
| | | | |
|
Title:
|
METHOD OF PRODUCING A LAYERED ARRANGEMENT AND LAYERED ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10501464
|
Filing Dt:
|
04/08/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
METHOD FOR MASKING A RECESS IN A STRUCTURE HAVING A HIGH ASPECT RATIO
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10501599
|
Filing Dt:
|
12/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
ELECTRONIC COMPONENT AND PANEL AND METHOD FOR PRODUCING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10505320
|
Filing Dt:
|
05/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
|
Title:
|
INTEGRATED READ-ONLY MEMORY, METHOD FOR OPERATING SAID READ-ONLY MEMORY AND CORRESPONDING PRODUCTION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
10507935
|
Filing Dt:
|
07/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
|
Title:
|
METHOD AND DEVICE FOR PACKAGING AND TRANSPORTING ELECTRONIC COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2007
|
Application #:
|
10509553
|
Filing Dt:
|
05/17/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
MRAM MEMORY CELL WITH A REFERENCE LAYER AND METHOD FOR FABRICATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
10518141
|
Filing Dt:
|
10/07/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
|
Title:
|
PACKAGE FOR SEMICONDUCTOR COMPONENTS AND METHOD FOR PRODUCING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
10519444
|
Filing Dt:
|
08/26/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
ELECTRONIC COMPONENT WITH MULTILAYERED REWIRING PLATE AND METHOD FOR PRODUCING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
10519741
|
Filing Dt:
|
11/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
|
Title:
|
METHOD FOR CONTACTING PARTS OF A COMPONENT INTEGRATED INTO A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
10520534
|
Filing Dt:
|
01/06/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
|
Title:
|
POLYMERIZABLE COMPOSITIONS; POLYMER, RESIST, AND LITHOGRAPHY METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
10522563
|
Filing Dt:
|
04/20/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
|
Title:
|
NOZZLE ASSEMBLY FOR APPLYING A LIQUID TO A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
10530964
|
Filing Dt:
|
10/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
|
Title:
|
IRRADIATION DEVICE FOR TESTING OBJECTS COATED WITH LIGHT-SENSITIVE PAINT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10533215
|
Filing Dt:
|
04/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
|
Title:
|
NON-VOLATILE MEMORY CELL, MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCTION OF A NON-VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
10533550
|
Filing Dt:
|
11/17/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
|
Title:
|
VERTICALLY INTEGRATED FIELD-EFFECT TRANSISTOR HAVING A NANOSTRUCTURE THEREIN
|
|
