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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10651281
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Filing Dt:
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08/28/2003
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Publication #:
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Pub Dt:
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03/03/2005
| | | | |
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Title:
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REFERENCE VOLTAGE DETECTOR FOR POWER-ON SEQUENCE IN A MEMORY
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10651753
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Filing Dt:
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08/29/2003
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Publication #:
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Pub Dt:
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03/03/2005
| | | | |
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Title:
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RELIABLE FERRO FUSE CELL
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Patent #:
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Issue Dt:
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12/20/2005
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Application #:
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10651803
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Filing Dt:
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08/29/2003
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Publication #:
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Pub Dt:
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05/12/2005
| | | | |
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Title:
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SEMI-CONDUCTOR COMPONENT TESTING SYSTEM WITH A REDUCED NUMBER OF TEST CHANNELS
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10652266
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Filing Dt:
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08/29/2003
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Publication #:
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Pub Dt:
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03/03/2005
| | | | |
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Title:
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CONTROLLED SUBSTRATE VOLTAGE FOR MEMORY SWITCHES
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10652291
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Filing Dt:
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08/29/2003
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
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Title:
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METHOD AND CONFIGURATION FOR COMPENSATING FOR UNEVENNESS IN THE SURFACE OF A SUBSTRATE
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Patent #:
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Issue Dt:
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05/01/2007
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Application #:
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10652520
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Filing Dt:
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08/29/2003
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Publication #:
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Pub Dt:
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05/06/2004
| | | | |
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Title:
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PROCESS AND ARRANGEMENT FOR THE SELECTIVE METALLIZATION OF 3D STRUCTURES
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10653537
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Filing Dt:
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09/02/2003
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Publication #:
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Pub Dt:
|
07/08/2004
| | | | |
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Title:
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MASK FOR PROJECTING A STRUCTURE PATTERN ONTO A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10653589
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Filing Dt:
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09/02/2003
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Publication #:
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Pub Dt:
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04/29/2004
| | | | |
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Title:
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METHOD FOR PATTERNING A MASK LAYER AND SEMICONDUCTOR PRODUCT
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10653599
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Filing Dt:
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09/02/2003
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Publication #:
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Pub Dt:
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04/29/2004
| | | | |
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Title:
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BARRRIER LAYER AND A METHOD FOR SUPPRESSING DIFFUSION PROCESSES DURING THE PRODUCTION OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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10654342
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Filing Dt:
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09/03/2003
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Publication #:
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Pub Dt:
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03/03/2005
| | | | |
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Title:
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SIMULATED MODULE LOAD
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10655199
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Filing Dt:
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09/04/2003
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Publication #:
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Pub Dt:
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03/10/2005
| | | | |
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Title:
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REDUCED CAP LAYER EROSION FOR BORDERLESS CONTACTS
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10656042
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Filing Dt:
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09/05/2003
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
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Title:
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METHOD FOR THE SOLDER-STOP STRUCTURING OF ELEVATIONS ON WAFERS
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Patent #:
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Issue Dt:
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04/08/2008
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Application #:
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10656353
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Filing Dt:
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09/05/2003
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
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Title:
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METHOD FOR DETERMINING THE END POINT FOR A CLEANING ETCHING PROCESS
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10657362
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Filing Dt:
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09/08/2003
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Publication #:
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Pub Dt:
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03/10/2005
| | | | |
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Title:
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FUSE LATCH CIRCUIT WITH NON-DISRUPTIVE RE-INTERROGATION
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10658130
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Filing Dt:
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09/08/2003
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Publication #:
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Pub Dt:
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03/10/2005
| | | | |
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Title:
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MEMORY DEVICE AND METHOD OF READING DATA FROM A MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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10658741
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Filing Dt:
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09/10/2003
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Publication #:
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Pub Dt:
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07/01/2004
| | | | |
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Title:
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SEMI-CONDUCTOR COMPONENT WITH CLOCK RELAYING DEVICE
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10659136
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Filing Dt:
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09/10/2003
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Publication #:
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Pub Dt:
|
03/10/2005
| | | | |
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Title:
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FABRICATION PROCESS FOR A MAGNETIC TUNNEL JUNCTION DEVICE
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Patent #:
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Issue Dt:
|
07/20/2004
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Application #:
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10659693
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Filing Dt:
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09/10/2003
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Publication #:
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Pub Dt:
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03/25/2004
| | | | |
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Title:
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SYNCHRONIZATION DEVICE FOR A SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10659843
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Filing Dt:
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09/11/2003
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Publication #:
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Pub Dt:
|
03/25/2004
| | | | |
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Title:
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TEST STRUCTURE FOR MEASURING A JUNCTION RESISTANCE IN A DRAM MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10660091
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Filing Dt:
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09/10/2003
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Publication #:
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Pub Dt:
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04/29/2004
| | | | |
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Title:
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FABRICATION METHOD FOR A SEMICONDUCTOR STRUCTURE HAVING A PARTLY FILLED TRENCH
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Patent #:
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Issue Dt:
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11/07/2006
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Application #:
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10661295
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Filing Dt:
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09/12/2003
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Publication #:
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Pub Dt:
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03/17/2005
| | | | |
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Title:
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AUTOMATED LAYOUT TRANSFORMATION SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10661340
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Filing Dt:
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09/12/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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CONFIGURATION AND METHOD FOR MAKING CONTACT WITH THE BACK SURFACE OF A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10662634
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Filing Dt:
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09/15/2003
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Publication #:
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Pub Dt:
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11/04/2004
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Title:
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SENSE AMPLIFIER CONFIGURATION FOR A SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10662795
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Filing Dt:
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09/15/2003
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Publication #:
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Pub Dt:
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03/25/2004
| | | | |
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Title:
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INTEGRATED CIRCUIT HAVING ELECTRICAL CONNECTING ELEMENTS
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10663151
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Filing Dt:
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09/15/2003
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Publication #:
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Pub Dt:
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03/17/2005
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Title:
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SELF-REFRESH SYSTEM AND METHOD FOR DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10663200
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Filing Dt:
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09/16/2003
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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METHOD OF FABRICATING AN ELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
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05/23/2006
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10663354
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Filing Dt:
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09/16/2003
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Publication #:
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Pub Dt:
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07/08/2004
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Title:
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ARRANGEMENT OF SEVERAL RESISTORS JOINTLY POSITIONED IN A WELL OF A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE INCLUDING AT LEAST ONE SUCH ARRANGEMENT
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Patent #:
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Issue Dt:
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10/24/2006
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10663448
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Filing Dt:
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09/16/2003
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Publication #:
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Pub Dt:
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07/01/2004
| | | | |
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Title:
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SEMICONDUCTOR DEVICE TESTING APPARATUS, SEMICONDUCTOR DEVICE TESTING SYSTEM, AND SEMICONDUCTOR DEVICE TESTING METHOD FOR MEASURING AND TRIMMING THE OUTPUT IMPEDANCE OF DRIVER DEVICES
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Issue Dt:
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03/27/2007
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10667481
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09/23/2003
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Pub Dt:
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03/24/2005
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Title:
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CIRCUIT, SYSTEM AND METHOD FOR ENCODING DATA TO BE STORED ON A NON-VOLATILE MEMORY ARRAY
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Patent #:
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Issue Dt:
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06/20/2006
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10667552
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Filing Dt:
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09/22/2003
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Pub Dt:
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06/17/2004
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Title:
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PHOTOMASK, IN PARTICULAR ALTERNATING PHASE SHIFT MASK, WITH COMPENSATION STRUCTURE
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Patent #:
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Issue Dt:
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11/08/2005
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10667730
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09/22/2003
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Pub Dt:
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06/17/2004
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Title:
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SEMICONDUCTOR ELEMENT HAVING A SEMI-MAGNETIC CONTACT
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Patent #:
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Issue Dt:
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09/19/2006
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10668375
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09/24/2003
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Pub Dt:
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07/01/2004
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Title:
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DEFECT REPAIR METHOD, IN PARTICULAR FOR REPAIRING QUARTZ DEFECTS ON ALTERNATING PHASE SHIFT MASKS
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Issue Dt:
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06/27/2006
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10668683
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09/23/2003
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Pub Dt:
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07/01/2004
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Title:
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CIRCUIT DEVICE WITH CLOCK PULSE DETECTION FACILITY
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Issue Dt:
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09/19/2006
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10668684
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09/23/2003
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Pub Dt:
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07/01/2004
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Title:
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PROCESS FOR DESIGNING AND MANUFACTURING SEMI-CONDUCTOR MEMORY COMPONENTS, IN PARTICULAR DRAM COMPONENTS
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Issue Dt:
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10/19/2004
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10669072
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09/23/2003
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Pub Dt:
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08/12/2004
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Title:
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METHOD FOR FABRICATING FERROELECTRIC MEMORY CELLS
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Issue Dt:
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10/17/2006
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Application #:
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10670662
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Filing Dt:
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09/25/2003
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Pub Dt:
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03/25/2004
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Title:
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INTEGRATED CIRCUIT HAVING AN INPUT CIRCUIT
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Patent #:
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Issue Dt:
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06/21/2005
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Application #:
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10672118
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09/26/2003
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Pub Dt:
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03/31/2005
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Title:
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RANDOM ACCESS MEMORY HAVING DRIVER FOR REDUCED LEAKAGE CURRENT
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Issue Dt:
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01/10/2006
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10672120
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09/26/2003
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Pub Dt:
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04/14/2005
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Title:
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MEMORY DEVICE HAVING MULTIPLE ARRAY STRUCTURE FOR INCREASED BANDWIDTH
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Issue Dt:
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01/10/2006
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10672145
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09/26/2003
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Pub Dt:
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11/18/2004
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Title:
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METHOD FOR CONTROLLING SEMICONDUCTOR CHIPS AND CONTROL APPARATUS
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Issue Dt:
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03/01/2005
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10672244
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09/25/2003
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Title:
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MEMORY SYSTEM WITH REDUCED REFRESH CURRENT
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Issue Dt:
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08/23/2005
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10672246
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Filing Dt:
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09/25/2003
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Pub Dt:
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03/31/2005
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Title:
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TEMPERATURE SENSOR SCHEME
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Issue Dt:
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02/21/2006
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10672306
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09/26/2003
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Pub Dt:
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03/31/2005
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Title:
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METHOD FOR PRODUCING A FERROELECTRIC CAPACITOR THAT INCLUDES ETCHING WITH HARDMASKS
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Issue Dt:
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09/12/2006
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10673262
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09/30/2003
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Pub Dt:
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03/31/2005
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Title:
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MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
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Issue Dt:
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12/28/2004
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10673705
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09/26/2003
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Pub Dt:
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08/12/2004
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Title:
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METHOD FOR FABRICATING A MOSFET HAVING A VERY SMALL CHANNEL LENGTH
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04/18/2006
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10673964
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09/29/2003
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Pub Dt:
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06/17/2004
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Title:
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PHOTOSENSITIVE COATING MATERIAL FOR A SUBSTRATE AND PROCESS FOR EXPOSING THE COATED SUBSTRATE
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Issue Dt:
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09/20/2005
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10673965
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Filing Dt:
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09/29/2003
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06/24/2004
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CALIBRATION CONFIGURATION
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Issue Dt:
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04/18/2006
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10674177
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Filing Dt:
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09/29/2003
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Pub Dt:
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03/31/2005
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RANDOM ACCESS MEMORY WITH POST-AMBLE DATA STROBE SIGNAL NOISE REJECTION
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09/20/2005
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10674304
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09/30/2003
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04/14/2005
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Title:
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BACKSIDE OF CHIP IMPLEMENTATION OF REDUNDANCY FUSES AND CONTACT PADS
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12/13/2005
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10674386
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10/01/2003
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04/07/2005
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SYSTEM AND METHOD FOR AUTOMATICALLY-DETECTING SOFT ERRORS IN LATCHES OF AN INTEGRATED CIRCUIT
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01/22/2008
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10674859
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09/30/2003
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03/31/2005
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DATA TRANSMISSION SYSTEM WITH REDUCED POWER CONSUMPTION
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Issue Dt:
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10/18/2005
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10674905
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Filing Dt:
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09/30/2003
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03/31/2005
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SELECTIVE BANK REFRESH
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Issue Dt:
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07/10/2007
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10675049
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Filing Dt:
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09/30/2003
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Pub Dt:
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04/29/2004
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Title:
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METHOD AND FURNACE FOR THE VAPOR PHASE DEPOSITION OF COMPONENTS ONTO SEMICONDUCTOR SUBSTRATES WITH A VARIABLE MAIN FLOW DIRECTION OF THE PROCESS GAS
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Issue Dt:
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10/25/2005
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10675492
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09/30/2003
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Pub Dt:
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04/29/2004
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METHOD FOR CALIBRATING SEMICONDUCTOR DEVICES USING A COMMON CALIBRATION REFERENCE AND A CALIBRATION CIRCUIT
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Issue Dt:
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02/07/2006
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Application #:
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10675549
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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ECHO CLOCK ON MEMORY SYSTEM HAVING WAIT INFORMATION
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10675634
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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METHOD FOR THE PATTERNED, SELECTIVE METALLIZATION OF A SURFACE OF A SUBSTRATE
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10675761
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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04/08/2004
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT CONFIGURATION
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10675772
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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07/01/2004
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Title:
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METHOD FOR COMMUNICATING A MEASURING POSITION OF A STRUCTURAL ELEMENT THAT IS TO BE FORMED ON A MASK
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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10676360
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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DEVICE AND A METHOD FOR FORMING A FERROELECTRIC CAPACITOR DEVICE
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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10676588
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Filing Dt:
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10/01/2003
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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TEST SYSTEM AND METHOD FOR TESTING MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10676596
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Filing Dt:
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10/01/2003
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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MEMORY CIRCUIT AND METHOD FOR READING OUT DATA
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10677099
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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03/31/2005
| | | | |
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Title:
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DEVICE AND A METHOD FOR FORMING A CAPACITOR DEVICE
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10677852
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Filing Dt:
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10/01/2003
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Publication #:
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Pub Dt:
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04/21/2005
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Title:
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SELF-ALIGNED VO-CONTACT FOR CELL SIZE REDUCTION
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10680773
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Filing Dt:
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10/07/2003
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Publication #:
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Pub Dt:
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04/08/2004
| | | | |
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Title:
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METHOD AND APPARATUS FOR OPERATING A SEMICONDUCTOR MEMORY AT DOUBLE DATA TRANSFER RATE
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10680782
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Filing Dt:
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10/07/2003
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Publication #:
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Pub Dt:
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04/08/2004
| | | | |
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Title:
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METHOD AND APPARATUS FOR INTERNALLY TRIMMING OUTPUT DRIVERS AND TERMINATIONS IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10681498
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Filing Dt:
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10/08/2003
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Publication #:
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Pub Dt:
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05/27/2004
| | | | |
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Title:
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CIRCUIT CONFIGURATION AND METHOD FOR MEASURING AT LEAST ONE OPERATING PARAMETER FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/26/2005
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Application #:
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10682649
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Filing Dt:
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10/09/2003
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Publication #:
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Pub Dt:
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04/15/2004
| | | | |
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Title:
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MEMORY MODULE WITH A HEAT DISSIPATION MEANS
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10683668
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
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04/14/2005
| | | | |
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Title:
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TRENCH ISOLATION EMPLOYING A HIGH ASPECT RATIO TRENCH
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10683768
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
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04/14/2005
| | | | |
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Title:
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METHOD AND CIRCUIT CONFIGURATION FOR DIGITIZING A SIGNAL IN AN INPUT BUFFER OF A DRAM DEVICE
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Patent #:
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Issue Dt:
|
12/06/2005
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Application #:
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10683965
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
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04/14/2005
| | | | |
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Title:
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REFERENCE CURRENT DISTRIBUTION IN MRAM DEVICES
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10685004
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Filing Dt:
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10/15/2003
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Publication #:
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Pub Dt:
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04/21/2005
| | | | |
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Title:
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MASK AND METHOD FOR USING THE MASK IN LITHOGRAPHIC PROCESSING
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Patent #:
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Issue Dt:
|
10/12/2004
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Application #:
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10685062
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Filing Dt:
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10/14/2003
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Publication #:
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Pub Dt:
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08/12/2004
| | | | |
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Title:
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HEATING SYSTEM, METHOD FOR HEATING A DEPOSITION OR OXIDATION REACTOR, AND REACTOR INCLUDING THE HEATING SYSTEM
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Patent #:
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Issue Dt:
|
05/24/2005
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Application #:
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10685064
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Filing Dt:
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10/14/2003
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Publication #:
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Pub Dt:
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05/06/2004
| | | | |
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Title:
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METHOD FOR WRITING TO THE MAGNETORESISTIVE MEMORY CELLS OF AN INTEGRATED MAGNETORESISTIVE SEMICONDUCTOR MEMORY
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|
|
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Patent #:
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|
Issue Dt:
|
03/07/2006
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Application #:
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10685065
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Filing Dt:
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10/14/2003
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Publication #:
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Pub Dt:
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04/22/2004
| | | | |
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Title:
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METHOD FOR APPLYING A SEMICONDUCTOR CHIP TO A CARRIER ELEMENT
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Patent #:
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|
Issue Dt:
|
10/19/2004
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Application #:
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10685082
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Filing Dt:
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10/14/2003
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Publication #:
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Pub Dt:
|
04/29/2004
| | | | |
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Title:
|
METHOD FOR OPERATING AN MRAM SEMICONDUCTOR MEMORY CONFIGURATION
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Patent #:
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|
Issue Dt:
|
09/18/2007
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Application #:
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10685684
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Filing Dt:
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10/15/2003
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Publication #:
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Pub Dt:
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04/21/2005
| | | | |
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Title:
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SEMICONDUCTOR DEVICE CLEANING EMPLOYING HETEROGENEOUS NUCLEATION FOR CONTROLLED CAVITATION
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Patent #:
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Issue Dt:
|
03/01/2005
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Application #:
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10686848
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Filing Dt:
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10/16/2003
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Publication #:
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Pub Dt:
|
04/29/2004
| | | | |
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Title:
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METHOD FOR ALIGNING AND EXPOSING A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
|
10/24/2006
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Application #:
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10689233
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Filing Dt:
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10/20/2003
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Publication #:
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Pub Dt:
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04/21/2005
| | | | |
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Title:
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INCLUSION OF LOW-K DIELECTRIC MATERIAL BETWEEN BIT LINES
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Patent #:
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|
Issue Dt:
|
08/01/2006
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Application #:
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10689241
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Filing Dt:
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10/20/2003
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Publication #:
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Pub Dt:
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04/21/2005
| | | | |
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Title:
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OPTICAL MEASUREMENT OF DEVICE FEATURES USING LENSLET ARRAY ILLUMINATION
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Patent #:
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|
Issue Dt:
|
03/07/2006
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Application #:
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10689419
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Filing Dt:
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10/20/2003
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Publication #:
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Pub Dt:
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04/29/2004
| | | | |
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Title:
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SEMICONDUCTOR MODULE AND METHODS FOR FUNCTIONALLY TESTING AND CONFIGURING A SEMICONDUCTOR MODULE
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Patent #:
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Issue Dt:
|
02/20/2007
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Application #:
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10689422
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Filing Dt:
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10/20/2003
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Publication #:
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Pub Dt:
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08/05/2004
| | | | |
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Title:
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METHOD FOR COMPARING THE ADDRESS OF A MEMORY ACCESS WITH AN ALREADY KNOWN ADDRESS OF A FAULTY MEMORY CELL
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Patent #:
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Issue Dt:
|
05/30/2006
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Application #:
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10690001
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Filing Dt:
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10/21/2003
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
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Title:
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MULTI-LEVEL DRIVER STAGE
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Patent #:
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Issue Dt:
|
09/27/2005
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Application #:
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10690002
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Filing Dt:
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10/21/2003
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Publication #:
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Pub Dt:
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07/29/2004
| | | | |
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Title:
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METHOD FOR PRODUCING VERTICAL PATTERNED LAYERS MADE OF SILICON DIOXIDE
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Patent #:
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Issue Dt:
|
01/06/2009
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Application #:
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10690538
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Filing Dt:
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10/23/2003
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Publication #:
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Pub Dt:
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04/28/2005
| | | | |
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Title:
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METHOD FOR FAST AND LOCAL ANNEAL OF ANTI-FERROMAGNETIC (AF) EXCHANGE-BIASED MAGNETIC STACKS
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Patent #:
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Issue Dt:
|
01/25/2005
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Application #:
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10692119
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Filing Dt:
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10/23/2003
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Title:
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METHOD AND CIRCUIT CONFIGURATION FOR MULTIPLE CHARGE RECYCLING DURING REFRESH OPERATIONS IN A DRAM DEVICE
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Patent #:
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Issue Dt:
|
11/01/2005
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Application #:
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10692150
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Filing Dt:
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10/21/2003
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Publication #:
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Pub Dt:
|
07/08/2004
| | | | |
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Title:
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METHOD FOR PRODUCTION OF A METALLIC OR METAL-CONTAINING LAYER
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10692234
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Filing Dt:
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10/23/2003
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Publication #:
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Pub Dt:
|
07/01/2004
| | | | |
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Title:
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METHOD FOR THE PLANARIZATION OF A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
|
02/22/2005
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Application #:
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10692636
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Filing Dt:
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10/24/2003
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Publication #:
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Pub Dt:
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06/10/2004
| | | | |
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Title:
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SEMICONDUCTOR MEMORY COMPONENT
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Patent #:
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Issue Dt:
|
08/22/2006
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Application #:
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10694593
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
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06/24/2004
| | | | |
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Title:
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METHOD FOR MINIMIZING THE VAPOR DEPOSITION OF TUNGSTEN OXIDE DURING THE SELECTIVE SIDE WALL OXIDATION OF TUNGSTEN-SILICON GATES
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Patent #:
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Issue Dt:
|
05/10/2005
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Application #:
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10694594
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
|
07/01/2004
| | | | |
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Title:
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METHOD FOR ADJUSTING PROCESSING PARAMETERS OF AT LEAST ONE PLATE-SHAPED OBJECT IN A PROCESSING TOOL
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Patent #:
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Issue Dt:
|
10/25/2005
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Application #:
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10695394
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
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Title:
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ACOUSTIC DETECTION OF MECHANICALLY INDUCED CIRCUIT DAMAGE
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10695624
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Filing Dt:
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10/28/2003
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Publication #:
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Pub Dt:
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07/15/2004
| | | | |
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Title:
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D-TYPE FLIPFLOP
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Patent #:
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Issue Dt:
|
11/22/2005
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Application #:
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10696159
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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06/17/2004
| | | | |
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Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
|
10/25/2005
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Application #:
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10696866
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
|
07/29/2004
| | | | |
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Title:
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PROCESS FOR THE BACK-SURFACE GRINDING OF WAFERS
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Patent #:
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Issue Dt:
|
02/21/2006
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Application #:
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10697639
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
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Title:
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METHOD OF CALCULATING A PRESSURE COMPENSATION RECIPE FOR A SEMICONDUCTOR WAFER IMPLANTER
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|
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Patent #:
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Issue Dt:
|
03/07/2006
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Application #:
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10697644
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
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Title:
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UTILIZATION OF AN ION GAUGE IN THE PROCESS CHAMBER OF A SEMICONDUCTOR ION IMPLANTER
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Patent #:
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Issue Dt:
|
05/23/2006
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Application #:
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10699135
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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07/08/2004
| | | | |
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Title:
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D-TYPE FLIP-FLOP WITH A REDUCED NUMBER OF TRANSISTORS
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|
|
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Patent #:
|
|
Issue Dt:
|
09/06/2005
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Application #:
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10699231
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Filing Dt:
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10/31/2003
|
|
Publication #:
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Pub Dt:
|
05/13/2004
| | | | |
|
Title:
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INTEGRATED DYNAMIC MEMORY AND OPERATING METHOD
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|
Patent #:
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Issue Dt:
|
07/04/2006
|
Application #:
|
10700087
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Filing Dt:
|
11/03/2003
|
|
Publication #:
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Pub Dt:
|
06/17/2004
| | | | |
|
Title:
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METHOD FOR POPULATING A SUBSTRATE WITH ELECTRONIC COMPONENTS
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Patent #:
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|
Issue Dt:
|
08/09/2005
|
Application #:
|
10700871
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Filing Dt:
|
11/04/2003
|
|
Publication #:
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Pub Dt:
|
06/17/2004
| | | | |
|
Title:
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STACK ARRANGEMENT OF A MEMORY MODULE
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|
|
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|
Patent #:
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|
Issue Dt:
|
04/03/2007
|
Application #:
|
10701742
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Filing Dt:
|
11/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
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Title:
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METHOD FOR MANUFACTURING A STACK ARRANGEMENT OF A MEMORY MODULE
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|
