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12/13/2005
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10770264
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Filing Dt:
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02/02/2004
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Publication #:
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Pub Dt:
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08/04/2005
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Title:
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METHOD OF MAKING ENCAPSULATED SPACERS IN VERTICAL PASS GATE DRAM AND DAMASCENE LOGIC GATES
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01/02/2007
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10771302
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02/05/2004
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02/02/2006
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Title:
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METHOD FOR EXPOSING A SUBSTRATE WITH A STRUCTURE PATTERN WHICH COMPENSATES FOR THE OPTICAL PROXIMITY EFFECT
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07/17/2007
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10774827
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02/09/2004
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Pub Dt:
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08/11/2005
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Title:
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LINE MASK DEFINED ACTIVE AREAS FOR 8F2 DRAM CELLS WITH FOLDED BIT LINES AND DEEP TRENCH PATTERNS
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10/10/2006
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10776178
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02/12/2004
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Pub Dt:
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09/23/2004
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Title:
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MEMORY MODULE HAVING A PLURALITY OF INTEGRATED MEMORY COMPONENTS
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Patent #:
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Issue Dt:
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01/03/2006
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10776467
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02/12/2004
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Pub Dt:
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12/30/2004
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Title:
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MEMORY MODULE HAVING A PLURALITY OF INTEGRATED MEMORY COMPONENTS
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Issue Dt:
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09/19/2006
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10777128
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02/13/2004
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01/06/2005
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Title:
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ARCHITECTURE FOR VERTICAL TRANSISTOR CELLS AND TRANSISTOR-CONTROLLED MEMORY CELLS
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11/27/2007
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10777608
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02/11/2004
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10/13/2005
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Title:
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POST METAL CHEMICAL MECHANICAL POLISHING DRY CLEANING
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12/12/2006
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10777992
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02/12/2004
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11/11/2004
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Title:
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METHOD AND CIRCUIT FOR ALLOCATING MEMORY ARRANGEMENT ADDRESSES
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10/31/2006
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10778014
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02/12/2004
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03/03/2005
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Title:
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SEMICONDUCTOR CIRCUIT ARRANGEMENT WITH TRENCH ISOLATION AND FABRICATION METHOD
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02/14/2006
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10779557
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02/06/2004
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09/23/2004
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Title:
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MEMORY CELL
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04/03/2007
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10780075
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02/17/2004
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08/19/2004
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Title:
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STREES-REDUCED LAYER SYSTEM FOR USE IN STORAGE CAPACITORS
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04/25/2006
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10780104
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02/17/2004
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11/11/2004
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Title:
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INTEGRATED TEST CIRCUIT IN AN INTEGRATED CIRCUIT
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Issue Dt:
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08/02/2005
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10780284
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02/17/2004
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Pub Dt:
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11/11/2004
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Title:
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DLL CIRCUIT FOR STABILIZATION OF THE INITIAL TRANSIENT PHASE
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09/20/2005
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10780884
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Filing Dt:
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02/19/2004
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Pub Dt:
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08/25/2005
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Title:
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METHOD OF DETERMINING THE OVERLAY ACCURACY OF MULTIPLE PATTERNS FORMED ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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12/05/2006
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10783068
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Filing Dt:
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02/20/2004
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09/30/2004
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Title:
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DEVICE AND METHOD FOR CONVERTING AN INPUT SIGNAL
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Issue Dt:
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12/13/2005
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10783377
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02/20/2004
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Pub Dt:
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11/11/2004
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Title:
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INTEGRATED MODULE HAVING A DELAY ELEMENT
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Issue Dt:
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10/14/2008
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10784134
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02/20/2004
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Pub Dt:
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11/11/2004
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Title:
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METHOD AND TEST DEVICE FOR DETERMINING A REPAIR SOLUTION FOR A MEMORY MODULE
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Patent #:
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Issue Dt:
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11/22/2005
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10785087
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Filing Dt:
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02/25/2004
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT HAVING A MULTIPLICITY OF MEMORY CELLS
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Patent #:
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Issue Dt:
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07/12/2005
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10785140
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Filing Dt:
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02/24/2004
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Pub Dt:
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11/11/2004
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Title:
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CIRCUIT MODULE HAVING INTERLEAVED GROUPS OF CIRCUIT CHIPS
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Patent #:
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Issue Dt:
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12/12/2006
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10785913
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Filing Dt:
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02/24/2004
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Pub Dt:
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08/25/2005
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Title:
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MAGNETIC TUNNEL JUNCTIONS FOR MRAM DEVICES
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Patent #:
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Issue Dt:
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12/19/2006
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10786996
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Filing Dt:
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02/25/2004
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Pub Dt:
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11/11/2004
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Title:
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METHOD OF REMOVING PECVD RESIDUES OF FLUORINATED PLASMA USING IN-SITU H2 PLASMA
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Issue Dt:
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07/11/2006
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10787118
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Filing Dt:
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02/27/2004
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Pub Dt:
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11/18/2004
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Title:
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PHASE-SHIFT MASK
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Patent #:
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Issue Dt:
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02/14/2006
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10787119
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Filing Dt:
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02/27/2004
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Pub Dt:
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10/07/2004
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT HAVING A CELL ARRAY HAVING A MULTIPLICITY OF MEMORY CELLS
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Patent #:
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Issue Dt:
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11/21/2006
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10787934
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Filing Dt:
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02/27/2004
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Pub Dt:
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11/18/2004
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Title:
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CAPACITOR ARRANGEMENT WITH CAPACITORS ARRANGED ONE IN THE OTHER
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Patent #:
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Issue Dt:
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06/12/2007
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10789994
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03/02/2004
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Pub Dt:
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10/07/2004
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Title:
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METHOD FOR FORMING AN OPENING IN A LIGHT-ABSORBING LAYER ON A MASK
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Issue Dt:
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09/09/2008
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10790907
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03/02/2004
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Pub Dt:
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09/08/2005
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INTEGRATED CIRCUIT WITH RE-ROUTE LAYER AND STACKED DIE ASSEMBLY
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07/01/2008
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10791763
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03/04/2004
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Pub Dt:
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10/14/2004
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Title:
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SET OF AT LEAST TWO MASKS FOR THE PROJECTION OF STRUCTURE PATTERNS
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Patent #:
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Issue Dt:
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01/31/2006
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10791768
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03/04/2004
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10/14/2004
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TEST APPARATUS FOR TESTING INTEGRATED MODULES AND METHOD FOR OPERATING A TEST APPARATUS
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Issue Dt:
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11/04/2008
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10792408
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03/03/2004
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Pub Dt:
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11/18/2004
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Title:
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BUFFER CHIP AND METHOD FOR CONTROLLING ONE OR MORE MEMORY ARRANGEMENTS
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08/01/2006
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10792691
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03/05/2004
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Pub Dt:
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10/07/2004
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METHOD FOR FORMING AN SOI SUBSTRATE, VERTICAL TRANSISTOR AND MEMORY CELL WITH VERTICAL TRANSISTOR
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07/01/2008
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10792693
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03/05/2004
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Pub Dt:
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10/07/2004
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Title:
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SET OF MASKS INCLUDING A FIRST MASK AND A SECOND TRIMMING MASK WITH A SEMITRANSPARENT REGION HAVING A TRANSPARENCY BETWEEN 20% AND 80% TO CONTROL DIFFRACTION EFFECTS AND OBTAIN MAXIMUM DEPTH OF FOCUS FOR THE PROJECTION OF STRUCTURE PATTERNS ONTO A SEMICONDUCTOR WAF
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05/09/2006
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10795611
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03/08/2004
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Pub Dt:
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09/08/2005
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Title:
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METHOD FOR PRODUCING SEMICONDUCTOR MEMORY DEVICES AND INTEGRATED MEMORY DEVICE
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03/01/2005
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10798245
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03/11/2004
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Pub Dt:
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12/23/2004
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Title:
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METHOD AND TEST CIRCUIT FOR TESTING A DYNAMIC MEMORY CIRCUIT
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10/09/2007
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10798332
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03/12/2004
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Pub Dt:
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09/15/2005
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METHOD AND ARRANGEMENT FOR CONTROLLING FOCUS PARAMETERS OF AN EXPOSURE TOOL
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02/20/2007
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10798334
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03/12/2004
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10/14/2004
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Title:
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INTEGRATED MEMORY HAVING REDUNDANT UNITS OF MEMORY CELLS AND METHOD FOR TESTING AN INTEGRATED MEMORY
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05/30/2006
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10798863
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03/12/2004
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Pub Dt:
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12/02/2004
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Title:
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INSULATOR STRUCTURE AND METHOD FOR PRODUCING INSULATOR STRUCTURES IN A SEMICONDUCTOR SUBSTRATE
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Issue Dt:
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07/18/2006
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10798865
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03/12/2004
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Pub Dt:
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09/15/2005
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Title:
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METHOD FOR FORMING A TOP OXIDE WITH NITRIDE LINER
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Issue Dt:
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05/02/2006
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10801781
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03/16/2004
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Pub Dt:
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10/14/2004
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Title:
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PROCESS FOR PRODUCING AN ETCHING MASK ON A MICROSTRUCTURE, IN PARTICULAR A SEMICONDUCTOR STRUCTURE WITH TRENCH CAPACITORS, AND CORRESPONDING USE OF THE ETCHING MASK
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Issue Dt:
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07/22/2008
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10802618
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03/17/2004
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Pub Dt:
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11/04/2004
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Title:
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ARRANGEMENT FOR TRANSFERRING INFORMATION/STRUCTURES TO WAFERS
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Issue Dt:
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12/27/2005
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10802728
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03/18/2004
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Pub Dt:
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10/14/2004
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Title:
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METHOD FOR MEASURING A CHARACTERISTIC DIMENSION OF AT LEAST ONE PATTERN ON A DISC -SHAPED OBJECT IN A MEASURING INSTRUMENT
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Issue Dt:
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11/01/2005
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10803395
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03/18/2004
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Pub Dt:
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09/09/2004
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Title:
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PITCHER-SHAPED ACTIVE AREA FOR FIELD EFFECT TRANSISTOR AND METHOD OF FORMING SAME
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Issue Dt:
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11/28/2006
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10804840
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Filing Dt:
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03/19/2004
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Pub Dt:
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09/22/2005
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Title:
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CLOCK STOP DETECTOR
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Issue Dt:
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01/03/2006
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10805024
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03/18/2004
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09/22/2005
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Title:
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MEMORY DEVICE WITH COMMON ROW INTERFACE
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01/30/2007
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10808190
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03/24/2004
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09/29/2005
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Title:
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TEMPERATURE SENSOR SCHEME
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Issue Dt:
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09/26/2006
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10809826
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03/26/2004
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Pub Dt:
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09/29/2005
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Title:
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CLOCK DISTORTION DETECTOR USING A SYNCHRONOUS MIRROR DELAY CIRCUIT
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11/14/2006
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10810489
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03/26/2004
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11/04/2004
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Title:
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INTEGRATED CIRCUIT WITH A TEST CIRCUIT
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Issue Dt:
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03/28/2006
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10811509
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03/29/2004
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01/06/2005
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Title:
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METHOD FOR FABRICATING A CONTACT HOLE PLANE IN A MEMORY MODULE
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07/29/2008
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10812395
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03/30/2004
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Pub Dt:
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01/27/2005
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Title:
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SEMICONDUCTOR DEVICE VOLTAGE SUPPLY FOR A SYSTEM WITH AT LEAST TWO, ESPECIALLY STACKED, SEMICONDUCTOR DEVICES
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Issue Dt:
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08/08/2006
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10812876
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03/31/2004
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02/03/2005
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Title:
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METHOD FOR FABRICATING TRANSISTORS OF DIFFERENT CONDUCTION TYPES AND HAVING DIFFERENT PACKING DENSITIES IN A SEMICONDUCTOR SUBSTRATE
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Issue Dt:
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08/19/2008
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10812991
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Filing Dt:
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03/31/2004
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Pub Dt:
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10/06/2005
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Title:
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SWITCHING DEVICE FOR CONFIGURABLE INTERCONNECT AND METHOD FOR PREPARING THE SAME
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10815223
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Filing Dt:
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03/31/2004
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Pub Dt:
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10/13/2005
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Title:
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CHARGE-TRAPPING MEMORY CELL ARRAY AND METHOD FOR PRODUCTION
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Issue Dt:
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10/11/2005
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Application #:
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10815224
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Filing Dt:
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03/31/2004
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Publication #:
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Pub Dt:
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10/06/2005
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Title:
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CIRCUIT BOARD FOR CONNECTING AN INTEGRATED CIRCUIT TO A SUPPORT AND IC BGA PACKAGE USING SAME
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Issue Dt:
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03/07/2006
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Application #:
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10815541
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Filing Dt:
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04/01/2004
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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INPUT CIRCUIT FOR RECEIVING A SIGNAL AT AN INPUT ON AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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10815840
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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11/04/2004
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Title:
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SEMICONDUCTOR MEMORY HAVING MUTUALLY CROSSING WORD AND BIT LINES AT WHICH MAGNETORESISTIVE MEMORY CELLS ARE ARRANGED
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10815856
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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11/11/2004
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Title:
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INTEGRATED MEMORY HAVING A VOLTAGE GENERATOR CIRCUIT FOR GENERATING A VOLTAGE SUPPLY FOR A READ/WRITE AMPLIFIER
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10816142
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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12/02/2004
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Title:
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SEMICONDUCTOR DEVICE IDENTIFICATION APPARATUS
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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10816184
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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METHOD AND APPARATUS FOR ORIENTING SEMICONDUCTOR WAFERS IN SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10817469
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
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Title:
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REFRESHING DYNAMIC MEMORY CELLS IN A MEMORY CIRCUIT AND A MEMORY CIRCUIT
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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10817504
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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11/25/2004
| | | | |
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Title:
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DATA MEMORY CIRCUIT
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Patent #:
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Issue Dt:
|
10/18/2005
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Application #:
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10819222
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Filing Dt:
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04/07/2004
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Publication #:
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Pub Dt:
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11/11/2004
| | | | |
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Title:
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DRIVER CIRCUIT HAVING A PLURALITY OF DRIVERS FOR DRIVING SIGNALS IN PARALLEL
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Patent #:
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Issue Dt:
|
10/17/2006
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Application #:
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10820292
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Filing Dt:
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04/08/2004
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Publication #:
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Pub Dt:
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10/13/2005
| | | | |
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Title:
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MULTICHIP PACKAGE WITH CLOCK FREQUENCY ADJUSTMENT
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Patent #:
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Issue Dt:
|
06/24/2008
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Application #:
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10822529
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Filing Dt:
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04/12/2004
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Publication #:
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Pub Dt:
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01/06/2005
| | | | |
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Title:
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METHOD AND APPARATUS FOR TESTING DRAM MEMORY CHIPS IN MULTICHIP MEMORY MODULES
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Patent #:
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Issue Dt:
|
08/15/2006
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Application #:
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10822997
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Filing Dt:
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04/13/2004
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Publication #:
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Pub Dt:
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06/23/2005
| | | | |
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Title:
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MEMORY APPARATUS HAVING A SHORT WORD LINE CYCLE TIME AND METHOD FOR OPERATING A MEMORY APPARATUS
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|
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Patent #:
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Issue Dt:
|
07/25/2006
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Application #:
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10823607
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Filing Dt:
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04/14/2004
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Publication #:
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Pub Dt:
|
11/04/2004
| | | | |
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Title:
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METHOD OF FORMING A SILICON DIOXIDE LAYER
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Patent #:
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Issue Dt:
|
09/06/2005
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Application #:
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10823608
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Filing Dt:
|
04/14/2004
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Publication #:
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Pub Dt:
|
11/04/2004
| | | | |
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Title:
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INTEGRATED DYNAMIC MEMORY HAVING A CONTROL CIRCUIT FOR CONTROLLING A REFRESH MODE FOR MEMORY CELLS
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Patent #:
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Issue Dt:
|
02/19/2008
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Application #:
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10826601
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Filing Dt:
|
04/16/2004
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Publication #:
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Pub Dt:
|
12/23/2004
| | | | |
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Title:
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METHOD FOR IMPROVING THE MECHANICAL PROPERTIES OF BOC MODULE ARRANGEMENTS
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|
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Patent #:
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|
Issue Dt:
|
10/03/2006
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Application #:
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10826603
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Filing Dt:
|
04/16/2004
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Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
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Title:
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METHOD FOR PROTECTING THE REDISTRIBUTION LAYER ON WAFERS/CHIPS
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|
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Patent #:
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|
Issue Dt:
|
06/13/2006
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Application #:
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10826840
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Filing Dt:
|
04/16/2004
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Publication #:
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Pub Dt:
|
10/20/2005
| | | | |
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Title:
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THRESHOLD VOLTAGE DETECTOR FOR PROCESS EFFECT COMPENSATION
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|
|
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Patent #:
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|
Issue Dt:
|
05/01/2007
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Application #:
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10826954
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Filing Dt:
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04/15/2004
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
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Title:
|
PROBE NEEDLE FOR TESTING SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING SAID PROBE NEEDLE
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Patent #:
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|
Issue Dt:
|
06/13/2006
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Application #:
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10828034
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Filing Dt:
|
04/20/2004
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Publication #:
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Pub Dt:
|
10/28/2004
| | | | |
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Title:
|
MEMORY MODULE HAVING SPACE-SAVING ARRANGEMENT OF MEMORY CHIPS AND MEMORY CHIP THEREFORE
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|
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Patent #:
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|
Issue Dt:
|
04/04/2006
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Application #:
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10829362
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Filing Dt:
|
04/22/2004
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Publication #:
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Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
DEVICE FOR COOLING MEMORY MODULES
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|
|
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Patent #:
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|
Issue Dt:
|
03/07/2006
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Application #:
|
10830675
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Filing Dt:
|
04/23/2004
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|
Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
FIELD-EFFECT TRANSISTOR
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/13/2009
|
Application #:
|
10831001
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Filing Dt:
|
04/23/2004
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|
Publication #:
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Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
INPUT RECEIVER CIRCUIT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/10/2006
|
Application #:
|
10831466
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Filing Dt:
|
04/23/2004
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|
Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
INTEGRATED MEMORY CIRCUIT HAVING A REDUNDANCY CIRCUIT AND A METHOD FOR REPLACING A MEMORY AREA
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/18/2006
|
Application #:
|
10831623
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Filing Dt:
|
04/23/2004
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|
Publication #:
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Pub Dt:
|
01/06/2005
| | | | |
|
Title:
|
METHOD FOR SETTING A TERMINATION VOLTAGE AND AN INPUT CIRCUIT
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|
|
|
Patent #:
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|
Issue Dt:
|
05/09/2006
|
Application #:
|
10832117
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Filing Dt:
|
04/26/2004
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|
Publication #:
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|
Pub Dt:
|
10/27/2005
| | | | |
|
Title:
|
MEMORY WITH ADJUSTABLE ACCESS TIME
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|
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Patent #:
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|
Issue Dt:
|
08/08/2006
|
Application #:
|
10833927
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Filing Dt:
|
04/28/2004
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|
Publication #:
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Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
CIRCUIT MODULE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/06/2007
|
Application #:
|
10833948
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Filing Dt:
|
04/28/2004
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Publication #:
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Pub Dt:
|
11/03/2005
| | | | |
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Title:
|
CIRCUIT BOARD
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|
|
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|
Patent #:
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|
Issue Dt:
|
12/06/2005
|
Application #:
|
10834276
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Filing Dt:
|
04/29/2004
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|
Publication #:
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Pub Dt:
|
11/03/2005
| | | | |
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Title:
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SWITCHING DEVICE FOR RECONFIGURABLE INTERCONNECT AND METHOD FOR MAKING THE SAME
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|
|
|
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Patent #:
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|
Issue Dt:
|
10/17/2006
|
Application #:
|
10834378
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Filing Dt:
|
04/29/2004
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|
Publication #:
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|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
LATCH OR PHASE DETECTOR DEVICE
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|
Patent #:
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|
Issue Dt:
|
08/16/2005
|
Application #:
|
10834382
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Filing Dt:
|
04/29/2004
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|
Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
VOLTAGE LEVEL CONVERTER DEVICE
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Patent #:
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|
Issue Dt:
|
02/07/2006
|
Application #:
|
10834383
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Filing Dt:
|
04/29/2004
|
|
Publication #:
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Pub Dt:
|
12/16/2004
| | | | |
|
Title:
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DEVICES FOR SYNCHRONIZING CLOCK SIGNALS
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Patent #:
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Issue Dt:
|
09/13/2005
|
Application #:
|
10834385
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Filing Dt:
|
04/29/2004
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|
Publication #:
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Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
DEVICE AND METHOD FOR CORRECTING THE DUTY CYCLE OF A CLOCK SIGNAL
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Patent #:
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|
Issue Dt:
|
08/08/2006
|
Application #:
|
10835217
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Filing Dt:
|
04/29/2004
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|
Publication #:
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Pub Dt:
|
11/11/2004
| | | | |
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Title:
|
METHOD FOR DETECTING AND COMPENSATING FOR POSITIONAL DISPLACEMENTS IN PHOTOLITHOGRAPHIC MASK UNITS AND APPARATUS FOR CARRYING OUT THE METHOD
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Patent #:
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|
Issue Dt:
|
12/11/2007
|
Application #:
|
10835259
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Filing Dt:
|
04/30/2004
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|
Publication #:
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Pub Dt:
|
01/06/2005
| | | | |
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Title:
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METHOD FOR DETERMINING THE DEPTH OF A BURIED STRUCTURE
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Patent #:
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Issue Dt:
|
08/08/2006
|
Application #:
|
10835390
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Filing Dt:
|
04/30/2004
|
|
Publication #:
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Pub Dt:
|
11/03/2005
| | | | |
|
Title:
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FLASH MEMORY CELL, FLASH MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
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|
Patent #:
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Issue Dt:
|
04/04/2006
|
Application #:
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10835393
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Filing Dt:
|
04/30/2004
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|
Publication #:
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Pub Dt:
|
11/03/2005
| | | | |
|
Title:
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METHOD OF OPTIMIZING THE TIMING BETWEEN SIGNALS
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|
Patent #:
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Issue Dt:
|
06/13/2006
|
Application #:
|
10835623
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Filing Dt:
|
04/30/2004
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Publication #:
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Pub Dt:
|
11/03/2005
| | | | |
|
Title:
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FIELD RAMP DOWN FOR PINNED SYNTHETIC ANTIFERROMAGNET
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Patent #:
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|
Issue Dt:
|
07/24/2007
|
Application #:
|
10836143
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Filing Dt:
|
04/30/2004
|
|
Publication #:
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Pub Dt:
|
11/04/2004
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE
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|
Patent #:
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Issue Dt:
|
11/20/2007
|
Application #:
|
10836753
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Filing Dt:
|
04/30/2004
|
|
Publication #:
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|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
PROCESS MONITORING BY COMPARING DELAYS PROPORTIONAL TO TEST VOLTAGES AND REFERENCE VOLTAGES
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Patent #:
|
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Issue Dt:
|
02/28/2006
|
Application #:
|
10836754
|
Filing Dt:
|
04/30/2004
|
|
Publication #:
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Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
DUTY CYCLE CORRECTION
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Patent #:
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|
Issue Dt:
|
07/17/2007
|
Application #:
|
10838535
|
Filing Dt:
|
05/04/2004
|
|
Publication #:
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|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
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METHOD FOR LOCALIZATION AND GENERATION OF SHORT CRITICAL SEQUENCE
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Patent #:
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|
Issue Dt:
|
05/06/2008
|
Application #:
|
10839800
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Filing Dt:
|
05/06/2004
|
|
Publication #:
|
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Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
DRAM MEMORY CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10840328
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Filing Dt:
|
05/07/2004
|
|
Publication #:
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|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
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INTEGRATED SEMICONDUCTOR STORAGE WITH AT LEAST A STORAGE CELL AND PROCEDURE
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|
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|
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Patent #:
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|
Issue Dt:
|
06/13/2006
|
Application #:
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10841162
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Filing Dt:
|
05/07/2004
|
|
Publication #:
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Pub Dt:
|
01/06/2005
| | | | |
|
Title:
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MULTIPLE CHIP SEMICONDUCTOR ARRANGEMENT HAVING ELECTRICAL COMPONENTS IN SEPARATING REGIONS
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|
|
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|
Patent #:
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|
Issue Dt:
|
02/14/2006
|
Application #:
|
10841546
|
Filing Dt:
|
05/10/2004
|
|
Publication #:
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|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
CIRCUIT ARRANGEMENT AND METHOD FOR SETTING A VOLTAGE SUPPLY FOR A READ/WRITE AMPLIFIER OF AN INTEGRATED MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10842259
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Filing Dt:
|
05/07/2004
|
|
Publication #:
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|
Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
CONNECTION BETWEEN A SEMICONDUCTOR CHIP AND AN EXTERNAL CONDUCTOR STRUCTURE AND METHOD FOR PRODUCING IT
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Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10843383
|
Filing Dt:
|
05/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
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METHOD AND ARRANGEMENT FOR TESTING OUTPUT CIRCUITS OF HIGH SPEED SEMICONDUCTOR MEMORY DEVICES
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|
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Patent #:
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Issue Dt:
|
03/18/2008
|
Application #:
|
10843669
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Filing Dt:
|
05/12/2004
|
|
Publication #:
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|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
GASSING-FREE EXPOSURE MASK
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|
Patent #:
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|
Issue Dt:
|
08/19/2008
|
Application #:
|
10846275
|
Filing Dt:
|
05/14/2004
|
|
Publication #:
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|
Pub Dt:
|
11/17/2005
| | | | |
|
Title:
|
SINGLE EXPOSURE OF MASK LEVELS HAVING A LINES AND SPACES ARRAY USING ALTERNATING PHASE-SHIFT MASK
|
|
