|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10920210
|
Filing Dt:
|
08/18/2004
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
INTEGRATED MEMORY HAVING A TEST CIRCUIT FOR FUNCTIONAL TESTING OF THE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10920559
|
Filing Dt:
|
08/18/2004
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
ADDRESS DECODING CIRCUIT AND METHOD FOR ADDRESSING A REGULAR MEMORY AREA AND A REDUNDANT MEMORY AREA IN A MEMORY CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10921766
|
Filing Dt:
|
08/19/2004
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE COMPRISING MEMORY CELLS WITH FLOATING GATE ELECTRODE AND METHOD OF PRODUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10922005
|
Filing Dt:
|
08/19/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
TEST ARRANGEMENT FOR TESTING SEMICONDUCTOR CIRCUIT CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10922434
|
Filing Dt:
|
08/20/2004
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
Title:
|
MRAM WITH MAGNETIC VIA FOR STORAGE OF INFORMATION AND FIELD SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10922624
|
Filing Dt:
|
08/20/2004
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
CIRCUIT FOR DISTRIBUTION OF AN INPUT SIGNAL TO ONE OR MORE TIME POSITIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10923651
|
Filing Dt:
|
08/20/2004
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
Title:
|
MRAM WITH VERTICAL STORAGE ELEMENT AND FIELD SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
10924207
|
Filing Dt:
|
08/24/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
DRIVER DEVICE, IN PARTICULAR FOR A SEMICONDUCTOR DEVICE, AND METHOD FOR OPERATING A DRIVER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10925882
|
Filing Dt:
|
08/23/2004
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
DATA CARRIER CARD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
10926838
|
Filing Dt:
|
08/25/2004
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
FLOATING GATE MEMORY CELL WITH A METALLIC SOURCE/DRAIN AND GATE, AND METHOD FOR MANUFACTURING SUCH A FLOATING GATE MEMORY GATE CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10927312
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
SEMICONDUCTOR MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
10927497
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
SENSE AMPLIFIER CONNECTING/DISCONNECTING CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING SUCH A CIRCUIT ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10927952
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
FBGA ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10928616
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
CIRCUIT BOARD AND METHOD FOR PRODUCING A CIRCUIT BOARD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
10928708
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
MEMORY MODULE AND METHOD FOR OPERATING A MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
10928759
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
LITHOGRAPHY MASK FOR IMAGING OF CONVEX STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
10929157
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
MULTI-LAYER ELECTRODE AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10930132
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHOD FOR TESTING THE SERVICEABILITY OF BIT LINES IN A DRAM MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10931978
|
Filing Dt:
|
09/02/2004
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10932888
|
Filing Dt:
|
09/02/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
INTEGRATED SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10933497
|
Filing Dt:
|
09/03/2004
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
TEST STRUCTURE FOR A SINGLE-SIDED BURIED STRAP DRAM MEMORY CELL ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
10933645
|
Filing Dt:
|
09/03/2004
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR CHECKING OUTPUT SIGNALS OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10934114
|
Filing Dt:
|
09/03/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
PROCESS FOR SEALING PLASMA-DAMAGED, POROUS LOW-K MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10934396
|
Filing Dt:
|
09/07/2004
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
DIFFERENTIAL AMPLIFIER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10937099
|
Filing Dt:
|
09/08/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
METHOD FOR FORMING A TRENCH IN A LAYER OR A LAYER STACK ON A SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10937155
|
Filing Dt:
|
09/07/2004
|
Publication #:
|
|
Pub Dt:
|
03/09/2006
| | | | |
Title:
|
CURRENT SENSE AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10937903
|
Filing Dt:
|
09/10/2004
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
Title:
|
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT DEVICE WITH THROUGH-PLATING ELEMENTS AND TERMINAL UNITS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
10938845
|
Filing Dt:
|
09/13/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
SEMICONDUCTOR CHIP WITH FLEXIBLE CONTACTS AT A FACE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10939255
|
Filing Dt:
|
09/10/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
TRANSISTOR, MEMORY CELL ARRAY AND METHOD OF MANUFACTURING A TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
10940382
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
SYSTEM AND METHOD FOR ENABLING A VENDOR MODE ON AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
10940490
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR CHARACTERIZING A RECESS LOCATED ON A SURFACE OF A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
10943017
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
METHOD OF ETCHING SILICON ANISOTROPICALLY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10944394
|
Filing Dt:
|
09/16/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
METHOD FOR GENERATING CHIP STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10944536
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
CIRCUIT ARRANGEMENT FOR READING OUT, EVALUATING AND READING IN AGAIN A CHARGE STATE INTO A MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10944537
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
ARRANGEMENT FOR PRODUCING AN ELECTRICAL CONNECTION BETWEEN A BGA PACKAGE AND A SIGNAL SOURCE, AND METHOD FOR PRODUCING SUCH A CONNECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10944678
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
METHOD OF FABRICATING AN INTERCONNECTION FOR CHIP SANDWICH ARRANGEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10944684
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
INTERCONNECTION ELEMENT FOR BGA HOUSINGS AND METHOD FOR PRODUCING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10945275
|
Filing Dt:
|
09/20/2004
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
METHOD OF PRODUCING AN INTEGRATED CIRCUIT ARRANGEMENT WITH FIELD-SHAPING ELECTRICAL CONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10946024
|
Filing Dt:
|
09/21/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH TEST CIRCUIT DISCONNECTED FROM POWER SUPPLY CONNECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10946660
|
Filing Dt:
|
09/22/2004
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
Title:
|
METHOD FOR TESTING CIRCUIT UNITS TO BE TESTED AND TEST APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10947449
|
Filing Dt:
|
09/23/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
CIRCUIT ARRANGEMENT FOR SETTING A VOLTAGE SUPPLY FOR A TEST MODE OF AN INTEGRATED MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10948557
|
Filing Dt:
|
09/24/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
CIRCUIT FOR SETTING ONE OF A PLURALITY OF ORGANIZATION FORMS OF AN INTEGRATED CIRCUIT AND METHOD FOR OPERATING IT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10948562
|
Filing Dt:
|
09/24/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
INTEGRATED MEMORY AND METHOD FOR FUNCTIONAL TESTING OF THE INTEGRATED MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2007
|
Application #:
|
10948570
|
Filing Dt:
|
09/24/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
METHOD FOR CARRYING OUT A DOUBLE OR MULTIPLE EXPOSURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
10948741
|
Filing Dt:
|
09/24/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
SIGNAL TEST PROCEDURE FOR TESTING SEMI-CONDUCTOR COMPONENTS AND A TEST APPARATUS FOR TESTING SEMI-CONDUCTOR COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10949793
|
Filing Dt:
|
09/24/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
APPARATUS FOR CALIBRATING THE RELATIVE PHASE OF TWO RECEPTION SIGNALS OF A MEMORY CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10949935
|
Filing Dt:
|
09/24/2004
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
APPARATUS FOR TESTING A MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10950165
|
Filing Dt:
|
09/24/2004
|
Publication #:
|
|
Pub Dt:
|
11/24/2005
| | | | |
Title:
|
METHOD FOR DETERMINING THE RELATIVE POSITIONAL ACCURACY OF TWO STRUCTURE ELEMENTS ON A WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10950185
|
Filing Dt:
|
09/24/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
SUBSTRATE FOR PRODUCING A SOLDERING CONNECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10950477
|
Filing Dt:
|
09/28/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
NONVOLATILE INTEGRATED SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10951596
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
ALIGNMENT MARK FOR COARSE ALIGNMENT AND FINE ALIGNMENT OF A SEMICONDUCTOR WAFER IN AN EXPOSURE TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10951661
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
METHOD FOR DETECTING POSITIONING ERRORS OF CIRCUIT PATTERNS DURING THE TRANSFER BY MEANS OF A MASK INTO LAYERS OF A SUBSTRATE OF A SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10951805
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
PHASE SHIFT MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10952233
|
Filing Dt:
|
09/28/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10952371
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
METHOD FOR FABRICATING MEMORY CELLS AND MEMORY CELL ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10952373
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
METHOD FOR THE CHARACTERIZATION OF A FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
|
10952383
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
METHOD FOR PRODUCING A MULTICHIP MODULE AND MULTICHIP MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
10952559
|
Filing Dt:
|
09/28/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
LITHOGRAPHIC MASK, AND METHOD FOR COVERING A MASK LAYER
|
|
|
Patent #:
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Issue Dt:
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09/09/2008
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Application #:
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10952707
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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CHARGE-TRAPPING MEMORY CELL AND CHARGE-TRAPPING MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/16/2008
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Application #:
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10952885
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/31/2005
| | | | |
Title:
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METHOD FOR REDUCING AN OVERLAY ERROR AND MEASUREMENT MARK FOR CARRYING OUT THE SAME
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Patent #:
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Issue Dt:
|
04/04/2006
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Application #:
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10953606
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
|
04/06/2006
| | | | |
Title:
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RESISTIVE MEMORY ELEMENT
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Patent #:
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Issue Dt:
|
08/22/2006
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Application #:
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10954156
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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CHARGE TRAPPING MEMORY CELL
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Patent #:
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Issue Dt:
|
05/15/2007
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Application #:
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10954157
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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METHOD FOR FABRICATING MEMORY COMPONENTS
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Patent #:
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Issue Dt:
|
09/26/2006
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Application #:
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10954596
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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INTEGRATED MEMORY CIRCUIT
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Patent #:
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Issue Dt:
|
09/26/2006
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Application #:
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10954642
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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METHOD FOR OPERATING A MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
|
02/20/2007
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Application #:
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10954869
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Filing Dt:
|
09/30/2004
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Publication #:
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Pub Dt:
|
03/30/2006
| | | | |
Title:
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MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM HAVING BIDIRECTIONAL CLOCK LINES
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Patent #:
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Issue Dt:
|
04/24/2007
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Application #:
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10954983
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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LONG RUNNING TEST METHOD FOR A CIRCUIT DESIGN ANALYSIS
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Patent #:
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Issue Dt:
|
02/06/2007
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Application #:
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10955177
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
|
03/30/2006
| | | | |
Title:
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MEMORY SYSTEM WITH TWO CLOCK LINES AND A MEMORY DEVICE
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Patent #:
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Issue Dt:
|
10/31/2006
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Application #:
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10955836
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
|
03/30/2006
| | | | |
Title:
|
CONTENT ADDRESSABLE MEMORY CELL INCLUDING RESISTIVE MEMORY ELEMENTS
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|
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Patent #:
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Issue Dt:
|
05/01/2007
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Application #:
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10955837
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Filing Dt:
|
09/30/2004
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Publication #:
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Pub Dt:
|
03/30/2006
| | | | |
Title:
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RESISTIVE MEMORY CELL RANDOM ACCESS MEMORY DEVICE AND METHOD OF FABRICATION
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|
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Patent #:
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Issue Dt:
|
11/28/2006
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Application #:
|
10957205
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Filing Dt:
|
10/01/2004
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Publication #:
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|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
METHOD FOR TESTING CIRCUIT UNITS TO BE TESTED BY MEANS OF MAJORITY DECISIONS AND TEST DEVICE FOR PERFORMING THE METHOD
|
|
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Patent #:
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|
Issue Dt:
|
06/26/2007
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Application #:
|
10957492
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Filing Dt:
|
10/01/2004
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Publication #:
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Pub Dt:
|
11/24/2005
| | | | |
Title:
|
ARRANGEMENT AND PROCESS FOR PROTECTING FUSES/ANTI-FUSES
|
|
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Patent #:
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|
Issue Dt:
|
09/19/2006
|
Application #:
|
10957803
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Filing Dt:
|
10/04/2004
|
Publication #:
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|
Pub Dt:
|
04/06/2006
| | | | |
Title:
|
FLEXIBLE BLENDER
|
|
|
Patent #:
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|
Issue Dt:
|
10/21/2008
|
Application #:
|
10958464
|
Filing Dt:
|
10/05/2004
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Publication #:
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Pub Dt:
|
04/06/2006
| | | | |
Title:
|
GATE LAYER DIODE METHOD AND APPARATUS
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|
|
Patent #:
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|
Issue Dt:
|
05/23/2006
|
Application #:
|
10960735
|
Filing Dt:
|
10/07/2004
|
Publication #:
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Pub Dt:
|
03/24/2005
| | | | |
Title:
|
MASKLESS MIDDLE-OF-LINE LINER DEPOSITION
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|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10960994
|
Filing Dt:
|
10/12/2004
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Publication #:
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Pub Dt:
|
05/26/2005
| | | | |
Title:
|
ELECTRONIC COMPONENT HAVING AT LEAST ONE SEMICONDUCTOR CHIP AND FLIP-CHIP CONTACTS, AND METHOD FOR PRODUCING THE SAME
|
|
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Patent #:
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|
Issue Dt:
|
12/25/2007
|
Application #:
|
10963434
|
Filing Dt:
|
10/12/2004
|
Publication #:
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Pub Dt:
|
06/16/2005
| | | | |
Title:
|
ELECTRONIC COMPONENT WITH FLEXIBLE CONTACTING PADS AND METHOD FOR PRODUCING THE ELECTRONIC COMPONENT
|
|
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Patent #:
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|
Issue Dt:
|
08/22/2006
|
Application #:
|
10964102
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Filing Dt:
|
10/13/2004
|
Publication #:
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|
Pub Dt:
|
04/13/2006
| | | | |
Title:
|
MEASURING FLARE IN SEMICONDUCTOR LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10966776
|
Filing Dt:
|
10/15/2004
|
Publication #:
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|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
COMBINED RECEIVER AND LATCH
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10966994
|
Filing Dt:
|
10/15/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE WITH AN ENCAPSULATION OF A FILLING WHICH IS USED FOR FILLING TRENCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10967020
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Filing Dt:
|
10/15/2004
|
Publication #:
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|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
WAFER LEVEL PACKAGES FOR CHIPS WITH SAWN EDGE PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
10967090
|
Filing Dt:
|
10/15/2004
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
DEVICE BASED ON PARTIALLY OXIDIZED POROUS SILICON AND METHOD FOR ITS PRODUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10967465
|
Filing Dt:
|
10/18/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING DEEP TRENCH STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10967768
|
Filing Dt:
|
10/18/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
DQS FOR DATA FROM A MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10967869
|
Filing Dt:
|
10/18/2004
|
Publication #:
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|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
EDGE PROTECTION PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10967899
|
Filing Dt:
|
10/18/2004
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
MEMORY DEVICE AND METHOD USING A SENSE AMPLIFIER AS A CACHE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10969343
|
Filing Dt:
|
10/21/2004
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
SIMULATING A FLOATING WORDLINE CONDITION IN A MEMORY DEVICE, AND RELATED TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10970483
|
Filing Dt:
|
10/21/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
PROCESS FOR GENERATING A HARD MASK FOR THE PATTERNING OF A LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10970664
|
Filing Dt:
|
10/22/2004
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
LEVEL CONVERTER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10971762
|
Filing Dt:
|
10/25/2004
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
CLOCK SIGNAL SYNCHRONIZING DEVICE, AND CLOCK SIGNAL SYNCHRONIZING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10972804
|
Filing Dt:
|
10/25/2004
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
ARRANGEMENT OF MICROSTRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10973389
|
Filing Dt:
|
10/27/2004
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
METHOD AND APPARATUS COMPENSATING FOR FREQUENCY DRIFT IN A DELAY LOCKED LOOP
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
10974019
|
Filing Dt:
|
10/27/2004
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY HAVING TRI-STATE DRIVER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10974521
|
Filing Dt:
|
10/27/2004
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
CIRCUIT HAVING DELAY LOCKED LOOP FOR CORRECTING OFF CHIP DRIVER DUTY DISTORTION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10974564
|
Filing Dt:
|
10/27/2004
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
VARIABLE DELAY LINE USING TWO BLENDER DELAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10974726
|
Filing Dt:
|
10/28/2004
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
Title:
|
PHOTORESIST SUITABLE FOR USE IN 157 NM PHOTOLITHOGRAPHY AND INCLUDING A POLYMER BASED ON FLUORINATED NORBORNENE DERIVATIVES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10974774
|
Filing Dt:
|
10/28/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
SILICON PARTICLES AS ADDITIVES FOR IMPROVING CHARGE CARRIER MOBILITY IN ORGANIC SEMICONDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
10974797
|
Filing Dt:
|
10/28/2004
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
TRENCH CAPACITOR STRUCTURE AND PROCESS FOR APPLYING A COVERING LAYER AND A MASK FOR TRENCH ETCHING PROCESSES IN SEMICONDUCTOR SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10974829
|
Filing Dt:
|
10/28/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
APPARATUS AND METHOD FOR PROOF OF OUTGASSING PRODUCTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10975085
|
Filing Dt:
|
10/28/2004
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
TRANSISTOR STRUCTURE, MEMORY CELL, DRAM, AND METHOD FOR FABRICATING A TRANSISTOR STRUCTURE IN A SEMICONDUCTOR SUBSTRATE
|
|