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Reel/Frame:035623/0001   Pages: 181
Recorded: 05/08/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 4024
Page 28 of 41
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
1
Patent #:
7304495
Issue Dt:
12/04/2007
Application #:
10975384
Filing Dt:
10/29/2004
Publication #:
US20050093569
Pub Dt:
05/05/2005
Title:
PSEUDODYNAMIC OFF-CHIP DRIVER CALIBRATION
2
Patent #:
7094507
Issue Dt:
08/22/2006
Application #:
10976159
Filing Dt:
10/29/2004
Publication #:
US20060095208
Pub Dt:
05/04/2006
Title:
METHOD FOR DETERMINING AN OPTIMAL ABSORBER STACK GEOMETRY OF A LITHOGRAPHIC REFLECTION MASK
3
Patent #:
7144770
Issue Dt:
12/05/2006
Application #:
10980069
Filing Dt:
11/03/2004
Publication #:
US20050158945
Pub Dt:
07/21/2005
Title:
MEMORY CELL AND METHOD FOR FABRICATING IT
4
Patent #:
7161365
Issue Dt:
01/09/2007
Application #:
10980301
Filing Dt:
11/04/2004
Publication #:
US20060103369
Pub Dt:
05/18/2006
Title:
APPARATUS AND METHOD FOR MAKING GROUND CONNECTION
5
Patent #:
7091764
Issue Dt:
08/15/2006
Application #:
10981947
Filing Dt:
11/05/2004
Publication #:
US20060097756
Pub Dt:
05/11/2006
Title:
DUTY DISTORTION DETECTOR
6
Patent #:
7304721
Issue Dt:
12/04/2007
Application #:
10984797
Filing Dt:
11/10/2004
Publication #:
US20050125164
Pub Dt:
06/09/2005
Title:
METHOD FOR DYNAMICALLY MONITORING A RETICLE
7
Patent #:
7224439
Issue Dt:
05/29/2007
Application #:
10986288
Filing Dt:
11/12/2004
Publication #:
US20050117135
Pub Dt:
06/02/2005
Title:
METHOD AND IMAGING APPARATUS FOR IMAGING A STRUCTURE ONTO A SEMICONDUCTOR WAFER BY MEANS OF IMMERSION LITHOGRAPHY
8
Patent #:
7050340
Issue Dt:
05/23/2006
Application #:
10986767
Filing Dt:
11/15/2004
Publication #:
US20060104132
Pub Dt:
05/18/2006
Title:
SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR THE TRANSFER OF WRITE AND READ DATA SIGNALS IN A SEMICONDUCTOR MEMORY SYSTEM
9
Patent #:
7266667
Issue Dt:
09/04/2007
Application #:
10987812
Filing Dt:
11/12/2004
Publication #:
US20060107026
Pub Dt:
05/18/2006
Title:
MEMORY ACCESS USING MULTIPLE SETS OF ADDRESS/DATA LINES
10
Patent #:
7308628
Issue Dt:
12/11/2007
Application #:
10988541
Filing Dt:
11/16/2004
Publication #:
US20050108603
Pub Dt:
05/19/2005
Title:
INPUT SWITCHING ARRANGEMENT FOR A SEMICONDUCTOR CIRCUIT AND TEST METHOD FOR UNIDIRECTIONAL INPUT DRIVERS IN SEMICONDUCTOR CIRCUITS
11
Patent #:
7161861
Issue Dt:
01/09/2007
Application #:
10988787
Filing Dt:
11/15/2004
Publication #:
US20060104136
Pub Dt:
05/18/2006
Title:
SENSE AMPLIFIER BITLINE BOOST CIRCUIT
12
Patent #:
7223639
Issue Dt:
05/29/2007
Application #:
10989650
Filing Dt:
11/16/2004
Publication #:
US20050067721
Pub Dt:
03/31/2005
Title:
METHOD OF PRODUCING AN ELECTRONIC COMPONENT AND A PANEL WITH A PLURALITY OF ELECTRONIC COMPONENTS
13
Patent #:
7157923
Issue Dt:
01/02/2007
Application #:
10990420
Filing Dt:
11/18/2004
Publication #:
US20060103401
Pub Dt:
05/18/2006
Title:
METHOD FOR FULL WAFER CONTACT PROBING, WAFER DESIGN AND PROBE CARD DEVICE WITH REDUCED PROBE CONTACTS
14
Patent #:
6979859
Issue Dt:
12/27/2005
Application #:
10991342
Filing Dt:
11/09/2004
Publication #:
US20050146940
Pub Dt:
07/07/2005
Title:
FLASH MEMORY CELL AND FABRICATION METHOD
15
Patent #:
7157768
Issue Dt:
01/02/2007
Application #:
10991345
Filing Dt:
11/09/2004
Publication #:
US20050139893
Pub Dt:
06/30/2005
Title:
NON-VOLATILE FLASH SEMICONDUCTOR MEMORY AND FABRICATION METHOD
16
Patent #:
7164613
Issue Dt:
01/16/2007
Application #:
10991434
Filing Dt:
11/19/2004
Publication #:
US20060109735
Pub Dt:
05/25/2006
Title:
FLEXIBLE INTERNAL ADDRESS COUNTING METHOD AND APPARATUS
17
Patent #:
7035003
Issue Dt:
04/25/2006
Application #:
10991517
Filing Dt:
11/19/2004
Publication #:
US20050122578
Pub Dt:
06/09/2005
Title:
MICROSCOPE ARRANGEMENT FOR INSPECTING A SUBSTRATE
18
Patent #:
7214552
Issue Dt:
05/08/2007
Application #:
10992982
Filing Dt:
11/19/2004
Publication #:
US20060110836
Pub Dt:
05/25/2006
Title:
ELIMINATING SYSTEMATIC PROCESS YIELD LOSS VIA PRECISION WAFER PLACEMENT ALIGNMENT
19
Patent #:
7082049
Issue Dt:
07/25/2006
Application #:
10993250
Filing Dt:
11/19/2004
Publication #:
US20060109721
Pub Dt:
05/25/2006
Title:
RANDOM ACCESS MEMORY HAVING FAST COLUMN ACCESS
20
Patent #:
7196406
Issue Dt:
03/27/2007
Application #:
10994977
Filing Dt:
11/22/2004
Publication #:
US20060108637
Pub Dt:
05/25/2006
Title:
ESD PROTECTION APPARATUS FOR AN ELECTRICAL DEVICE
21
Patent #:
7413993
Issue Dt:
08/19/2008
Application #:
10995025
Filing Dt:
11/22/2004
Publication #:
US20060108324
Pub Dt:
05/25/2006
Title:
PROCESS FOR REMOVING A RESIDUE FROM A METAL STRUCTURE ON A SEMICONDUCTOR SUBSTRATE
22
Patent #:
7180313
Issue Dt:
02/20/2007
Application #:
10995111
Filing Dt:
11/24/2004
Publication #:
US20050162176
Pub Dt:
07/28/2005
Title:
TEST DEVICE FOR WAFER TESTING DIGITAL SEMICONDUCTOR CIRCUITS
23
Patent #:
7207030
Issue Dt:
04/17/2007
Application #:
10995126
Filing Dt:
11/24/2004
Publication #:
US20050114823
Pub Dt:
05/26/2005
Title:
METHOD FOR IMPROVING A SIMULATION MODEL OF PHOTOLITHOGRAPHIC PROJECTION
24
Patent #:
7113424
Issue Dt:
09/26/2006
Application #:
10995643
Filing Dt:
11/23/2004
Publication #:
US20060109707
Pub Dt:
05/25/2006
Title:
ENERGY ADJUSTED WRITE PULSES IN PHASE-CHANGE MEMORIES
25
Patent #:
7031181
Issue Dt:
04/18/2006
Application #:
10995644
Filing Dt:
11/23/2004
Title:
MULTI-PULSE RESET WRITE SCHEME FOR PHASE-CHANGE MEMORIES
26
Patent #:
7259060
Issue Dt:
08/21/2007
Application #:
10995677
Filing Dt:
11/23/2004
Publication #:
US20050124124
Pub Dt:
06/09/2005
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
27
Patent #:
7011574
Issue Dt:
03/14/2006
Application #:
10996669
Filing Dt:
11/24/2004
Publication #:
US20050153643
Pub Dt:
07/14/2005
Title:
POLYELECTROLYTE DISPENSING POLISHING PAD
28
Patent #:
7368375
Issue Dt:
05/06/2008
Application #:
10997761
Filing Dt:
11/24/2004
Publication #:
US20050127521
Pub Dt:
06/16/2005
Title:
ELECTRONIC COMPONENT WITH COMPLIANT ELEVATIONS HAVING ELECTRICAL CONTACT AREAS AND METHOD FOR PRODUCING IT
29
Patent #:
7200033
Issue Dt:
04/03/2007
Application #:
10998808
Filing Dt:
11/30/2004
Publication #:
US20060114713
Pub Dt:
06/01/2006
Title:
MRAM WITH COIL FOR CREATING OFFSET FIELD
30
Patent #:
7355230
Issue Dt:
04/08/2008
Application #:
10998975
Filing Dt:
11/30/2004
Publication #:
US20060113587
Pub Dt:
06/01/2006
Title:
TRANSISTOR ARRAY FOR SEMICONDUCTOR MEMORY DEVICES AND METHOD FOR FABRICATING A VERTICAL CHANNEL TRANSISTOR ARRAY
31
Patent #:
7195978
Issue Dt:
03/27/2007
Application #:
10999810
Filing Dt:
11/29/2004
Publication #:
US20050157583
Pub Dt:
07/21/2005
Title:
METHOD FOR THE PRODUCTION OF A MEMORY CELL, MEMORY CELL AND MEMORY CELL ARRANGEMENT
32
Patent #:
7247956
Issue Dt:
07/24/2007
Application #:
11000252
Filing Dt:
11/30/2004
Publication #:
US20060113845
Pub Dt:
06/01/2006
Title:
PERFORMANCE TEST BOARD
33
Patent #:
7457589
Issue Dt:
11/25/2008
Application #:
11000323
Filing Dt:
11/30/2004
Publication #:
US20060116086
Pub Dt:
06/01/2006
Title:
CIRCUIT AND METHOD FOR TRANSMITTING A SIGNAL
34
Patent #:
7169716
Issue Dt:
01/30/2007
Application #:
11000342
Filing Dt:
11/29/2004
Publication #:
US20050130444
Pub Dt:
06/16/2005
Title:
PHOTOSENSITIVE LACQUER FOR PROVIDING A COATING ON A SEMICONDUCTOR SUBSTRATE OR A MASK
35
Patent #:
7298004
Issue Dt:
11/20/2007
Application #:
11000350
Filing Dt:
11/30/2004
Publication #:
US20060115978
Pub Dt:
06/01/2006
Title:
CHARGE-TRAPPING MEMORY CELL AND METHOD FOR PRODUCTION
36
Patent #:
7334150
Issue Dt:
02/19/2008
Application #:
11002148
Filing Dt:
12/03/2004
Publication #:
US20060123265
Pub Dt:
06/08/2006
Title:
MEMORY MODULE WITH A CLOCK SIGNAL REGENERATION CIRCUIT AND A REGISTER CIRCUIT FOR TEMPORARILY STORING THE INCOMING COMMAND AND ADDRESS SIGNALS
37
Patent #:
7163891
Issue Dt:
01/16/2007
Application #:
11003592
Filing Dt:
12/03/2004
Publication #:
US20050130352
Pub Dt:
06/16/2005
Title:
HIGH DENSITY DRAM WITH REDUCED PERIPHERAL DEVICE AREA AND METHOD OF MANUFACTURE
38
Patent #:
7102911
Issue Dt:
09/05/2006
Application #:
11004880
Filing Dt:
12/07/2004
Publication #:
US20050128796
Pub Dt:
06/16/2005
Title:
METHOD FOR IMPROVING THE READ SIGNAL IN A MEMORY HAVING PASSIVE MEMORY ELEMENTS
39
Patent #:
7139184
Issue Dt:
11/21/2006
Application #:
11004881
Filing Dt:
12/07/2004
Publication #:
US20060120129
Pub Dt:
06/08/2006
Title:
MEMORY CELL ARRAY
40
Patent #:
7034408
Issue Dt:
04/25/2006
Application #:
11005045
Filing Dt:
12/07/2004
Title:
MEMORY DEVICE AND METHOD OF MANUFACTURING A MEMORY DEVICE
41
Patent #:
7205195
Issue Dt:
04/17/2007
Application #:
11006049
Filing Dt:
12/07/2004
Publication #:
US20050085037
Pub Dt:
04/21/2005
Title:
METHOD FOR FABRICATING NROM MEMORY CELLS WITH TRENCH TRANSISTORS
42
Patent #:
7026220
Issue Dt:
04/11/2006
Application #:
11006484
Filing Dt:
12/07/2004
Title:
METHOD FOR PRODUCTION OF CHARGE-TRAPPING MEMORY DEVICES
43
Patent #:
7203123
Issue Dt:
04/10/2007
Application #:
11006865
Filing Dt:
12/08/2004
Publication #:
US20060120200
Pub Dt:
06/08/2006
Title:
INTEGRATED DRAM MEMORY DEVICE
44
Patent #:
7340826
Issue Dt:
03/11/2008
Application #:
11008081
Filing Dt:
12/09/2004
Publication #:
US20050150685
Pub Dt:
07/14/2005
Title:
METHOD FOR PRODUCING AN ELECTRONIC DEVICE CONNECTED TO A PRINTED CIRCUIT BOARD
45
Patent #:
7042773
Issue Dt:
05/09/2006
Application #:
11008159
Filing Dt:
12/10/2004
Publication #:
US20050135163
Pub Dt:
06/23/2005
Title:
INTEGRATED CIRCUIT FOR STORING OPERATING PARAMETERS
46
Patent #:
7005640
Issue Dt:
02/28/2006
Application #:
11008643
Filing Dt:
12/10/2004
Publication #:
US20050139768
Pub Dt:
06/30/2005
Title:
METHOD AND APPARATUS FOR THE CHARACTERIZATION OF A DEPTH STRUCTURE IN A SUBSTRATE
47
Patent #:
7392582
Issue Dt:
07/01/2008
Application #:
11008648
Filing Dt:
12/10/2004
Publication #:
US20050125994
Pub Dt:
06/16/2005
Title:
SOCKET AND/OR ADAPTER DEVICE, AND AN APPARATUS AND PROCESS FOR LOADING A SOCKET AND/OR ADAPTER DEVICE WITH A CORRESPONDING SEMI-CONDUCTOR COMPONENT
48
Patent #:
7359278
Issue Dt:
04/15/2008
Application #:
11009557
Filing Dt:
12/10/2004
Publication #:
US20050141336
Pub Dt:
06/30/2005
Title:
METHOD FOR PRODUCING AN INTEGRATED MEMORY MODULE
49
Patent #:
7035160
Issue Dt:
04/25/2006
Application #:
11009967
Filing Dt:
12/10/2004
Publication #:
US20050146977
Pub Dt:
07/07/2005
Title:
CIRCUIT
50
Patent #:
7198403
Issue Dt:
04/03/2007
Application #:
11009969
Filing Dt:
12/10/2004
Publication #:
US20050226309
Pub Dt:
10/13/2005
Title:
ARRANGEMENT FOR DETERMINING A TEMPERATURE LOADING OF AN INTEGRATED CIRCUIT AND METHOD
51
Patent #:
7266639
Issue Dt:
09/04/2007
Application #:
11010182
Filing Dt:
12/10/2004
Publication #:
US20060129755
Pub Dt:
06/15/2006
Title:
MEMORY RANK DECODER FOR A MULTI-RANK DUAL INLINE MEMORY MODULE (DIMM)
52
Patent #:
7265025
Issue Dt:
09/04/2007
Application #:
11010186
Filing Dt:
12/10/2004
Publication #:
US20050148171
Pub Dt:
07/07/2005
Title:
METHOD FOR FILLING TRENCH AND RELIEF GEOMETRIES IN SEMICONDUCTOR STRUCTURES
53
Patent #:
7118955
Issue Dt:
10/10/2006
Application #:
11010941
Filing Dt:
12/10/2004
Publication #:
US20050130370
Pub Dt:
06/16/2005
Title:
METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR SUBSTRATE COMPRISING A PLURALITY OF GATE STACKS ON A SEMICONDUCTOR SUBSTRATE, AND CORRESPONDING SEMICONDUCTOR STRUCTURE
54
Patent #:
7200021
Issue Dt:
04/03/2007
Application #:
11010942
Filing Dt:
12/10/2004
Publication #:
US20060126369
Pub Dt:
06/15/2006
Title:
STACKED DRAM MEMORY CHIP FOR A DUAL INLINE MEMORY MODULE (DIMM)
55
Patent #:
7208095
Issue Dt:
04/24/2007
Application #:
11011038
Filing Dt:
12/15/2004
Publication #:
US20060124582
Pub Dt:
06/15/2006
Title:
METHOD FOR FABRICATING BOTTOM ELECTRODES OF STACKED CAPACITOR MEMORY CELLS AND METHOD FOR CLEANING AND DRYING A SEMICONDUCTOR WAFER
56
Patent #:
7018893
Issue Dt:
03/28/2006
Application #:
11011039
Filing Dt:
12/15/2004
Title:
METHOD FOR FABRICATING BOTTOM ELECTRODES OF STACKED CAPACITOR MEMORY CELLS
57
Patent #:
7476920
Issue Dt:
01/13/2009
Application #:
11011040
Filing Dt:
12/15/2004
Publication #:
US20060281250
Pub Dt:
12/14/2006
Title:
6F2 ACCESS TRANSISTOR ARRANGEMENT AND SEMICONDUCTOR MEMORY DEVICE
58
Patent #:
7453259
Issue Dt:
11/18/2008
Application #:
11012715
Filing Dt:
12/16/2004
Publication #:
US20050170689
Pub Dt:
08/04/2005
Title:
LOADING A SOCKET AND/OR ADAPTER DEVICE WITH A SEMICONDUCTOR COMPONENT
59
Patent #:
7265585
Issue Dt:
09/04/2007
Application #:
11012777
Filing Dt:
12/14/2004
Publication #:
US20060125520
Pub Dt:
06/15/2006
Title:
METHOD TO IMPROVE CURRENT AND SLEW RATE RATIO OF OFF-CHIP DRIVERS
60
Patent #:
6961273
Issue Dt:
11/01/2005
Application #:
11012927
Filing Dt:
12/14/2004
Publication #:
US20050152194
Pub Dt:
07/14/2005
Title:
RAM MEMORY CIRCUIT HAVING A PLURALITY OF BANKS AND AN AUXILIARY DEVICE FOR TESTING
61
Patent #:
7170813
Issue Dt:
01/30/2007
Application #:
11013582
Filing Dt:
12/16/2004
Publication #:
US20060133130
Pub Dt:
06/22/2006
Title:
MEMORY CIRCUIT RECEIVERS ACTIVATED BY ENABLE CIRCUIT
62
Patent #:
7263638
Issue Dt:
08/28/2007
Application #:
11013870
Filing Dt:
12/16/2004
Publication #:
US20060136792
Pub Dt:
06/22/2006
Title:
MEMORY HAVING TEST CIRCUIT
63
Patent #:
7193426
Issue Dt:
03/20/2007
Application #:
11013873
Filing Dt:
12/16/2004
Publication #:
US20050156612
Pub Dt:
07/21/2005
Title:
TEST SYSTEM AND TEST STRUCTURE FOR TESTING AN INTEGRATED CIRCUIT AND AN INTEGRATED CIRCUIT HAVING A TEST STRUCTURE
64
Patent #:
6963514
Issue Dt:
11/08/2005
Application #:
11017857
Filing Dt:
12/22/2004
Publication #:
US20050162949
Pub Dt:
07/28/2005
Title:
METHOD FOR TESTING AN INTEGRATED SEMICONDUCTOR MEMORY, AND INTEGRATED SEMICONDUCTOR MEMORY
65
Patent #:
7272070
Issue Dt:
09/18/2007
Application #:
11018313
Filing Dt:
12/21/2004
Publication #:
US20060133186
Pub Dt:
06/22/2006
Title:
MEMORY ACCESS USING MULTIPLE ACTIVATED MEMORY CELL ROWS
66
Patent #:
7151275
Issue Dt:
12/19/2006
Application #:
11020191
Filing Dt:
12/27/2004
Publication #:
US20050133782
Pub Dt:
06/23/2005
Title:
REDUCING THE CONTACT RESISTANCE IN ORGANIC FIELD-EFFECT TRANSISTORS WITH PALLADIUM CONTACTS BY USING NITRILES AND ISONITRILES
67
Patent #:
7148729
Issue Dt:
12/12/2006
Application #:
11021370
Filing Dt:
12/23/2004
Publication #:
US20060139075
Pub Dt:
06/29/2006
Title:
DELAY LOCKED LOOP USING SYNCHRONOUS MIRROR DELAY
68
Patent #:
7123542
Issue Dt:
10/17/2006
Application #:
11022202
Filing Dt:
12/22/2004
Publication #:
US20060133187
Pub Dt:
06/22/2006
Title:
MEMORY HAVING INTERNAL COLUMN COUNTER FOR COMPRESSION TEST MODE
69
Patent #:
7094648
Issue Dt:
08/22/2006
Application #:
11023041
Filing Dt:
12/27/2004
Publication #:
US20050164456
Pub Dt:
07/28/2005
Title:
METHOD FOR FABRICATING AN NROM MEMORY CELL ARRAY
70
Patent #:
7455795
Issue Dt:
11/25/2008
Application #:
11023368
Filing Dt:
12/29/2004
Publication #:
US20050198462
Pub Dt:
09/08/2005
Title:
CHARGE TRANSFER COMPLEXES INCLUDING AN ELECTRON DONOR AND AN ELECTRON ACCEPTOR AS BASIS OF RESISTIVE MEMORIES
71
Patent #:
7265381
Issue Dt:
09/04/2007
Application #:
11024932
Filing Dt:
12/30/2004
Publication #:
US20060145181
Pub Dt:
07/06/2006
Title:
OPTO-ELECTRONIC MEMORY ELEMENT ON THE BASIS OF ORGANIC METALLOPORPHYRIN MOLECULES
72
Patent #:
7279742
Issue Dt:
10/09/2007
Application #:
11024935
Filing Dt:
12/30/2004
Publication #:
US20050151206
Pub Dt:
07/14/2005
Title:
TRANSISTOR STRUCTURE WITH A CURVED CHANNEL, MEMORY CELL AND MEMORY CELL ARRAY FOR DRAMS, AND METHODS FOR FABRICATING A DRAM
73
Patent #:
7061797
Issue Dt:
06/13/2006
Application #:
11024945
Filing Dt:
12/30/2004
Publication #:
US20060146601
Pub Dt:
07/06/2006
Title:
HYBRID MEMORY CELL FOR SPIN-POLARIZED ELECTRON CURRENT INDUCED SWITCHING AND WRITING/READING PROCESS USING SUCH MEMORY CELL
74
Patent #:
7254089
Issue Dt:
08/07/2007
Application #:
11025561
Filing Dt:
12/29/2004
Publication #:
US20060140040
Pub Dt:
06/29/2006
Title:
MEMORY WITH SELECTABLE SINGLE CELL OR TWIN CELL CONFIGURATION
75
Patent #:
6993455
Issue Dt:
01/31/2006
Application #:
11029573
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Publication #:
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Pub Dt:
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Title:
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Title:
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Title:
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Pub Dt:
06/09/2005
Title:
Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations
Assignor
1
QIMONDA AG
Exec Dt:
10/09/2014
Assignee
1
INFINEON TECHNOLOGIES AG
AM CAMPEON 1-12
NEUBIBERG, GERMANY 85579
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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