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Patent Assignment Details
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Reel/Frame:035623/0001   Pages: 181
Recorded: 05/08/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 4024
Page 31 of 41
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
1
Patent #:
Issue Dt:
07/31/2007
Application #:
11154943
Filing Dt:
06/17/2005
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD FOR FABRICATING A SHADOW MASK IN A TRENCH OF A MICROELECTRONIC OR MICROMECHANICAL STRUCTURE
2
Patent #:
Issue Dt:
11/20/2007
Application #:
11155277
Filing Dt:
06/17/2005
Publication #:
Pub Dt:
12/21/2006
Title:
MULTI-CHIP DEVICE AND METHOD FOR PRODUCING A MULTI-CHIP DEVICE
3
Patent #:
Issue Dt:
08/14/2007
Application #:
11155317
Filing Dt:
06/17/2005
Publication #:
Pub Dt:
03/09/2006
Title:
SUBSTRATE-BASED HOUSING COMPONENT WITH A SEMICONDUCTOR CHIP
4
Patent #:
Issue Dt:
01/22/2008
Application #:
11157143
Filing Dt:
06/20/2005
Publication #:
Pub Dt:
12/21/2006
Title:
METHOD OF FORMING A CONTACT IN A FLASH MEMORY DEVICE
5
Patent #:
Issue Dt:
10/02/2007
Application #:
11157425
Filing Dt:
06/21/2005
Publication #:
Pub Dt:
12/21/2006
Title:
OUTPUT CIRCUIT THAT TURNS OFF ONE OF A FIRST CIRCUIT AND A SECOND CIRCUIT
6
Patent #:
Issue Dt:
07/17/2007
Application #:
11157868
Filing Dt:
06/22/2005
Publication #:
Pub Dt:
12/28/2006
Title:
PARALLEL DATA PATH ARCHITECTURE
7
Patent #:
Issue Dt:
09/15/2009
Application #:
11158271
Filing Dt:
06/21/2005
Publication #:
Pub Dt:
12/29/2005
Title:
REFLECTION MASK, USE OF THE REFLECTION MASK AND METHOD FOR FABRICATING THE REFLECTION MASK
8
Patent #:
Issue Dt:
02/12/2008
Application #:
11158439
Filing Dt:
06/22/2005
Publication #:
Pub Dt:
11/17/2005
Title:
DRAM CELL ARRANGEMENT WITH VERTICAL MOS TRANSISTORS
9
Patent #:
Issue Dt:
02/10/2009
Application #:
11159026
Filing Dt:
06/22/2005
Publication #:
Pub Dt:
01/05/2006
Title:
SEMICONDUCTOR MEMORY DEVICE
10
Patent #:
Issue Dt:
01/15/2008
Application #:
11159404
Filing Dt:
06/23/2005
Publication #:
Pub Dt:
12/29/2005
Title:
RESISTIVE SEMICONDUCTOR ELEMENT BASED ON A SOLID-STATE ION CONDUCTOR
11
Patent #:
Issue Dt:
02/05/2008
Application #:
11165566
Filing Dt:
06/24/2005
Publication #:
Pub Dt:
01/12/2006
Title:
METHOD FOR DETERMINING A MATRIX OF TRANSMISSION CROSS COEFFICIENTS IN AN OPTICAL PROXIMITY CORRECTION OF MASK LAYOUTS
12
Patent #:
Issue Dt:
10/16/2007
Application #:
11166788
Filing Dt:
06/24/2005
Publication #:
Pub Dt:
12/28/2006
Title:
MEMORY DEVICE AND METHOD FOR OPERATING THE MEMORY DEVICE
13
Patent #:
Issue Dt:
09/04/2007
Application #:
11167510
Filing Dt:
06/27/2005
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD FOR FABRICATING FIELD-EFFECT TRANSISTOR STRUCTURES WITH GATE ELECTRODES WITH A METAL LAYER
14
Patent #:
Issue Dt:
05/20/2008
Application #:
11167930
Filing Dt:
06/28/2005
Publication #:
Pub Dt:
01/05/2006
Title:
DEVICE AND A PROCESS FOR THE CALIBRATION OF A SEMICONDUCTOR COMPONENT TEST SYSTEM
15
Patent #:
Issue Dt:
06/12/2007
Application #:
11168818
Filing Dt:
06/28/2005
Publication #:
Pub Dt:
01/11/2007
Title:
DUAL FREQUENCY FIRST-IN-FIRST-OUT STRUCTURE
16
Patent #:
Issue Dt:
07/22/2008
Application #:
11168820
Filing Dt:
06/28/2005
Publication #:
Pub Dt:
12/28/2006
Title:
MULTI-CHIP DEVICE AND METHOD FOR PRODUCING A MULTI-CHIP DEVICE
17
Patent #:
Issue Dt:
12/25/2007
Application #:
11169812
Filing Dt:
06/29/2005
Publication #:
Pub Dt:
01/12/2006
Title:
METHOD FOR FABRICATING A DRAM MEMORY CELL ARRANGEMENT HAVING FIN FIELD EFFECT TRANSISTORS AND DRAM MEMORY CELL
18
Patent #:
Issue Dt:
09/23/2008
Application #:
11170187
Filing Dt:
06/29/2005
Publication #:
Pub Dt:
01/04/2007
Title:
METHOD FOR PRODUCING CHARGE-TRAPPING MEMORY CELL ARRAYS
19
Patent #:
Issue Dt:
01/27/2009
Application #:
11170189
Filing Dt:
06/29/2005
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD FOR ADAPTING STRUCTURE DIMENSIONS DURING THE PHOTOLITHOGRAPHIC PROJECTION OF A PATTERN OF STRUCTURE ELEMENTS ONTO A SEMICONDUCTOR WAFER
20
Patent #:
Issue Dt:
10/09/2007
Application #:
11170190
Filing Dt:
06/29/2005
Publication #:
Pub Dt:
01/04/2007
Title:
HANDLING UNIT FOR ELECTRONIC DEVICES
21
Patent #:
Issue Dt:
11/06/2007
Application #:
11170200
Filing Dt:
06/29/2005
Publication #:
Pub Dt:
01/04/2007
Title:
FLUIDS FOR IMMERSION LITHOGRAPHY SYSTEMS
22
Patent #:
Issue Dt:
01/29/2008
Application #:
11170887
Filing Dt:
06/30/2005
Publication #:
Pub Dt:
01/04/2007
Title:
SYNCHRONOUS SIGNAL GENERATOR
23
Patent #:
Issue Dt:
04/29/2008
Application #:
11172083
Filing Dt:
06/30/2005
Publication #:
Pub Dt:
02/09/2006
Title:
SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR COMPONENTS CONNECTED TO ONE ANOTHER
24
Patent #:
Issue Dt:
04/21/2009
Application #:
11172366
Filing Dt:
06/30/2005
Publication #:
Pub Dt:
01/04/2007
Title:
METHOD FOR FORMING A SEMICONDUCTOR PRODUCT AND SEMICONDUCTOR PRODUCT
25
Patent #:
Issue Dt:
04/10/2007
Application #:
11172367
Filing Dt:
06/30/2005
Publication #:
Pub Dt:
01/04/2007
Title:
METHOD AND APPARATUS FOR SENSING A STATE OF A MEMORY CELL
26
Patent #:
Issue Dt:
02/27/2007
Application #:
11172421
Filing Dt:
06/30/2005
Publication #:
Pub Dt:
01/04/2007
Title:
METHOD FOR PROGRAMMING MULTI-BIT CHARGE-TRAPPING MEMORY CELL ARRAYS
27
Patent #:
Issue Dt:
04/17/2007
Application #:
11173171
Filing Dt:
07/01/2005
Publication #:
Pub Dt:
01/05/2006
Title:
PROCESS FOR PRODUCING A MASK ON A SUBSTRATE
28
Patent #:
Issue Dt:
11/20/2007
Application #:
11175280
Filing Dt:
07/07/2005
Publication #:
Pub Dt:
01/11/2007
Title:
METHOD AND APPARATUS FOR SELECTIVELY ACCESSING AND CONFIGURING INDIVIDUAL CHIPS OF A SEMI-CONDUCTOR WAFER
29
Patent #:
Issue Dt:
08/21/2007
Application #:
11175386
Filing Dt:
07/07/2005
Publication #:
Pub Dt:
01/11/2007
Title:
METHOD OF TREATING A SUBSTRATE IN MANUFACTURING A MAGNETORESISTIVE MEMORY CELL
30
Patent #:
Issue Dt:
11/06/2007
Application #:
11175724
Filing Dt:
07/06/2005
Publication #:
Pub Dt:
01/11/2007
Title:
TEMPERATURE DEPENDENT SELF-REFRESH MODULE FOR A MEMORY DEVICE
31
Patent #:
Issue Dt:
07/15/2008
Application #:
11177245
Filing Dt:
07/08/2005
Publication #:
Pub Dt:
01/11/2007
Title:
METHOD OF FORMING A CHARGE-TRAPPING MEMORY DEVICE
32
Patent #:
Issue Dt:
12/25/2007
Application #:
11178251
Filing Dt:
07/08/2005
Publication #:
Pub Dt:
02/09/2006
Title:
PROCESS FOR PRODUCING A LAYER ARRANGEMENT, AND LAYER ARRANGEMENT FOR USE AS A DUAL-GATE FIELD-EFFECT TRANSISTOR
33
Patent #:
Issue Dt:
06/16/2009
Application #:
11178915
Filing Dt:
07/11/2005
Publication #:
Pub Dt:
01/26/2006
Title:
DIGITAL RAM MEMORY CIRCUIT WITH AN EXPANDED COMMAND STRUCTURE
34
Patent #:
Issue Dt:
07/10/2007
Application #:
11179345
Filing Dt:
07/12/2005
Publication #:
Pub Dt:
01/18/2007
Title:
NON-VOLATILE MEMORY CELL DEVICE, PROGRAMMING ELEMENT AND METHOD FOR PROGRAMMING DATA INTO A PLURALITY OF NON-VOLATILE MEMORY CELLS
35
Patent #:
Issue Dt:
04/08/2008
Application #:
11179358
Filing Dt:
07/12/2005
Publication #:
Pub Dt:
01/18/2007
Title:
COLUMN REDUNDANCY REUSE IN MEMORY DEVICES
36
Patent #:
Issue Dt:
01/23/2007
Application #:
11181387
Filing Dt:
07/13/2005
Publication #:
Pub Dt:
01/18/2007
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY
37
Patent #:
Issue Dt:
09/02/2008
Application #:
11182022
Filing Dt:
07/14/2005
Publication #:
Pub Dt:
01/18/2007
Title:
RESISTIVITY CHANGING MEMORY CELL HAVING NANOWIRE ELECTRODE
38
Patent #:
Issue Dt:
07/22/2008
Application #:
11182063
Filing Dt:
07/15/2005
Publication #:
Pub Dt:
02/08/2007
Title:
SEMICONDUCTOR MEMORY DEVICE INCLUDING A SIGNAL CONTROL DEVICE AND METHOD OF OPERATING THE SAME
39
Patent #:
Issue Dt:
05/06/2008
Application #:
11182064
Filing Dt:
07/15/2005
Publication #:
Pub Dt:
01/18/2007
Title:
INTEGRATED RECEIVER CIRCUIT
40
Patent #:
Issue Dt:
05/06/2008
Application #:
11182066
Filing Dt:
07/15/2005
Publication #:
Pub Dt:
02/02/2006
Title:
METHOD OF PRODUCING A STRUCTURE ON THE SURFACE OF A SUBSTRATE
41
Patent #:
Issue Dt:
04/10/2007
Application #:
11183224
Filing Dt:
07/14/2005
Publication #:
Pub Dt:
01/18/2007
Title:
MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR STRUCTURE AND CORRESPONDING INTEGRATED SEMICONDUCTOR STRUCTURE
42
Patent #:
Issue Dt:
11/06/2007
Application #:
11184074
Filing Dt:
07/19/2005
Publication #:
Pub Dt:
01/25/2007
Title:
LOW RESISTANCE CONTACT IN A SEMICONDUCTOR DEVICE
43
Patent #:
Issue Dt:
05/06/2008
Application #:
11184532
Filing Dt:
07/19/2005
Publication #:
Pub Dt:
01/26/2006
Title:
METHOD FOR MOUNTING A CHIP ON A BASE AND ARRANGEMENT PRODUCED BY THIS METHOD
44
Patent #:
Issue Dt:
04/14/2009
Application #:
11185472
Filing Dt:
07/20/2005
Publication #:
Pub Dt:
07/27/2006
Title:
METHOD FOR CONNECTION OF AN INTEGRATED CIRCUIT TO A SUBSTRATE, AND A CORRESPONDING CIRCUIT ARRANGEMENT
45
Patent #:
Issue Dt:
10/23/2007
Application #:
11187321
Filing Dt:
07/22/2005
Publication #:
Pub Dt:
01/25/2007
Title:
TEMPERATURE UPDATE MASKING TO ENSURE CORRECT MEASUREMENT OF TEMPERATURE WHEN REFERENCES BECOME UNSTABLE
46
Patent #:
Issue Dt:
06/24/2008
Application #:
11187533
Filing Dt:
07/22/2005
Publication #:
Pub Dt:
01/26/2006
Title:
PHASE CHANGE MEMORY DEVICE WITH THERMAL INSULATING LAYERS
47
Patent #:
Issue Dt:
04/17/2007
Application #:
11187546
Filing Dt:
07/22/2005
Publication #:
Pub Dt:
01/25/2007
Title:
CLOCKED STANDBY MODE WITH MAXIMUM CLOCK FREQUENCY
48
Patent #:
Issue Dt:
02/13/2007
Application #:
11187643
Filing Dt:
07/22/2005
Publication #:
Pub Dt:
01/25/2007
Title:
DISABLING CLOCKED STANDBY MODE BASED ON DEVICE TEMPERATURE
49
Patent #:
Issue Dt:
04/01/2008
Application #:
11187693
Filing Dt:
07/22/2005
Publication #:
Pub Dt:
01/25/2007
Title:
NON-VOLATILE MEMORY CELLS AND METHODS FOR FABRICATING NON-VOLATILE MEMORY CELLS
50
Patent #:
Issue Dt:
04/10/2007
Application #:
11189018
Filing Dt:
07/26/2005
Publication #:
Pub Dt:
02/02/2006
Title:
INTEGRATED SEMICONDUCTOR MEMORY WITH REDUNDANT MEMORY CELLS
51
Patent #:
Issue Dt:
02/12/2008
Application #:
11189231
Filing Dt:
07/26/2005
Publication #:
Pub Dt:
02/02/2006
Title:
SEMICONDUCTOR CIRCUIT DEVICE AND A SYSTEM FOR TESTING A SEMICONDUCTOR APPARATUS
52
Patent #:
Issue Dt:
07/31/2007
Application #:
11190056
Filing Dt:
07/27/2005
Publication #:
Pub Dt:
02/02/2006
Title:
METHOD FOR CORRECTING STRUCTURE-SIZE-DEPENDENT POSITIONING ERRORS IN PHOTOLITHOGRAPHY
53
Patent #:
Issue Dt:
07/17/2007
Application #:
11190068
Filing Dt:
07/26/2005
Publication #:
Pub Dt:
02/01/2007
Title:
SUBSTRATE BASED IC-PACKAGE
54
Patent #:
Issue Dt:
02/26/2008
Application #:
11191141
Filing Dt:
07/28/2005
Publication #:
Pub Dt:
02/02/2006
Title:
INTEGRATED SEMICONDUCTOR MEMORY
55
Patent #:
Issue Dt:
12/18/2007
Application #:
11191167
Filing Dt:
07/27/2005
Publication #:
Pub Dt:
03/09/2006
Title:
METHOD FOR CORRECTING LAYOUT ERRORS
56
Patent #:
Issue Dt:
11/20/2007
Application #:
11191837
Filing Dt:
07/28/2005
Publication #:
Pub Dt:
03/01/2007
Title:
NON-VOLATILE, RESISTIVE MEMORY CELL BASED ON METAL OXIDE NANOPARTICLES, PROCESS FOR MANUFACTURING THE SAME AND MEMORY CELL ARRANGEMENT OF THE SAME
57
Patent #:
Issue Dt:
08/19/2008
Application #:
11192335
Filing Dt:
07/29/2005
Publication #:
Pub Dt:
02/01/2007
Title:
RE-DRIVING CAWD AND RD SIGNAL LINES
58
Patent #:
Issue Dt:
03/25/2008
Application #:
11192981
Filing Dt:
07/29/2005
Publication #:
Pub Dt:
02/01/2007
Title:
SEMICONDUCTOR PACKAGE BASED ON LEAD-ON-CHIP ARCHITECTURE, THE FABRICATION THEREOF AND A LEADFRAME FOR IMPLEMENTING IN A SEMICONDUCTOR PACKAGE
59
Patent #:
Issue Dt:
05/20/2008
Application #:
11193024
Filing Dt:
07/29/2005
Publication #:
Pub Dt:
03/16/2006
Title:
METHOD FOR PRODUCTION OF A STANDARD CELL ARRANGEMENT, AND APPARATUS FOR CARRYING OUT THE METHOD
60
Patent #:
Issue Dt:
05/05/2009
Application #:
11193026
Filing Dt:
07/29/2005
Publication #:
Pub Dt:
02/01/2007
Title:
SEMICONDUCTOR MEMORY WITH CHARGE-TRAPPING STACK ARRANGEMENT
61
Patent #:
Issue Dt:
01/31/2012
Application #:
11193184
Filing Dt:
07/29/2005
Publication #:
Pub Dt:
02/01/2007
Title:
SEMICONDUCTOR MEMORY CHIP AND MEMORY SYSTEM
62
Patent #:
Issue Dt:
03/18/2008
Application #:
11194302
Filing Dt:
08/01/2005
Publication #:
Pub Dt:
02/01/2007
Title:
MAINTAINING INTERNAL VOLTAGES OF AN INTEGRATED CIRCUIT IN RESPONSE TO A CLOCKED STANDBY MODE
63
Patent #:
Issue Dt:
11/06/2007
Application #:
11194489
Filing Dt:
08/01/2005
Publication #:
Pub Dt:
02/01/2007
Title:
METHOD OF PRODUCING PITCH FRACTIONIZATIONS IN SEMICONDUCTOR TECHNOLOGY
64
Patent #:
Issue Dt:
09/02/2008
Application #:
11194494
Filing Dt:
08/01/2005
Publication #:
Pub Dt:
02/09/2006
Title:
METHOD AND ARRANGEMENT FOR GENERATING AN OUTPUT CLOCK SIGNAL WITH AN ADJUSTABLE PHASE RELATION FROM A PLURALITY OF INPUT CLOCK SIGNALS
65
Patent #:
Issue Dt:
05/27/2008
Application #:
11194509
Filing Dt:
08/01/2005
Publication #:
Pub Dt:
02/02/2006
Title:
DEVICE FOR SETTING A CLOCK DELAY
66
Patent #:
Issue Dt:
10/16/2007
Application #:
11194770
Filing Dt:
08/01/2005
Publication #:
Pub Dt:
03/09/2006
Title:
METHOD AND DEVICE FOR GENERATING A CLOCK SIGNAL USING A PHASE DIFFERENCE SIGNAL AND A FEEDBACK SIGNAL
67
Patent #:
Issue Dt:
07/22/2008
Application #:
11194773
Filing Dt:
08/01/2005
Publication #:
Pub Dt:
02/01/2007
Title:
METHOD OF OPERATING A MEMORY DEVICE, MEMORY MODULE, AND A MEMORY DEVICE COMPRISING THE MEMORY MODULE
68
Patent #:
Issue Dt:
07/08/2008
Application #:
11196369
Filing Dt:
08/03/2005
Publication #:
Pub Dt:
02/08/2007
Title:
TECHNIQUE TO SUPPRESS LEAKAGE CURRENT
69
Patent #:
Issue Dt:
04/15/2008
Application #:
11196513
Filing Dt:
08/04/2005
Publication #:
Pub Dt:
04/13/2006
Title:
METHOD AND APPARATUS FOR THE DEPTH-RESOLVED CHARACTERIZATION OF A LAYER OF A CARRIER
70
Patent #:
Issue Dt:
04/01/2008
Application #:
11198129
Filing Dt:
08/05/2005
Publication #:
Pub Dt:
02/08/2007
Title:
CARD STIFFENER AND INSERTION TOOL
71
Patent #:
Issue Dt:
09/16/2008
Application #:
11198246
Filing Dt:
08/05/2005
Publication #:
Pub Dt:
02/08/2007
Title:
MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM
72
Patent #:
Issue Dt:
05/25/2010
Application #:
11198366
Filing Dt:
08/05/2005
Publication #:
Pub Dt:
02/08/2007
Title:
SYSTEM MEMORY DEVICE HAVING A DUAL PORT
73
Patent #:
Issue Dt:
05/06/2008
Application #:
11200256
Filing Dt:
08/09/2005
Publication #:
Pub Dt:
02/15/2007
Title:
METHOD FOR OPTIMIZING A PHOTOLITHOGRAPHIC MASK
74
Patent #:
Issue Dt:
06/19/2007
Application #:
11200504
Filing Dt:
08/09/2005
Publication #:
Pub Dt:
02/15/2007
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR READING A MEMORY CELL
75
Patent #:
Issue Dt:
04/08/2008
Application #:
11202634
Filing Dt:
08/12/2005
Publication #:
Pub Dt:
03/09/2006
Title:
SEMICONDUCTOR COMPONENT WITH A MOS TRANSISTOR
76
Patent #:
Issue Dt:
04/14/2009
Application #:
11203861
Filing Dt:
08/15/2005
Publication #:
Pub Dt:
02/15/2007
Title:
DIFFERENTIAL CHIP PERFORMANCE WITHIN A MULTI-CHIP PACKAGE
77
Patent #:
Issue Dt:
01/27/2009
Application #:
11203927
Filing Dt:
08/15/2005
Publication #:
Pub Dt:
02/15/2007
Title:
MEMORY DEVICE AND METHOD OF MANUFACTURING A MEMORY DEVICE
78
Patent #:
Issue Dt:
05/13/2008
Application #:
11204201
Filing Dt:
08/15/2005
Publication #:
Pub Dt:
03/01/2007
Title:
INTEGRATED CIRCUIT HAVING RESISTIVE MEMORY
79
Patent #:
Issue Dt:
09/04/2007
Application #:
11204281
Filing Dt:
08/15/2005
Publication #:
Pub Dt:
02/15/2007
Title:
STACKABLE SINGLE PACKAGE AND STACKED MULTI-CHIP ASSEMBLY
80
Patent #:
Issue Dt:
06/03/2008
Application #:
11204604
Filing Dt:
08/15/2005
Publication #:
Pub Dt:
02/15/2007
Title:
METHOD AND APPARATUS FOR MONITORING PRECISION OF WAFER PLACEMENT ALIGNMENT
81
Patent #:
Issue Dt:
05/15/2007
Application #:
11204739
Filing Dt:
08/15/2005
Publication #:
Pub Dt:
02/16/2006
Title:
METHOD FOR TESTING A MEMORY DEVICE AND MEMORY DEVICE FOR CARRYING OUT THE METHOD
82
Patent #:
Issue Dt:
01/23/2007
Application #:
11205402
Filing Dt:
08/17/2005
Title:
SEMICONDUCTOR MEMORY DEVICE
83
Patent #:
Issue Dt:
06/24/2008
Application #:
11206481
Filing Dt:
08/18/2005
Publication #:
Pub Dt:
02/22/2007
Title:
SIGNAL ROUTING ON REDISTRIBUTION LAYER
84
Patent #:
Issue Dt:
12/22/2009
Application #:
11209548
Filing Dt:
08/23/2005
Publication #:
Pub Dt:
03/23/2006
Title:
SEMICONDUCTOR MEMORY AND METHOD FOR FABRICATING THE SEMICONDUCTOR MEMORY
85
Patent #:
Issue Dt:
06/19/2007
Application #:
11209977
Filing Dt:
08/23/2005
Publication #:
Pub Dt:
03/09/2006
Title:
INTEGRATED MEMORY ARRANGEMENT BASED ON RESISTIVE MEMORY CELLS AND PRODUCTION METHOD
86
Patent #:
Issue Dt:
02/19/2008
Application #:
11210055
Filing Dt:
08/23/2005
Publication #:
Pub Dt:
03/08/2007
Title:
FUSE RESISTANCE READ-OUT CIRCUIT
87
Patent #:
Issue Dt:
03/16/2010
Application #:
11210372
Filing Dt:
08/24/2005
Publication #:
Pub Dt:
03/01/2007
Title:
INTEGRATED CIRCUIT HAVING A SWITCH.
88
Patent #:
Issue Dt:
09/04/2007
Application #:
11210387
Filing Dt:
08/24/2005
Publication #:
Pub Dt:
03/02/2006
Title:
SEMICONDUCTOR AND METHOD FOR PRODUCING A SEMICONDUCTOR
89
Patent #:
Issue Dt:
03/04/2008
Application #:
11210525
Filing Dt:
08/24/2005
Publication #:
Pub Dt:
03/08/2007
Title:
PHASE CHANGE MEMORY ARRAY HAVING EQUALIZED RESISTANCE
90
Patent #:
Issue Dt:
12/03/2013
Application #:
11210723
Filing Dt:
08/24/2005
Publication #:
Pub Dt:
03/02/2006
Title:
SEMICONDUCTOR APPARATUS HAVING STACKED SEMICONDUCTOR COMPONENTS
91
Patent #:
Issue Dt:
01/27/2009
Application #:
11211084
Filing Dt:
08/25/2005
Publication #:
Pub Dt:
08/09/2007
Title:
CLOCK SIGNAL SYNCHRONIZING DEVICE, AND CLOCK SIGNAL SYNCHRONIZING METHOD
92
Patent #:
Issue Dt:
02/05/2008
Application #:
11211168
Filing Dt:
08/23/2005
Publication #:
Pub Dt:
10/19/2006
Title:
INTEGRATED ELECTRONIC COMPONENT
93
Patent #:
Issue Dt:
07/31/2007
Application #:
11211824
Filing Dt:
08/25/2005
Publication #:
Pub Dt:
03/01/2007
Title:
DIFFERENTIAL DUTY CYCLE RESTORATION
94
Patent #:
Issue Dt:
11/06/2007
Application #:
11211825
Filing Dt:
08/25/2005
Publication #:
Pub Dt:
03/01/2007
Title:
DELAY LOCKED LOOP USING A FIFO CIRCUIT TO SYNCHRONIZE BETWEEN BLENDER AND COARSE DELAY CONTROL SIGNALS
95
Patent #:
Issue Dt:
01/08/2008
Application #:
11211893
Filing Dt:
08/25/2005
Publication #:
Pub Dt:
03/09/2006
Title:
MEMORY MODULE HAVING MEMORY CHIPS PROTECTED FROM EXCESSIVE HEAT
96
Patent #:
Issue Dt:
02/27/2007
Application #:
11212919
Filing Dt:
08/29/2005
Publication #:
Pub Dt:
03/02/2006
Title:
METHOD FOR TESTING AN INTEGRATED SEMICONDUCTOR MEMORY
97
Patent #:
Issue Dt:
05/13/2008
Application #:
11213342
Filing Dt:
08/26/2005
Publication #:
Pub Dt:
03/09/2006
Title:
INTEGRATED SEMICONDUCTOR CIRCUIT COMPRISING A TRANSISTOR AND A STRIP CONDUCTOR
98
Patent #:
Issue Dt:
07/31/2007
Application #:
11213372
Filing Dt:
08/26/2005
Publication #:
Pub Dt:
03/09/2006
Title:
MEMORY CIRCUIT HAVING MEMORY CELLS WHICH HAVE A RESISTANCE MEMORY ELEMENT
99
Patent #:
Issue Dt:
04/06/2010
Application #:
11214023
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
03/02/2006
Title:
REACTIVE SPUTTERING PROCESS FOR OPTIMIZING THE THERMAL STABILITY OF THIN CHALCOGENIDE LAYERS
100
Patent #:
Issue Dt:
03/11/2008
Application #:
11214067
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
03/23/2006
Title:
DQS SIGNALING IN DDR-III MEMORY SYSTEMS WITHOUT PREAMBLE
Assignor
1
Exec Dt:
10/09/2014
Assignee
1
AM CAMPEON 1-12
NEUBIBERG, GERMANY 85579
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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