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Patent #:
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Issue Dt:
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07/31/2007
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11154943
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Filing Dt:
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06/17/2005
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Publication #:
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Pub Dt:
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01/05/2006
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Title:
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METHOD FOR FABRICATING A SHADOW MASK IN A TRENCH OF A MICROELECTRONIC OR MICROMECHANICAL STRUCTURE
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11/20/2007
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11155277
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06/17/2005
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Publication #:
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Pub Dt:
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12/21/2006
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Title:
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MULTI-CHIP DEVICE AND METHOD FOR PRODUCING A MULTI-CHIP DEVICE
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Patent #:
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Issue Dt:
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08/14/2007
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11155317
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Filing Dt:
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06/17/2005
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Publication #:
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Pub Dt:
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03/09/2006
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Title:
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SUBSTRATE-BASED HOUSING COMPONENT WITH A SEMICONDUCTOR CHIP
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01/22/2008
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11157143
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Filing Dt:
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06/20/2005
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12/21/2006
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Title:
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METHOD OF FORMING A CONTACT IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/02/2007
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11157425
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Filing Dt:
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06/21/2005
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Pub Dt:
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12/21/2006
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Title:
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OUTPUT CIRCUIT THAT TURNS OFF ONE OF A FIRST CIRCUIT AND A SECOND CIRCUIT
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07/17/2007
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11157868
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06/22/2005
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Pub Dt:
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12/28/2006
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Title:
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PARALLEL DATA PATH ARCHITECTURE
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Patent #:
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09/15/2009
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11158271
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06/21/2005
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Publication #:
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Pub Dt:
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12/29/2005
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Title:
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REFLECTION MASK, USE OF THE REFLECTION MASK AND METHOD FOR FABRICATING THE REFLECTION MASK
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02/12/2008
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11158439
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06/22/2005
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11/17/2005
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Title:
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DRAM CELL ARRANGEMENT WITH VERTICAL MOS TRANSISTORS
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02/10/2009
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11159026
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06/22/2005
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01/05/2006
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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01/15/2008
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11159404
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06/23/2005
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12/29/2005
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Title:
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RESISTIVE SEMICONDUCTOR ELEMENT BASED ON A SOLID-STATE ION CONDUCTOR
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02/05/2008
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11165566
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06/24/2005
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01/12/2006
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Title:
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METHOD FOR DETERMINING A MATRIX OF TRANSMISSION CROSS COEFFICIENTS IN AN OPTICAL PROXIMITY CORRECTION OF MASK LAYOUTS
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10/16/2007
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11166788
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06/24/2005
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12/28/2006
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Title:
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MEMORY DEVICE AND METHOD FOR OPERATING THE MEMORY DEVICE
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09/04/2007
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11167510
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06/27/2005
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01/05/2006
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Title:
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METHOD FOR FABRICATING FIELD-EFFECT TRANSISTOR STRUCTURES WITH GATE ELECTRODES WITH A METAL LAYER
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05/20/2008
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11167930
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06/28/2005
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01/05/2006
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Title:
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DEVICE AND A PROCESS FOR THE CALIBRATION OF A SEMICONDUCTOR COMPONENT TEST SYSTEM
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Patent #:
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06/12/2007
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11168818
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06/28/2005
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01/11/2007
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Title:
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DUAL FREQUENCY FIRST-IN-FIRST-OUT STRUCTURE
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07/22/2008
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11168820
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06/28/2005
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Pub Dt:
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12/28/2006
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Title:
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MULTI-CHIP DEVICE AND METHOD FOR PRODUCING A MULTI-CHIP DEVICE
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12/25/2007
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11169812
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06/29/2005
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01/12/2006
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Title:
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METHOD FOR FABRICATING A DRAM MEMORY CELL ARRANGEMENT HAVING FIN FIELD EFFECT TRANSISTORS AND DRAM MEMORY CELL
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09/23/2008
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11170187
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06/29/2005
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01/04/2007
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Title:
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METHOD FOR PRODUCING CHARGE-TRAPPING MEMORY CELL ARRAYS
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01/27/2009
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11170189
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06/29/2005
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01/05/2006
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Title:
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METHOD FOR ADAPTING STRUCTURE DIMENSIONS DURING THE PHOTOLITHOGRAPHIC PROJECTION OF A PATTERN OF STRUCTURE ELEMENTS ONTO A SEMICONDUCTOR WAFER
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10/09/2007
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11170190
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06/29/2005
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01/04/2007
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Title:
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HANDLING UNIT FOR ELECTRONIC DEVICES
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11/06/2007
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11170200
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Filing Dt:
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06/29/2005
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01/04/2007
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Title:
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FLUIDS FOR IMMERSION LITHOGRAPHY SYSTEMS
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Patent #:
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01/29/2008
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11170887
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06/30/2005
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Pub Dt:
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01/04/2007
| | | | |
Title:
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SYNCHRONOUS SIGNAL GENERATOR
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04/29/2008
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11172083
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06/30/2005
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02/09/2006
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Title:
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SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR COMPONENTS CONNECTED TO ONE ANOTHER
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04/21/2009
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11172366
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06/30/2005
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01/04/2007
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Title:
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METHOD FOR FORMING A SEMICONDUCTOR PRODUCT AND SEMICONDUCTOR PRODUCT
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04/10/2007
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11172367
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06/30/2005
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01/04/2007
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Title:
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METHOD AND APPARATUS FOR SENSING A STATE OF A MEMORY CELL
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02/27/2007
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11172421
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06/30/2005
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01/04/2007
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Title:
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METHOD FOR PROGRAMMING MULTI-BIT CHARGE-TRAPPING MEMORY CELL ARRAYS
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04/17/2007
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11173171
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07/01/2005
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01/05/2006
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Title:
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PROCESS FOR PRODUCING A MASK ON A SUBSTRATE
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11/20/2007
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11175280
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07/07/2005
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01/11/2007
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METHOD AND APPARATUS FOR SELECTIVELY ACCESSING AND CONFIGURING INDIVIDUAL CHIPS OF A SEMI-CONDUCTOR WAFER
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08/21/2007
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11175386
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07/07/2005
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01/11/2007
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Title:
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METHOD OF TREATING A SUBSTRATE IN MANUFACTURING A MAGNETORESISTIVE MEMORY CELL
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11/06/2007
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11175724
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07/06/2005
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01/11/2007
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TEMPERATURE DEPENDENT SELF-REFRESH MODULE FOR A MEMORY DEVICE
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07/15/2008
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11177245
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07/08/2005
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01/11/2007
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METHOD OF FORMING A CHARGE-TRAPPING MEMORY DEVICE
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12/25/2007
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11178251
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07/08/2005
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02/09/2006
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PROCESS FOR PRODUCING A LAYER ARRANGEMENT, AND LAYER ARRANGEMENT FOR USE AS A DUAL-GATE FIELD-EFFECT TRANSISTOR
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06/16/2009
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11178915
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07/11/2005
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01/26/2006
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DIGITAL RAM MEMORY CIRCUIT WITH AN EXPANDED COMMAND STRUCTURE
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07/10/2007
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11179345
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07/12/2005
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01/18/2007
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NON-VOLATILE MEMORY CELL DEVICE, PROGRAMMING ELEMENT AND METHOD FOR PROGRAMMING DATA INTO A PLURALITY OF NON-VOLATILE MEMORY CELLS
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04/08/2008
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11179358
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07/12/2005
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01/18/2007
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Title:
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COLUMN REDUNDANCY REUSE IN MEMORY DEVICES
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01/23/2007
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11181387
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07/13/2005
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01/18/2007
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NON-VOLATILE SEMICONDUCTOR MEMORY
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09/02/2008
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11182022
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07/14/2005
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01/18/2007
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Title:
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RESISTIVITY CHANGING MEMORY CELL HAVING NANOWIRE ELECTRODE
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07/22/2008
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11182063
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07/15/2005
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02/08/2007
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Title:
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SEMICONDUCTOR MEMORY DEVICE INCLUDING A SIGNAL CONTROL DEVICE AND METHOD OF OPERATING THE SAME
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05/06/2008
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11182064
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07/15/2005
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01/18/2007
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Title:
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INTEGRATED RECEIVER CIRCUIT
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05/06/2008
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11182066
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07/15/2005
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02/02/2006
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METHOD OF PRODUCING A STRUCTURE ON THE SURFACE OF A SUBSTRATE
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04/10/2007
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11183224
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07/14/2005
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01/18/2007
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Title:
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MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR STRUCTURE AND CORRESPONDING INTEGRATED SEMICONDUCTOR STRUCTURE
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11/06/2007
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11184074
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07/19/2005
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01/25/2007
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Title:
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LOW RESISTANCE CONTACT IN A SEMICONDUCTOR DEVICE
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05/06/2008
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11184532
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07/19/2005
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01/26/2006
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Title:
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METHOD FOR MOUNTING A CHIP ON A BASE AND ARRANGEMENT PRODUCED BY THIS METHOD
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04/14/2009
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11185472
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07/20/2005
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07/27/2006
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METHOD FOR CONNECTION OF AN INTEGRATED CIRCUIT TO A SUBSTRATE, AND A CORRESPONDING CIRCUIT ARRANGEMENT
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10/23/2007
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11187321
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07/22/2005
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01/25/2007
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TEMPERATURE UPDATE MASKING TO ENSURE CORRECT MEASUREMENT OF TEMPERATURE WHEN REFERENCES BECOME UNSTABLE
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06/24/2008
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11187533
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07/22/2005
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01/26/2006
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Title:
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PHASE CHANGE MEMORY DEVICE WITH THERMAL INSULATING LAYERS
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04/17/2007
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11187546
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07/22/2005
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01/25/2007
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Title:
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CLOCKED STANDBY MODE WITH MAXIMUM CLOCK FREQUENCY
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02/13/2007
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11187643
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07/22/2005
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Pub Dt:
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01/25/2007
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Title:
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DISABLING CLOCKED STANDBY MODE BASED ON DEVICE TEMPERATURE
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04/01/2008
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11187693
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07/22/2005
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01/25/2007
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Title:
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NON-VOLATILE MEMORY CELLS AND METHODS FOR FABRICATING NON-VOLATILE MEMORY CELLS
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04/10/2007
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11189018
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07/26/2005
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02/02/2006
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Title:
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INTEGRATED SEMICONDUCTOR MEMORY WITH REDUNDANT MEMORY CELLS
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02/12/2008
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11189231
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07/26/2005
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02/02/2006
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SEMICONDUCTOR CIRCUIT DEVICE AND A SYSTEM FOR TESTING A SEMICONDUCTOR APPARATUS
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07/31/2007
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11190056
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07/27/2005
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02/02/2006
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Title:
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METHOD FOR CORRECTING STRUCTURE-SIZE-DEPENDENT POSITIONING ERRORS IN PHOTOLITHOGRAPHY
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07/17/2007
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11190068
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07/26/2005
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Pub Dt:
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02/01/2007
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Title:
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SUBSTRATE BASED IC-PACKAGE
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02/26/2008
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11191141
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07/28/2005
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Pub Dt:
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02/02/2006
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Title:
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INTEGRATED SEMICONDUCTOR MEMORY
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12/18/2007
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11191167
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07/27/2005
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Pub Dt:
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03/09/2006
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METHOD FOR CORRECTING LAYOUT ERRORS
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Issue Dt:
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11/20/2007
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11191837
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07/28/2005
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Pub Dt:
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03/01/2007
| | | | |
Title:
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NON-VOLATILE, RESISTIVE MEMORY CELL BASED ON METAL OXIDE NANOPARTICLES, PROCESS FOR MANUFACTURING THE SAME AND MEMORY CELL ARRANGEMENT OF THE SAME
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Issue Dt:
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08/19/2008
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11192335
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07/29/2005
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Pub Dt:
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02/01/2007
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Title:
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RE-DRIVING CAWD AND RD SIGNAL LINES
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Issue Dt:
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03/25/2008
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11192981
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07/29/2005
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02/01/2007
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Title:
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SEMICONDUCTOR PACKAGE BASED ON LEAD-ON-CHIP ARCHITECTURE, THE FABRICATION THEREOF AND A LEADFRAME FOR IMPLEMENTING IN A SEMICONDUCTOR PACKAGE
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05/20/2008
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11193024
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Filing Dt:
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07/29/2005
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Pub Dt:
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03/16/2006
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Title:
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METHOD FOR PRODUCTION OF A STANDARD CELL ARRANGEMENT, AND APPARATUS FOR CARRYING OUT THE METHOD
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05/05/2009
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11193026
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07/29/2005
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02/01/2007
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Title:
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SEMICONDUCTOR MEMORY WITH CHARGE-TRAPPING STACK ARRANGEMENT
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01/31/2012
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11193184
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Filing Dt:
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07/29/2005
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Pub Dt:
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02/01/2007
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Title:
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SEMICONDUCTOR MEMORY CHIP AND MEMORY SYSTEM
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03/18/2008
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11194302
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08/01/2005
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Pub Dt:
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02/01/2007
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Title:
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MAINTAINING INTERNAL VOLTAGES OF AN INTEGRATED CIRCUIT IN RESPONSE TO A CLOCKED STANDBY MODE
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11/06/2007
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11194489
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08/01/2005
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02/01/2007
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Title:
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METHOD OF PRODUCING PITCH FRACTIONIZATIONS IN SEMICONDUCTOR TECHNOLOGY
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09/02/2008
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11194494
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08/01/2005
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Pub Dt:
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02/09/2006
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Title:
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METHOD AND ARRANGEMENT FOR GENERATING AN OUTPUT CLOCK SIGNAL WITH AN ADJUSTABLE PHASE RELATION FROM A PLURALITY OF INPUT CLOCK SIGNALS
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Patent #:
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05/27/2008
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11194509
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08/01/2005
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Pub Dt:
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02/02/2006
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Title:
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DEVICE FOR SETTING A CLOCK DELAY
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10/16/2007
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11194770
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08/01/2005
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Pub Dt:
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03/09/2006
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Title:
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METHOD AND DEVICE FOR GENERATING A CLOCK SIGNAL USING A PHASE DIFFERENCE SIGNAL AND A FEEDBACK SIGNAL
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07/22/2008
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11194773
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08/01/2005
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Pub Dt:
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02/01/2007
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Title:
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METHOD OF OPERATING A MEMORY DEVICE, MEMORY MODULE, AND A MEMORY DEVICE COMPRISING THE MEMORY MODULE
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07/08/2008
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11196369
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08/03/2005
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02/08/2007
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Title:
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TECHNIQUE TO SUPPRESS LEAKAGE CURRENT
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04/15/2008
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11196513
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08/04/2005
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04/13/2006
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Title:
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METHOD AND APPARATUS FOR THE DEPTH-RESOLVED CHARACTERIZATION OF A LAYER OF A CARRIER
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04/01/2008
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11198129
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08/05/2005
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02/08/2007
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Title:
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CARD STIFFENER AND INSERTION TOOL
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09/16/2008
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11198246
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08/05/2005
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02/08/2007
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Title:
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MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM
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05/25/2010
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11198366
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08/05/2005
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02/08/2007
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Title:
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SYSTEM MEMORY DEVICE HAVING A DUAL PORT
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05/06/2008
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11200256
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08/09/2005
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02/15/2007
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Title:
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METHOD FOR OPTIMIZING A PHOTOLITHOGRAPHIC MASK
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06/19/2007
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11200504
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08/09/2005
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02/15/2007
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Title:
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NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR READING A MEMORY CELL
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04/08/2008
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11202634
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08/12/2005
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03/09/2006
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Title:
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SEMICONDUCTOR COMPONENT WITH A MOS TRANSISTOR
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04/14/2009
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11203861
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08/15/2005
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02/15/2007
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Title:
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DIFFERENTIAL CHIP PERFORMANCE WITHIN A MULTI-CHIP PACKAGE
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01/27/2009
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11203927
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08/15/2005
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02/15/2007
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Title:
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MEMORY DEVICE AND METHOD OF MANUFACTURING A MEMORY DEVICE
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05/13/2008
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11204201
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08/15/2005
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03/01/2007
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Title:
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INTEGRATED CIRCUIT HAVING RESISTIVE MEMORY
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09/04/2007
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11204281
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08/15/2005
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02/15/2007
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Title:
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STACKABLE SINGLE PACKAGE AND STACKED MULTI-CHIP ASSEMBLY
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06/03/2008
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11204604
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08/15/2005
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02/15/2007
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Title:
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METHOD AND APPARATUS FOR MONITORING PRECISION OF WAFER PLACEMENT ALIGNMENT
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05/15/2007
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11204739
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08/15/2005
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02/16/2006
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Title:
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METHOD FOR TESTING A MEMORY DEVICE AND MEMORY DEVICE FOR CARRYING OUT THE METHOD
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01/23/2007
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11205402
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08/17/2005
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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06/24/2008
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11206481
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08/18/2005
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02/22/2007
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SIGNAL ROUTING ON REDISTRIBUTION LAYER
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12/22/2009
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11209548
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08/23/2005
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03/23/2006
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SEMICONDUCTOR MEMORY AND METHOD FOR FABRICATING THE SEMICONDUCTOR MEMORY
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06/19/2007
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11209977
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08/23/2005
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03/09/2006
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Title:
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INTEGRATED MEMORY ARRANGEMENT BASED ON RESISTIVE MEMORY CELLS AND PRODUCTION METHOD
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02/19/2008
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11210055
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08/23/2005
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03/08/2007
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FUSE RESISTANCE READ-OUT CIRCUIT
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03/16/2010
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11210372
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08/24/2005
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03/01/2007
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INTEGRATED CIRCUIT HAVING A SWITCH.
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09/04/2007
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11210387
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08/24/2005
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03/02/2006
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SEMICONDUCTOR AND METHOD FOR PRODUCING A SEMICONDUCTOR
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03/04/2008
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11210525
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08/24/2005
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03/08/2007
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PHASE CHANGE MEMORY ARRAY HAVING EQUALIZED RESISTANCE
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12/03/2013
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11210723
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08/24/2005
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03/02/2006
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SEMICONDUCTOR APPARATUS HAVING STACKED SEMICONDUCTOR COMPONENTS
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01/27/2009
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11211084
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08/25/2005
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08/09/2007
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CLOCK SIGNAL SYNCHRONIZING DEVICE, AND CLOCK SIGNAL SYNCHRONIZING METHOD
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02/05/2008
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11211168
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08/23/2005
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10/19/2006
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INTEGRATED ELECTRONIC COMPONENT
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07/31/2007
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11211824
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08/25/2005
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03/01/2007
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DIFFERENTIAL DUTY CYCLE RESTORATION
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11/06/2007
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11211825
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08/25/2005
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03/01/2007
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DELAY LOCKED LOOP USING A FIFO CIRCUIT TO SYNCHRONIZE BETWEEN BLENDER AND COARSE DELAY CONTROL SIGNALS
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01/08/2008
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11211893
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08/25/2005
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03/09/2006
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MEMORY MODULE HAVING MEMORY CHIPS PROTECTED FROM EXCESSIVE HEAT
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02/27/2007
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11212919
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08/29/2005
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03/02/2006
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METHOD FOR TESTING AN INTEGRATED SEMICONDUCTOR MEMORY
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05/13/2008
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11213342
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08/26/2005
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03/09/2006
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT COMPRISING A TRANSISTOR AND A STRIP CONDUCTOR
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07/31/2007
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11213372
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08/26/2005
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03/09/2006
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Title:
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MEMORY CIRCUIT HAVING MEMORY CELLS WHICH HAVE A RESISTANCE MEMORY ELEMENT
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04/06/2010
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11214023
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08/30/2005
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03/02/2006
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Title:
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REACTIVE SPUTTERING PROCESS FOR OPTIMIZING THE THERMAL STABILITY OF THIN CHALCOGENIDE LAYERS
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03/11/2008
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11214067
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08/30/2005
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03/23/2006
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Title:
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DQS SIGNALING IN DDR-III MEMORY SYSTEMS WITHOUT PREAMBLE
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