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Patent Assignment Details
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Reel/Frame:035623/0001   Pages: 181
Recorded: 05/08/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 4024
Page 36 of 41
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
1
Patent #:
Issue Dt:
10/14/2008
Application #:
11602720
Filing Dt:
11/21/2006
Publication #:
Pub Dt:
05/22/2008
Title:
RESISTIVE MEMORY INCLUDING BIPOLAR TRANSISTOR ACCESS DEVICES
2
Patent #:
Issue Dt:
05/26/2009
Application #:
11603636
Filing Dt:
11/22/2006
Publication #:
Pub Dt:
05/22/2008
Title:
RESISTIVE MEMORY INCLUDING REFRESH OPERATION
3
Patent #:
Issue Dt:
05/18/2010
Application #:
11604666
Filing Dt:
11/27/2006
Publication #:
Pub Dt:
05/29/2008
Title:
APPARATUS AND METHOD FOR SWITCHING AN APPARATUS TO A POWER SAVING MODE
4
Patent #:
Issue Dt:
11/17/2009
Application #:
11605079
Filing Dt:
11/28/2006
Publication #:
Pub Dt:
05/29/2008
Title:
MEMORY CELL WITH TRIGGER ELEMENT
5
Patent #:
Issue Dt:
11/03/2009
Application #:
11606812
Filing Dt:
11/29/2006
Publication #:
Pub Dt:
05/29/2008
Title:
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
6
Patent #:
Issue Dt:
12/16/2008
Application #:
11607518
Filing Dt:
12/01/2006
Publication #:
Pub Dt:
09/04/2008
Title:
OUTPUT DRIVER
7
Patent #:
Issue Dt:
12/29/2009
Application #:
11611222
Filing Dt:
12/15/2006
Publication #:
Pub Dt:
06/19/2008
Title:
CIRCUIT AND METHOD FOR SUPPRESSING GATE INDUCED DRAIN LEAKAGE
8
Patent #:
Issue Dt:
08/19/2008
Application #:
11612541
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
DIE AND WAFER FAILURE CLASSIFICATION SYSTEM AND METHOD
9
Patent #:
Issue Dt:
02/16/2010
Application #:
11615101
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
DELAYED SENSE AMPLIFIER MULTIPLEXER ISOLATION
10
Patent #:
Issue Dt:
10/28/2008
Application #:
11615118
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
PROGRAMMABLE SENSE AMPLIFIER MULTIPLEXER CIRCUIT WITH DYNAMIC LATCHING MODE
11
Patent #:
Issue Dt:
06/15/2010
Application #:
11615418
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
SENDER, RECEIVER AND METHOD OF TRANSFERRING INFORMATION FROM A SENDER TO A RECEIVER
12
Patent #:
Issue Dt:
03/22/2011
Application #:
11618172
Filing Dt:
12/29/2006
Publication #:
Pub Dt:
09/13/2007
Title:
CHIP CARRIER WITH REDUCED INTERFERENCE SIGNAL SENSITIVITY
13
Patent #:
Issue Dt:
04/07/2009
Application #:
11620432
Filing Dt:
01/05/2007
Publication #:
Pub Dt:
07/10/2008
Title:
CURRENT COMPLIANT SENSING ARCHITECTURE FOR MULTILEVEL PHASE CHANGE MEMORY
14
Patent #:
Issue Dt:
07/15/2008
Application #:
11622802
Filing Dt:
01/12/2007
Publication #:
Pub Dt:
07/17/2008
Title:
INTEGRATED CIRCUIT, MEMORY CHIP AND METHOD OF EVALUATING A MEMORY STATE OF A RESISTIVE MEMORY CELL
15
Patent #:
Issue Dt:
01/18/2011
Application #:
11624465
Filing Dt:
01/18/2007
Publication #:
Pub Dt:
07/24/2008
Title:
MULTI-COMPONENT MODULE FLY-BY OUTPUT ALIGNMENT ARRANGEMENT AND METHOD
16
Patent #:
Issue Dt:
03/30/2010
Application #:
11633090
Filing Dt:
12/04/2006
Publication #:
Pub Dt:
06/05/2008
Title:
STORAGE CAPACITOR, A MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME
17
Patent #:
Issue Dt:
04/06/2010
Application #:
11633210
Filing Dt:
12/04/2006
Publication #:
Pub Dt:
06/05/2008
Title:
MULTI-BIT RESISTIVE MEMORY
18
Patent #:
Issue Dt:
10/09/2007
Application #:
11634988
Filing Dt:
12/07/2006
Publication #:
Pub Dt:
04/19/2007
Title:
MRAM MEMORY CELL HAVING A WEAK INTRINSIC ANISOTROPIC STORAGE LAYER AND METHOD OF PRODUCING THE SAME
19
Patent #:
Issue Dt:
10/21/2008
Application #:
11635088
Filing Dt:
12/07/2006
Publication #:
Pub Dt:
06/14/2007
Title:
INTEGRATED SEMICONDUCTOR MEMORY WITH DETERMINATION OF A CHIP TEMPERATURE
20
Patent #:
Issue Dt:
01/01/2008
Application #:
11636616
Filing Dt:
12/11/2006
Publication #:
Pub Dt:
04/12/2007
Title:
HYBRID MEMORY CELL FOR SPIN-POLARIZED ELECTRON CURRENT INDUCED SWITCHING AND WRITING/READING PROCESS USING SUCH MEMORY CELL
21
Patent #:
Issue Dt:
08/19/2008
Application #:
11638089
Filing Dt:
12/13/2006
Publication #:
Pub Dt:
03/06/2008
Title:
CIRCUIT ARRANGEMENT AND METHOD FOR CONVERTING LOGIC SIGNAL LEVELS AND USE OF THE CIRCUIT ARRANGEMENT
22
Patent #:
Issue Dt:
07/14/2009
Application #:
11638310
Filing Dt:
12/12/2006
Publication #:
Pub Dt:
10/04/2007
Title:
ARRANGEMENT OF SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY MODULE COMPRISING AN ARRANGEMENT OF SEMICONDUCTOR MEMORY DEVICES
23
Patent #:
Issue Dt:
04/28/2009
Application #:
11638324
Filing Dt:
12/13/2006
Publication #:
Pub Dt:
06/19/2008
Title:
CIRCUIT AND METHOD FOR ADJUSTING A VOLTAGE DROP
24
Patent #:
Issue Dt:
06/02/2009
Application #:
11638766
Filing Dt:
12/14/2006
Publication #:
Pub Dt:
07/05/2007
Title:
MEASURING METHOD FOR A SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR MEMORY
25
Patent #:
Issue Dt:
03/29/2011
Application #:
11639161
Filing Dt:
12/15/2006
Publication #:
Pub Dt:
06/19/2008
Title:
METHOD AND APPARATUS FOR SELECTIVELY UTILIZING INFORMATION WITHIN A SEMICONDUCTOR DEVICE
26
Patent #:
Issue Dt:
05/29/2012
Application #:
11640065
Filing Dt:
12/15/2006
Publication #:
Pub Dt:
06/19/2008
Title:
PHASE CHANGE RANDOM ACCESS MEMORY DEVICE WITH TRANSISTOR, AND METHOD FOR FABRICATING A MEMORY DEVICE
27
Patent #:
Issue Dt:
07/29/2008
Application #:
11641545
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY CIRCUIT REQUIRING A SECOND SUPPLY VOLTAGE
28
Patent #:
Issue Dt:
09/13/2011
Application #:
11643438
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
PILLAR PHASE CHANGE MEMORY CELL
29
Patent #:
Issue Dt:
01/25/2011
Application #:
11644044
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
MEMORY DEVICE
30
Patent #:
Issue Dt:
07/27/2010
Application #:
11644084
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/28/2007
Title:
SYNCHRONIZATION OF A DIGITAL CIRCUIT
31
Patent #:
Issue Dt:
07/21/2009
Application #:
11644090
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
32
Patent #:
Issue Dt:
05/26/2009
Application #:
11644285
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
INTEGRATED CIRCUIT HAVING A METAL ELEMENT
33
Patent #:
Issue Dt:
08/21/2007
Application #:
11644792
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
05/10/2007
Title:
FERROMAGNETIC LINER FOR CONDUCTIVE LINES OF MAGNETIC MEMORY CELLS
34
Patent #:
Issue Dt:
05/03/2011
Application #:
11644998
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
APPARATUS AND METHOD FOR PROVIDING A SIGNAL FOR TRANSMISSION VIA A SIGNAL LINE
35
Patent #:
Issue Dt:
09/14/2010
Application #:
11647602
Filing Dt:
12/29/2006
Publication #:
Pub Dt:
07/03/2008
Title:
METHOD OF FORMING AN INTEGRATED CIRCUIT WITH TWO TYPES OF TRANSISTORS
36
Patent #:
Issue Dt:
01/05/2010
Application #:
11649047
Filing Dt:
01/03/2007
Publication #:
Pub Dt:
05/17/2007
Title:
CONTINUOUS SELF-CALIBRATION OF INTERNAL ANALOG SIGNALS
37
Patent #:
Issue Dt:
09/14/2010
Application #:
11650120
Filing Dt:
01/05/2007
Publication #:
Pub Dt:
07/10/2008
Title:
MEMORY REFRESH SYSTEM AND METHOD
38
Patent #:
Issue Dt:
04/07/2009
Application #:
11650244
Filing Dt:
01/05/2007
Publication #:
Pub Dt:
12/06/2007
Title:
HIGH DENSITY MEMORY ARRAY FOR LOW POWER APPLICATION
39
Patent #:
Issue Dt:
01/26/2010
Application #:
11651157
Filing Dt:
01/09/2007
Publication #:
Pub Dt:
07/10/2008
Title:
MEMORY INCLUDING TWO ACCESS DEVICES PER PHASE CHANGE ELEMENT
40
Patent #:
Issue Dt:
02/23/2010
Application #:
11655583
Filing Dt:
01/19/2007
Publication #:
Pub Dt:
07/24/2008
Title:
DEPOSITION METHOD FOR A TRANSITION-METAL-CONTAINING DIELECTRIC
41
Patent #:
Issue Dt:
10/21/2008
Application #:
11657407
Filing Dt:
01/24/2007
Publication #:
Pub Dt:
08/23/2007
Title:
SEMICONDUCTOR COMPONENT COMPRISING AN INTEGRATED SEMICONDUCTOR CHIP AND A CHIP HOUSING, AND ELECTRONIC DEVICE
42
Patent #:
Issue Dt:
01/05/2010
Application #:
11668565
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
08/23/2007
Title:
METHOD FOR PRODUCING A MASK FOR THE LITHOGRAPHIC PROJECTION OF A PATTERN ONTO A SUBSTRATE
43
Patent #:
Issue Dt:
02/10/2009
Application #:
11668753
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
07/31/2008
Title:
MEMORY DEVICE WITH ADAPTIVE SENSE UNIT AND METHOD OF READING A CELL ARRAY
44
Patent #:
Issue Dt:
09/27/2011
Application #:
11668849
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT FOR RECEIVING DATA
45
Patent #:
Issue Dt:
04/28/2009
Application #:
11668992
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
07/31/2008
Title:
PHASE CHANGE MEMORY CELL DESIGN WITH ADJUSTED SEAM LOCATION
46
Patent #:
Issue Dt:
03/16/2010
Application #:
11669500
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
02/07/2008
Title:
METHOD OF REMOVING REFRACTORY METAL LAYERS AND OF SILICIDING CONTACT AREAS
47
Patent #:
Issue Dt:
06/01/2010
Application #:
11669613
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
METHOD OF PRODUCING AN INTEGRATED CIRCUIT HAVING A CAPACITOR WITH A SUPPORTING LAYER
48
Patent #:
Issue Dt:
06/29/2010
Application #:
11669848
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
ASYNCHRONOUS DATA TRANSMISSION
49
Patent #:
Issue Dt:
10/28/2008
Application #:
11669959
Filing Dt:
02/01/2007
Publication #:
Pub Dt:
08/09/2007
Title:
INTEGRATED SEMICONDUCTOR MEMORY DEVICES WITH GENERATION OF VOLTAGES
50
Patent #:
Issue Dt:
03/03/2009
Application #:
11672343
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
06/28/2007
Title:
MEMORY WITH RESISTANCE MEMORY CELL AND EVALUATION CIRCUIT
51
Patent #:
Issue Dt:
11/16/2010
Application #:
11674164
Filing Dt:
02/13/2007
Publication #:
Pub Dt:
08/14/2008
Title:
3-D CHANNEL FIELD-EFFECT TRANSISTOR, MEMORY CELL AND INTEGRATED CIRCUIT
52
Patent #:
Issue Dt:
11/30/2010
Application #:
11675460
Filing Dt:
02/15/2007
Publication #:
Pub Dt:
08/21/2008
Title:
GATE ELECTRODE STRUCTURE, MOS FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING THE SAME
53
Patent #:
Issue Dt:
12/09/2008
Application #:
11676622
Filing Dt:
02/20/2007
Publication #:
Pub Dt:
08/21/2008
Title:
INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
54
Patent #:
Issue Dt:
01/11/2011
Application #:
11676635
Filing Dt:
02/20/2007
Publication #:
Pub Dt:
08/21/2008
Title:
METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES
55
Patent #:
Issue Dt:
11/23/2010
Application #:
11676774
Filing Dt:
02/20/2007
Publication #:
Pub Dt:
08/21/2008
Title:
POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE
56
Patent #:
Issue Dt:
07/27/2010
Application #:
11679295
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
INTEGRATED CIRCUIT AND METHODS OF MANUFACTURING A CONTACT ARRANGEMENT AND AN INTERCONNECTION ARRANGEMENT
57
Patent #:
Issue Dt:
05/19/2009
Application #:
11679609
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/30/2007
Title:
MEMORY ARRANGEMENT
58
Patent #:
Issue Dt:
05/25/2010
Application #:
11679732
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/30/2007
Title:
MEMORY ARRANGEMENT HAVING EFFICIENT ARRANGEMENT OF DEVICES
59
Patent #:
Issue Dt:
11/10/2009
Application #:
11683629
Filing Dt:
03/08/2007
Publication #:
Pub Dt:
09/11/2008
Title:
ABBREVIATED BURST DATA TRANSFERS FOR SEMICONDUCTOR MEMORY
60
Patent #:
Issue Dt:
07/06/2010
Application #:
11684533
Filing Dt:
03/09/2007
Publication #:
Pub Dt:
09/27/2007
Title:
INTEGRATED DEVICE FOR SIMPLIFIED PARALLEL TESTING, TEST BOARD FOR TESTING A PLURALITY OF INTEGRATED DEVICES, AND TEST SYSTEM AND TESTER UNIT
61
Patent #:
Issue Dt:
08/18/2009
Application #:
11686211
Filing Dt:
03/14/2007
Publication #:
Pub Dt:
09/18/2008
Title:
INTEGRATED CIRCUITS, METHODS FOR MANUFACTURING INTEGRATED CIRCUITS, INTEGRATED MEMORY ARRAYS
62
Patent #:
Issue Dt:
07/27/2010
Application #:
11686450
Filing Dt:
03/15/2007
Publication #:
Pub Dt:
09/25/2008
Title:
MULTI-MODE VOLTAGE SUPPLY CIRCUIT
63
Patent #:
Issue Dt:
11/22/2011
Application #:
11687365
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
09/18/2008
Title:
RESISTIVE MEMORY AND METHOD
64
Patent #:
Issue Dt:
08/17/2010
Application #:
11687426
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
12/13/2007
Title:
METHODS FOR FORMING AN INTEGRATED CIRCUIT, INCLUDING OPENINGS IN A MOLD LAYER FROM NANOWIRES OR NANOTUBES
65
Patent #:
Issue Dt:
06/08/2010
Application #:
11688949
Filing Dt:
03/21/2007
Publication #:
Pub Dt:
09/25/2008
Title:
MEMORY DEVICE, A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING A MEMORY DEVICE
66
Patent #:
Issue Dt:
12/07/2010
Application #:
11692245
Filing Dt:
03/28/2007
Publication #:
Pub Dt:
10/02/2008
Title:
REDUCED-DELAY CLOCKED LOGIC
67
Patent #:
Issue Dt:
12/29/2009
Application #:
11692637
Filing Dt:
03/28/2007
Publication #:
Pub Dt:
10/02/2008
Title:
SEMICONDUCTOR DEVICE
68
Patent #:
Issue Dt:
02/02/2010
Application #:
11693391
Filing Dt:
03/29/2007
Publication #:
Pub Dt:
10/02/2008
Title:
INTEGRATED CIRCUIT HAVING A RESISTIVELY SWITCHING MEMORY AND METHOD
69
Patent #:
Issue Dt:
05/26/2009
Application #:
11694393
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
08/28/2008
Title:
INTEGRATED CIRCUIT HAVING A RESISTIVE SWITCHING DEVICE
70
Patent #:
Issue Dt:
03/16/2010
Application #:
11695676
Filing Dt:
04/03/2007
Publication #:
Pub Dt:
10/09/2008
Title:
CONFIGURABLE MEMORY DATA PATH
71
Patent #:
Issue Dt:
07/20/2010
Application #:
11696777
Filing Dt:
04/05/2007
Publication #:
Pub Dt:
10/09/2008
Title:
SEMICONDUCTOR MEMORY DEVICE WITH TEMPERATURE CONTROL
72
Patent #:
Issue Dt:
07/19/2011
Application #:
11697792
Filing Dt:
04/09/2007
Publication #:
Pub Dt:
10/09/2008
Title:
MEMORY MODULE WITH RANKS OF MEMORY CHIPS
73
Patent #:
Issue Dt:
08/25/2009
Application #:
11697883
Filing Dt:
04/09/2007
Publication #:
Pub Dt:
08/09/2007
Title:
METHOD FOR CLEANING A SEMICONDUCTOR WAFER
74
Patent #:
Issue Dt:
06/30/2009
Application #:
11700399
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
BUS STRUCTURE, MEMORY CHIP AND INTEGRATED CIRCUIT
75
Patent #:
Issue Dt:
05/19/2009
Application #:
11700547
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND MASK FOR MANUFACTURING A SEMICONDUCTOR DEVICE
76
Patent #:
Issue Dt:
05/26/2009
Application #:
11701006
Filing Dt:
02/01/2007
Publication #:
Pub Dt:
08/07/2008
Title:
MEMORY CONFIGURED ON A COMMON SUBSTRATE
77
Patent #:
Issue Dt:
09/21/2010
Application #:
11701198
Filing Dt:
02/01/2007
Publication #:
Pub Dt:
08/07/2008
Title:
RESISTIVE MEMORY INCLUDING BURIED WORD LINES
78
Patent #:
Issue Dt:
10/20/2009
Application #:
11704783
Filing Dt:
02/09/2007
Publication #:
Pub Dt:
08/14/2008
Title:
MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR MEMORY DEVICE AND CORRESPONDING SEMICONDUCTOR MEMORY DEVICE
79
Patent #:
Issue Dt:
11/11/2008
Application #:
11707408
Filing Dt:
02/16/2007
Publication #:
Pub Dt:
07/05/2007
Title:
SYSTEM AND METHOD FOR TESTING ONE OR MORE DIES ON A SEMICONDUCTOR WAFER
80
Patent #:
Issue Dt:
02/22/2011
Application #:
11708757
Filing Dt:
02/20/2007
Publication #:
Pub Dt:
05/01/2008
Title:
CARBON FILAMENT MEMORY AND FABRICATION METHOD
81
Patent #:
Issue Dt:
11/09/2010
Application #:
11709289
Filing Dt:
02/21/2007
Publication #:
Pub Dt:
08/21/2008
Title:
INTEGRATED CIRCUIT, METHOD OF READING DATA STORED WITHIN A MEMORY DEVICE OF AN INTEGRATED CIRCUIT, METHOD OF WRITING DATA INTO A MEMORY DEVICE OF AN INTEGRATED CIRCUIT, MEMORY MODULE, AND COMPUTER PROGRAM
82
Patent #:
Issue Dt:
05/11/2010
Application #:
11712635
Filing Dt:
03/01/2007
Publication #:
Pub Dt:
07/05/2007
Title:
METHOD FOR CLASSIFYING ERRORS IN THE LAYOUT OF A SEMICONDUCTOR CIRCUIT
83
Patent #:
Issue Dt:
03/01/2011
Application #:
11715749
Filing Dt:
03/08/2007
Publication #:
Pub Dt:
09/11/2008
Title:
METHOD TO PREVENT OVERRESET
84
Patent #:
Issue Dt:
06/01/2010
Application #:
11715824
Filing Dt:
03/08/2007
Publication #:
Pub Dt:
09/11/2008
Title:
CARBON MEMORY
85
Patent #:
Issue Dt:
05/18/2010
Application #:
11715839
Filing Dt:
03/08/2007
Publication #:
Pub Dt:
09/13/2007
Title:
INTEGRATED SEMICONDUCTOR MEMORY
86
Patent #:
Issue Dt:
11/12/2013
Application #:
11720954
Filing Dt:
01/12/2011
Publication #:
Pub Dt:
06/30/2011
Title:
METHOD OF APPLYING AN ADHESIVE LAYER ON THINCUT SEMICONDUCTOR CHIPS OF A SEMICONDUCTOR WAFER
87
Patent #:
Issue Dt:
10/21/2008
Application #:
11724057
Filing Dt:
03/14/2007
Publication #:
Pub Dt:
09/13/2007
Title:
SEMICONDUCTOR MEMORY DEVICE
88
Patent #:
Issue Dt:
06/26/2012
Application #:
11726401
Filing Dt:
03/21/2007
Publication #:
Pub Dt:
09/18/2008
Title:
CIRCUIT
89
Patent #:
Issue Dt:
05/25/2010
Application #:
11731457
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
10/02/2008
Title:
ZIRCONIUM OXIDE BASED CAPACITOR AND PROCESS TO MANUFACTURE THE SAME
90
Patent #:
Issue Dt:
11/16/2010
Application #:
11731763
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
10/25/2007
Title:
INTEGRATED SEMICONDUCTOR MEMORY WITH GENERATION OF DATA
91
Patent #:
Issue Dt:
01/18/2011
Application #:
11733679
Filing Dt:
04/10/2007
Publication #:
Pub Dt:
10/16/2008
Title:
MULTI-CHIP MODULE
92
Patent #:
Issue Dt:
03/30/2010
Application #:
11734433
Filing Dt:
04/12/2007
Publication #:
Pub Dt:
10/16/2008
Title:
SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND A METHOD FOR OPERATING THE SAME
93
Patent #:
Issue Dt:
01/05/2010
Application #:
11735164
Filing Dt:
04/13/2007
Publication #:
Pub Dt:
10/16/2008
Title:
INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT
94
Patent #:
Issue Dt:
04/07/2009
Application #:
11735748
Filing Dt:
04/16/2007
Publication #:
Pub Dt:
10/16/2008
Title:
CIRCUIT HAVING A CLOCK SIGNAL SYNCHRONIZING DEVICE WITH CAPABILITY TO FILTER CLOCK-JITTER
95
Patent #:
Issue Dt:
12/15/2009
Application #:
11735928
Filing Dt:
04/16/2007
Publication #:
Pub Dt:
10/25/2007
Title:
MEMORY DEVICE AND METHOD OF OPERATING SUCH
96
Patent #:
Issue Dt:
02/16/2010
Application #:
11735971
Filing Dt:
04/16/2007
Publication #:
Pub Dt:
12/06/2007
Title:
MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING SUCH
97
Patent #:
Issue Dt:
05/22/2012
Application #:
11737108
Filing Dt:
04/18/2007
Publication #:
Pub Dt:
10/25/2007
Title:
MEMORY CIRCUIT HAVING MEMORY CHIPS PARALLEL CONNECTED TO PORTS AND CORRESPONDING PRODUCTION METHOD
98
Patent #:
Issue Dt:
07/15/2014
Application #:
11737531
Filing Dt:
04/19/2007
Publication #:
Pub Dt:
10/23/2008
Title:
STACKED SONOS MEMORY
99
Patent #:
Issue Dt:
05/11/2010
Application #:
11737617
Filing Dt:
04/19/2007
Publication #:
Pub Dt:
10/23/2008
Title:
INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING THEREOF
100
Patent #:
Issue Dt:
05/11/2010
Application #:
11737838
Filing Dt:
04/20/2007
Publication #:
Pub Dt:
08/16/2007
Title:
PHASE CHANGE MEMORY CELL WITH HIGH READ MARGIN AT LOW POWER OPERATION
Assignor
1
Exec Dt:
10/09/2014
Assignee
1
AM CAMPEON 1-12
NEUBIBERG, GERMANY 85579
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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