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Reel/Frame:035623/0001   Pages: 181
Recorded: 05/08/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 4024
Page 5 of 41
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
1
Patent #:
6215349
Issue Dt:
04/10/2001
Application #:
09265253
Filing Dt:
03/09/1999
Title:
CAPACITIVE COUPLED DRIVER CIRCUIT
2
Patent #:
6294919
Issue Dt:
09/25/2001
Application #:
09266038
Filing Dt:
03/11/1999
Title:
METHOD FOR NONDESTRUCTIVE MEASUREMENT OF DOPANT CONCENTRATIONS AND PROFILES IN THE DRIFT REGION OF CERTAIN SEMICONDUCTOR DEVICES
3
Patent #:
6346821
Issue Dt:
02/12/2002
Application #:
09266039
Filing Dt:
03/11/1999
Title:
METHOD FOR NONDESTRUCTIVE MEASUREMENT OF MINORITY CARRIER DIFFUSION LENGTH AND MINORITY CARRIER LIFETIME IN SEMICONDUCTOR DEVICES
4
Patent #:
6114074
Issue Dt:
09/05/2000
Application #:
09266473
Filing Dt:
03/11/1999
Title:
EXTRUSION ENHANCED MASK FOR IMPROVING WINDOW
5
Patent #:
6181183
Issue Dt:
01/30/2001
Application #:
09269047
Filing Dt:
03/18/1999
Title:
STEEP EDGE TIME-DELAY RELAY
6
Patent #:
6184107
Issue Dt:
02/06/2001
Application #:
09271124
Filing Dt:
03/17/1999
Title:
CAPACITOR TRENCH-TOP DIELECTRIC FOR SELF-ALIGNED DEVICE ISOLATION
7
Patent #:
6429131
Issue Dt:
08/06/2002
Application #:
09271684
Filing Dt:
03/18/1999
Publication #:
US20010034134
Pub Dt:
10/25/2001
Title:
CMP UNIFORMITY
8
Patent #:
6097049
Issue Dt:
08/01/2000
Application #:
09272077
Filing Dt:
03/18/1999
Title:
DRAM CELL ARRANGEMENT
9
Patent #:
6211544
Issue Dt:
04/03/2001
Application #:
09272215
Filing Dt:
03/18/1999
Title:
MEMORY CELL LAYOUT FOR REDUCED INTERACTION BETWEEN STORAGE NODES AND TRANSISTORS
10
Patent #:
6200851
Issue Dt:
03/13/2001
Application #:
09272217
Filing Dt:
03/18/1999
Title:
MEMORY CELL THAT INCLUDES A VERTICAL TRANSISTOR AND A TRENCH CAPACITOR
11
Patent #:
6150210
Issue Dt:
11/21/2000
Application #:
09272218
Filing Dt:
03/18/1999
Title:
MEMORY CELL THAT INCLUDES A VERTICAL TRANSISTOR AND A TRENCH CAPACITOR
12
Patent #:
6573593
Issue Dt:
06/03/2003
Application #:
09272668
Filing Dt:
03/18/1999
Title:
INTEGRATED CIRCUIT WITH A HOUSING ACCOMMODATING THE INTEGRATED CIRCUIT
13
Patent #:
6281079
Issue Dt:
08/28/2001
Application #:
09272968
Filing Dt:
03/19/1999
Title:
MOS TRANSISTOR IN A SINGLE-TRANSISTOR MEMORY CELL HAVING A LOCALLY THICKENED GATE OXIDE, AND PRODUCTION PROCESS
14
Patent #:
6044006
Issue Dt:
03/28/2000
Application #:
09273648
Filing Dt:
03/23/1999
Title:
METHOD FOR PROGRAMMING A ROM CELL ARRANGEMENT
15
Patent #:
6367027
Issue Dt:
04/02/2002
Application #:
09273842
Filing Dt:
03/22/1999
Title:
SKEW POINTER GENERATION
16
Patent #:
6229364
Issue Dt:
05/08/2001
Application #:
09274633
Filing Dt:
03/23/1999
Title:
FREQUENCY RANGE TRIMMING FOR A DELAY LINE
17
Patent #:
6044009
Issue Dt:
03/28/2000
Application #:
09274733
Filing Dt:
03/23/1999
Title:
DRAM CELL ARRANGEMENT AND METHOD FOR ITS PRODUCTION
18
Patent #:
6204140
Issue Dt:
03/20/2001
Application #:
09275337
Filing Dt:
03/24/1999
Title:
DYNAMIC RANDOM ACCESS MEMORY
19
Patent #:
6245629
Issue Dt:
06/12/2001
Application #:
09276027
Filing Dt:
03/25/1999
Title:
SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
20
Patent #:
6693447
Issue Dt:
02/17/2004
Application #:
09277281
Filing Dt:
03/26/1999
Title:
CONFIGURATION FOR INDENTIFYING CONTACT FAULTS DURING THE TESTING OF INTEGRATED CIRCUITS
21
Patent #:
6083788
Issue Dt:
07/04/2000
Application #:
09277669
Filing Dt:
03/26/1999
Title:
STACKED CAPACITOR MEMORY CELL AND METHOD OF MANUFACUTRE
22
Patent #:
6162735
Issue Dt:
12/19/2000
Application #:
09277673
Filing Dt:
03/26/1999
Title:
IN-SITU METHOD FOR PREPARING AND HIGHLIGHTING OF DEFECTS FOR FAILURE ANALYSIS
23
Patent #:
6214496
Issue Dt:
04/10/2001
Application #:
09280615
Filing Dt:
03/29/1999
Title:
METHOD FOR REDUCING CORNER ROUNDING IN MASK FABRICATION UTILIZING ELLIPTICAL ENERGY BEAM
24
Patent #:
6046953
Issue Dt:
04/04/2000
Application #:
09281019
Filing Dt:
03/30/1999
Title:
DECODED AUTOREFRESH MODE IN A DRAM
25
Patent #:
6324125
Issue Dt:
11/27/2001
Application #:
09281020
Filing Dt:
03/30/1999
Title:
PULSE WIDTH DETECTION
26
Patent #:
6453433
Issue Dt:
09/17/2002
Application #:
09281021
Filing Dt:
03/30/1999
Title:
REDUCED SIGNAL TEST FOR DYNAMIC RANDOM ACCESS MEMORY
27
Patent #:
6168988
Issue Dt:
01/02/2001
Application #:
09281691
Filing Dt:
03/30/1999
Title:
METHOD FOR PRODUCING BARRIER-FREE SEMICONDUCTOR MEMORY CONFIGURATIONS
28
Patent #:
6197633
Issue Dt:
03/06/2001
Application #:
09281822
Filing Dt:
03/30/1999
Title:
METHOD FOR THE PRODUCTION OF AN INTEGRATED SEMICONDUCTOR MEMORY CONFIGURATION
29
Patent #:
6346424
Issue Dt:
02/12/2002
Application #:
09282094
Filing Dt:
03/30/1999
Title:
PROCESS FOR PRODUCING HIGH-EPSILON DIELECTRIC LAYER OR FERROELECTRIC LAYER
30
Patent #:
6297526
Issue Dt:
10/02/2001
Application #:
09282097
Filing Dt:
03/30/1999
Title:
PROCESS FOR PRODUCING BARRIER-FREE SEMICONDUCTOR MEMORY CONFIGURATIONS
31
Patent #:
6207494
Issue Dt:
03/27/2001
Application #:
09282122
Filing Dt:
03/31/1999
Title:
ISOLATION COLLAR NITRIDE LINER FOR DRAM PROCESS IMPROVEMENT
32
Patent #:
6379869
Issue Dt:
04/30/2002
Application #:
09282745
Filing Dt:
03/31/1999
Title:
METHOD OF IMPROVING THE ETCH RESISTANCE OF CHEMICALLY AMPLIFIED PHOTORESISTS BY INTRODUCING SILICON AFTER PATTERNING
33
Patent #:
6403440
Issue Dt:
06/11/2002
Application #:
09285897
Filing Dt:
04/08/1999
Title:
METHOD FOR FABRICATING A STACKED CAPACITOR IN A SEMICONDUCTOR CONFIGURATION, AND STACKED CAPACITOR FABRICATED BY THIS METHOD
34
Patent #:
6293291
Issue Dt:
09/25/2001
Application #:
09289491
Filing Dt:
04/09/1999
Title:
METHOD AND APPARATUS FOR THE TREATMENT OF OBJECTS, PREFERABLY WAFERS
35
Patent #:
6252443
Issue Dt:
06/26/2001
Application #:
09295157
Filing Dt:
04/20/1999
Title:
DELAY ELEMENT USING A DELAY LOCKED LOOP
36
Patent #:
6063543
Issue Dt:
05/16/2000
Application #:
09299364
Filing Dt:
04/26/1999
Title:
RADIATION-SENSITIVE MIXTURE AND ITS USE
37
Patent #:
6496958
Issue Dt:
12/17/2002
Application #:
09299979
Filing Dt:
04/27/1999
Title:
YIELD PREDICTION AND STATISTICAL PROCESS CONTROL USING PREDICTED DEFECT RELATED YIELD LOSS
38
Patent #:
6274431
Issue Dt:
08/14/2001
Application #:
09301108
Filing Dt:
04/28/1999
Title:
METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT ARRANGEMENT HAVING AT LEAST ONE MOS TRANSISTOR
39
Patent #:
6529028
Issue Dt:
03/04/2003
Application #:
09302649
Filing Dt:
04/30/1999
Title:
CONFIGURATION FOR TESTING A PLURALITY OF MEMORY CHIPS ON A WAFER
40
Patent #:
6117790
Issue Dt:
09/12/2000
Application #:
09302655
Filing Dt:
04/30/1999
Title:
METHOD FOR FABRICATING A CAPACITOR FOR A SEMICONDUCTOR MEMORY CONFIGURATION
41
Patent #:
6472767
Issue Dt:
10/29/2002
Application #:
09302757
Filing Dt:
04/30/1999
Title:
STATIC RANDOM ACCESS MEMORY (SRAM)
42
Patent #:
6459123
Issue Dt:
10/01/2002
Application #:
09302768
Filing Dt:
04/30/1999
Title:
DOUBLE GATED TRANSISTOR
43
Patent #:
6380015
Issue Dt:
04/30/2002
Application #:
09306617
Filing Dt:
05/06/1999
Title:
MOSFETS WITH IMPROVED SHORT CHANNEL EFFECTS AND METHOD OF MAKING THE SAME
44
Patent #:
6756820
Issue Dt:
06/29/2004
Application #:
09311118
Filing Dt:
05/13/1999
Title:
OPTIMIZED-DELAY MULTIPLEXER
45
Patent #:
6198328
Issue Dt:
03/06/2001
Application #:
09311120
Filing Dt:
05/13/1999
Title:
CIRCUIT CONFIGURATION FOR PRODUCING COMPLEMENTARY SIGNALS
46
Patent #:
6190971
Issue Dt:
02/20/2001
Application #:
09311471
Filing Dt:
05/13/1999
Title:
FORMATION OF 5F2 CELL WITH PARTIALLY VERTICAL TRANSISTOR AND GATE CONDUCTOR ALIGNED BURIED STRAP WITH RAISED SHALLOW TRENCH ISOLATION REGION
47
Patent #:
6127220
Issue Dt:
10/03/2000
Application #:
09312571
Filing Dt:
05/14/1999
Title:
MANUFACTURING METHOD FOR A CAPACITOR IN AN INTEGRATED STORAGE CIRCUIT
48
Patent #:
6204119
Issue Dt:
03/20/2001
Application #:
09312572
Filing Dt:
05/14/1999
Title:
MANUFACTURING METHOD FOR A CAPACITOR IN AN INTEGRATED MEMORY CIRCUIT
49
Patent #:
6651203
Issue Dt:
11/18/2003
Application #:
09312974
Filing Dt:
05/17/1999
Title:
ON CHIP PROGRAMMABLE DATA PATTERN GENERATOR FOR SEMICONDUCTOR MEMORIES
50
Patent #:
6357027
Issue Dt:
03/12/2002
Application #:
09313016
Filing Dt:
05/17/1999
Title:
ON CHIP DATA COMPARATOR WITH VARIABLE DATA AND COMPARE RESULT COMPRESSION
51
Patent #:
6359457
Issue Dt:
03/19/2002
Application #:
09313422
Filing Dt:
05/17/1999
Title:
METHOD OF HOLDING A WAFER AND TESTING THE INTEGRATED CIRCUITS ON THE WAFER
52
Patent #:
6958282
Issue Dt:
10/25/2005
Application #:
09313424
Filing Dt:
05/17/1999
Title:
SOI SEMICONDUCTOR CONFIGURATION AND METHOD OF FABRICATING THE SAME
53
Patent #:
6207573
Issue Dt:
03/27/2001
Application #:
09314358
Filing Dt:
05/19/1999
Title:
DIFFERENTIAL TRENCH OPEN PROCESS
54
Patent #:
6144590
Issue Dt:
11/07/2000
Application #:
09315328
Filing Dt:
05/20/1999
Title:
SEMICONDUCTOR MEMORY HAVING DIFFERENTIAL BIT LINES
55
Patent #:
6403473
Issue Dt:
06/11/2002
Application #:
09315329
Filing Dt:
05/20/1999
Title:
PROCESS FOR PRODUCING METAL-CONTAINING LAYERS
56
Patent #:
6167891
Issue Dt:
01/02/2001
Application #:
09318156
Filing Dt:
05/25/1999
Title:
TEMPERATURE CONTROLLED DEGASSIFICATION OF DEIONIZED WATER FOR MEGASONIC CLEANING OF SEMICONDUCTOR WAFERS
57
Patent #:
6215351
Issue Dt:
04/10/2001
Application #:
09321174
Filing Dt:
05/27/1999
Title:
FUSE-LATCH CIRCUIT
58
Patent #:
6292008
Issue Dt:
09/18/2001
Application #:
09322717
Filing Dt:
05/28/1999
Title:
CIRCUIT CONFIGURATION FOR BURN-IN SYSTEMS FOR TESTING MODULES BY USING A BOARD
59
Patent #:
6160747
Issue Dt:
12/12/2000
Application #:
09322718
Filing Dt:
05/28/1999
Title:
CONFIGURATION FOR CROSSTALK ATTENUATION IN WORD LINES OF DRAM CIRCUITS
60
Patent #:
6201730
Issue Dt:
03/13/2001
Application #:
09323363
Filing Dt:
06/01/1999
Title:
SENSING OF MEMORY CELL VIA A PLATELINE
61
Patent #:
6309983
Issue Dt:
10/30/2001
Application #:
09324926
Filing Dt:
06/03/1999
Title:
LOW TEMPERATURE SACRIFICIAL OXIDE FORMATION
62
Patent #:
6352893
Issue Dt:
03/05/2002
Application #:
09324927
Filing Dt:
06/03/1999
Title:
LOW TEMPERATURE SELF-ALIGNED COLLAR FORMATION
63
Patent #:
6229206
Issue Dt:
05/08/2001
Application #:
09326366
Filing Dt:
06/04/1999
Title:
BONDING PAD TEST CONFIGURATION
64
Patent #:
6218696
Issue Dt:
04/17/2001
Application #:
09326889
Filing Dt:
06/07/1999
Title:
LAYOUT AND WIRING SCHEME FOR MEMORY CELLS WITH VERTICAL TRANSISTORS
65
Patent #:
6294841
Issue Dt:
09/25/2001
Application #:
09327699
Filing Dt:
06/08/1999
Title:
INTEGRATED SEMICONDUCTOR CIRCUIT HAVING DUMMY STRUCTURES
66
Patent #:
6387771
Issue Dt:
05/14/2002
Application #:
09327711
Filing Dt:
06/08/1999
Title:
LOW TEMPERFATURE OXIDATION OF CONDUCTIVE LAYERS FOR SEMICONDUCTOR FABRICATION
67
Patent #:
6426254
Issue Dt:
07/30/2002
Application #:
09328763
Filing Dt:
06/09/1999
Title:
METHOD FOR EXPANDING TRENCHES BY AN ANISOTROPIC WET ETCH
68
Patent #:
6379222
Issue Dt:
04/30/2002
Application #:
09333228
Filing Dt:
06/14/1999
Publication #:
US20010046831
Pub Dt:
11/29/2001
Title:
IMPROVED METHODS AND APPARATUS FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OF A SEMICONDUCTOR WAFER
69
Patent #:
6081479
Issue Dt:
06/27/2000
Application #:
09333539
Filing Dt:
06/15/1999
Title:
HIERARCHICAL PREFETCH FOR SEMICONDUCTOR MEMORIES
70
Patent #:
6258153
Issue Dt:
07/10/2001
Application #:
09335561
Filing Dt:
06/18/1999
Title:
DEVICE FOR THE DEPOSITION OF SUBSTANCES
71
Patent #:
6194278
Issue Dt:
02/27/2001
Application #:
09337168
Filing Dt:
06/21/1999
Title:
DEVICE PERFORMANCE BY EMPLOYING AN IMPROVED METHOD FOR FORMING HALO IMPLANTS
72
Patent #:
6368516
Issue Dt:
04/09/2002
Application #:
09339519
Filing Dt:
06/24/1999
Title:
SEMICONDUCTOR MANUFACTURING METHODS
73
Patent #:
6175531
Issue Dt:
01/16/2001
Application #:
09343429
Filing Dt:
06/30/1999
Title:
DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INITIALIZING A DYNAMIC SEMICONDUCTOR MEMORY DEVICE
74
Patent #:
6157589
Issue Dt:
12/05/2000
Application #:
09343431
Filing Dt:
06/30/1999
Title:
DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INTIALIZING A DYNAMIC SEMICONDUCTOR MEMORY DEVICE
75
Patent #:
6101141
Issue Dt:
08/08/2000
Application #:
09344922
Filing Dt:
06/28/1999
Title:
INTEGRATED MEMORY
76
Patent #:
6130549
Issue Dt:
10/10/2000
Application #:
09346379
Filing Dt:
07/01/1999
Title:
OUTPUT DRIVER OF AN INTEGRATED SEMICONDUCTOR CHIP
77
Patent #:
6557130
Issue Dt:
04/29/2003
Application #:
09352992
Filing Dt:
07/14/1999
Title:
CONFIGURATION AND METHOD FOR STORING THE TEST RESULTS OBTAINED BY A BIST CIRCUIT
78
Patent #:
6366110
Issue Dt:
04/02/2002
Application #:
09353612
Filing Dt:
07/14/1999
Title:
CONFIGURATION FOR TESTING CHIPS
79
Patent #:
6190964
Issue Dt:
02/20/2001
Application #:
09356402
Filing Dt:
07/16/1999
Title:
METHOD OF PRODUCING A STACKED CAPACITOR
80
Patent #:
6133779
Issue Dt:
10/17/2000
Application #:
09356811
Filing Dt:
07/19/1999
Title:
INTEGRATED CIRCUIT WITH A VOLTAGE REGULATOR
81
Patent #:
6675322
Issue Dt:
01/06/2004
Application #:
09356813
Filing Dt:
07/19/1999
Title:
INTEGRATED CIRCUIT HAVING A SELF-TEST DEVICE
82
Patent #:
6278285
Issue Dt:
08/21/2001
Application #:
09356955
Filing Dt:
07/19/1999
Title:
CONFIGURATION FOR TESTING INTEGRATED COMPONENTS
83
Patent #:
6501131
Issue Dt:
12/31/2002
Application #:
09359291
Filing Dt:
07/22/1999
Title:
TRANSISTORS HAVING INDEPENDENTLY ADJUSTABLE PARAMETERS
84
Patent #:
6320215
Issue Dt:
11/20/2001
Application #:
09359292
Filing Dt:
07/22/1999
Title:
CRYSTAL-AXIS-ALIGNED VERTICAL SIDE WALL DEVICE
85
Patent #:
6656376
Issue Dt:
12/02/2003
Application #:
09360944
Filing Dt:
07/26/1999
Title:
PROCESS FOR CLEANING CVD UNITS
86
Patent #:
6262476
Issue Dt:
07/17/2001
Application #:
09360973
Filing Dt:
07/27/1999
Title:
COMPOSITE MEMBER COMPOSED OF AT LEAST TWO INTEGRATED CIRCUITS AND METHOD FOR THE MANUFACTURE OF A COMPOSITE MEMBER COMPOSED OF AT LEAST TWO INTEGRATED CIRCUITS
87
Patent #:
6307263
Issue Dt:
10/23/2001
Application #:
09363263
Filing Dt:
07/29/1999
Title:
INTEGRATED SEMICONDUCTOR CHIP WITH MODULAR DUMMY STRUCTURES
88
Patent #:
6828191
Issue Dt:
12/07/2004
Application #:
09363277
Filing Dt:
07/28/1999
Title:
TRENCH CAPACITOR WITH AN INSULATION COLLAR AND METHOD FOR PRODUCING A TRENCH CAPACITOR
89
Patent #:
6415406
Issue Dt:
07/02/2002
Application #:
09368134
Filing Dt:
08/04/1999
Title:
INTEGRATED CIRCUIT HAVING A SELF-TEST DEVICE AND METHOD FOR PRODUCING THE INTEGRATED CIRCUIT
90
Patent #:
6313656
Issue Dt:
11/06/2001
Application #:
09372307
Filing Dt:
08/11/1999
Title:
METHOD OF TESTING LEAKAGE CURRENT AT A CONTACT-MAKING POINT IN AN INTEGRATED CIRCUIT BY DETERMINING A POTENTIAL AT THE CONTACT-MAKING POINT
91
Patent #:
6285621
Issue Dt:
09/04/2001
Application #:
09373476
Filing Dt:
08/12/1999
Title:
METHOD OF MINIMIZING THE ACCESS TIME IN SEMICONDUCTOR MEMORIES
92
Patent #:
6355520
Issue Dt:
03/12/2002
Application #:
09374537
Filing Dt:
08/16/1999
Title:
METHOD FOR FABRICATING 4F2 MEMORY CELLS WITH IMPROVED GATE CONDUCTOR STRUCTURE
93
Patent #:
6294436
Issue Dt:
09/25/2001
Application #:
09374538
Filing Dt:
08/16/1999
Title:
METHOD FOR FABRICATION OF ENLARGED STACKED CAPACITORS USING ISOTROPIC ETCHING
94
Patent #:
6153902
Issue Dt:
11/28/2000
Application #:
09374687
Filing Dt:
08/16/1999
Title:
VERTICAL DRAM CELL WITH WORDLINE SELF-ALIGNED TO STORAGE TRENCH
95
Patent #:
6627496
Issue Dt:
09/30/2003
Application #:
09374893
Filing Dt:
08/13/1999
Title:
PROCESS FOR PRODUCING STRUCTURED LAYERS, PROCESS FOR PRODUCING COMPONENTS OF AN INTEGRATED CIRCUIT, AND PROCESS FOR PRODUCING A MEMORY CONFIGURATION
96
Patent #:
6081469
Issue Dt:
06/27/2000
Application #:
09374894
Filing Dt:
08/13/1999
Title:
COMBINED PRECHARGING AND HOMOGENIZING CIRCUIT
97
Patent #:
6376913
Issue Dt:
04/23/2002
Application #:
09374895
Filing Dt:
08/13/1999
Title:
INTEGRATED SEMICONDUCTOR CHIP HAVING LEADS TO ONE OR MORE EXTERNAL TERMINALS
98
Patent #:
6668031
Issue Dt:
12/23/2003
Application #:
09377588
Filing Dt:
08/19/1999
Title:
SYNCHRONIZED DATA CAPTURING CIRCUITS USING REDUCED VOLTAGE LEVELS AND METHODS THEREFOR
99
Patent #:
6107177
Issue Dt:
08/22/2000
Application #:
09382933
Filing Dt:
08/25/1999
Title:
SILYLATION METHOD FOR REDUCING CRITICAL DIMENSION LOSS AND RESIST LOSS
100
Patent #:
6352934
Issue Dt:
03/05/2002
Application #:
09383666
Filing Dt:
08/26/1999
Title:
SIDEWALL OXIDE PROCESS FOR IMPROVED SHALLOW JUNCTION FORMATION IN SUPPORT REGION
Assignor
1
QIMONDA AG
Exec Dt:
10/09/2014
Assignee
1
INFINEON TECHNOLOGIES AG
AM CAMPEON 1-12
NEUBIBERG, GERMANY 85579
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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