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02/13/2001
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09384701
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08/27/1999
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08/01/2000
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09388274
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09/01/1999
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03/06/2001
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09390496
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09/03/1999
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09/26/2000
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09391717
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09/08/1999
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01/08/2002
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09391720
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09/08/1999
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09/05/2000
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09/07/1999
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03/12/2002
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09394196
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09/10/1999
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05/08/2001
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09395005
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09/13/1999
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07/10/2001
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09395316
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09/13/1999
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CAPACITOR WITH HIGH-E DIELECTRIC OR FERROELECTRIC MATERIAL BASED ON THE FIN STACK PRINCIPLE AND PRODUCTION PROCESS USING A NEGATIVE MOLD
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12/05/2000
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09395320
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09/13/1999
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METHOD OF TESTING AN INTEGRATED CIRCUIT HAVING A MEMORY AND A TEST CIRCUIT
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05/22/2001
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09395952
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09/14/1999
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PROCESS FOR IMPROVING THE THICKNESS UNIFORMITY OF A THIN LAYER IN SEMICONCUCTOR WAFER FABRICATION
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04/15/2003
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09/14/1999
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12/20/2001
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METHOD OF PLASMA ETCHING THIN FILMS OF DIFFICULT TO DRY ETCH MATERIALS
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01/30/2001
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09398695
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09/20/1999
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INTEGRATED CIRCUIT MEMORY HAVING A SENSE AMPLIFIER ACTIVATED BASED ON WORD LINE POTENTIALS
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08/21/2001
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09401022
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09/21/1999
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INTEGRATED CIRCUIT
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11/20/2001
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09401387
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09/22/1999
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METHOD FOR DETERMINING THE DRIVE CAPABILITY OF A DRIVER CIRCUIT OF AN INTEGRATED CIRCUIT
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01/23/2001
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09401388
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09/22/1999
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INTEGRATED MEMORY HAVING A SELF-REPAIR FUNCTION
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07/31/2001
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09/22/1999
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BURN-IN TEST DEVICE
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08/14/2001
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09405916
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09/24/1999
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MEMORY CELL CONFIGURATION AND PRODUCTION PROCESS THEREFOR
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12/04/2001
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09406890
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09/28/1999
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REDUCING IMPACT OF COUPLING NOISE IN MULTI-LEVEL BIELINE ARCHITECTURE
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11/20/2001
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09406892
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09/28/1999
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REDUCED IMPACT FROM COUPLING NOISE IN DIAGONAL BITLINE ARCHITECTURES
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06/12/2001
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09407263
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09/27/1999
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METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
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04/11/2000
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09407384
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09/28/1999
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GAPFILL OF SEMICONDUCTOR STRUCTURE USING DOPED SILICATE GLASSES
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09/12/2000
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09407437
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09/29/1999
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DYNAMIC RANDOM ACCESS MEMORY CELL LAYOUT
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07/08/2003
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09408246
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09/29/1999
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SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
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05/25/2004
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09/29/1999
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SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
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02/13/2001
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09408476
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09/28/1999
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INTEGRATED CIRCUIT HAVING A CONTACT-MAKING POINT FOR SELECTING AN OPERATING MODE OF THE INTEGRATED CIRCUIT
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05/13/2003
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09408477
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09/28/1999
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METHOD FOR INSTALLING PROTECTIVE COMPONENTS IN INTEGRATED CIRCUITS THAT ARE CONSTRUCTED FROM STANDARD CELLS
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07/18/2000
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09408479
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09/28/1999
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FERROELECTRIC MEMORY AND METHOD FOR PREVENTING AGING IN A MEMORY CELL
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12/12/2000
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09408677
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09/30/1999
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INTEGRATED CIRCUIT WITH A CONFIGURATION ASSEMBLY
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02/20/2001
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09408685
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09/30/1999
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INTEGRATED CIRCUIT HAVING ADJUSTABLE DELAY UNITS FOR CLOCK SIGNALS
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02/27/2001
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09408687
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09/30/1999
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INTEGRATED CIRCUIT WITH ADJUSTABLE DELAY UNIT
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04/06/2004
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09408688
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09/30/1999
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VERTICAL FIELD EFFECT TRANSISTOR WITH INTERNAL ANNULAR GATE AND METHOD OF PRODUCTION
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09/18/2001
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09411551
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10/04/1999
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LOCALLY FOLDED SPLIT LEVEL BITLINE WIRING
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10/24/2000
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09413265
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10/06/1999
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IMPROVED METAL LINE DEPOSITION PROCESS
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07/17/2001
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09420402
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10/18/1999
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SELF-ALIGNED METAL CAPS FOR INTERLEVEL METAL CONNECTIONS
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02/11/2003
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09423864
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11/15/1999
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INTEGRATED CMOS CIRCUIT CONFIGURATION, AND PRODUCTION OF SAME
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03/04/2003
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09425329
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10/22/1999
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PREFETCH ARCHITECTURES FOR DATA AND TIME SIGNALS IN AN INTEGRATED CIRCUIT AND METHODS THEREFOR
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01/14/2003
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09428582
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10/28/1999
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METHOD AND AN APPARATUS FOR TREATING WASTEWATER FROM A CHEMICAL-MECHANICAL POLISHING PROCESS USED IN CHIP FABRICATION
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05/14/2002
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09429834
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10/29/1999
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METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT WITH LOW THRESHOLD VOLTAGE DIFFERENCES OF THE TRANISTORS THEREIN
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03/25/2003
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09431529
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11/01/1999
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READ/WRITE MEMORY WITH SELF-TEST DEVICE AND ASSOCIATED TEST METHOD
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03/27/2001
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09432063
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11/02/1999
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SPACER PROCESS TO ELIMINATE CORNER TRANSISTOR DEVICE
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04/20/2004
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09432064
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11/02/1999
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EFFICIENT REDUNDANCY CALCULATION SYSTEM AND METHOD FOR VARIOUS TYPES OF MEMORY DEVICES
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09/02/2003
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11/10/1999
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SEMICONDUCTOR CHIP CONFIGURATION AND METHOD OF CONTROLLING A SEMICONDUCTOR CHIP
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04/16/2002
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09438305
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09/13/1999
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BACKING FILM FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OF A SEMICONDUCTOR WAFER
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02/25/2003
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09439253
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11/12/1999
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METHODS AND APPARATUS FOR REORDERING OF THE MEMORY REQUESTS TO ACHIEVE HIGHER AVERAGE UTILIZATION OF THE COMMAND AND DATA BUS
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04/23/2002
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09439254
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11/12/1999
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UNIVERSAL MEMORY CONTROLLER
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04/10/2001
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09439276
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11/12/1999
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METHODS AND APPARATUS FOR DETECTING THE COLLISION OF DATA ON A DATA BUS IN CASE OF OUT-OF-ORDER MEMORY ACCESSES OF DIFFERENT TIMES OF MEMORY ACCESS EXECUTION
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03/11/2003
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09439544
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11/12/1999
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UNIVERSAL RESOURCE ACCESS CONTROLLER
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09/04/2001
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09439715
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11/12/1999
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METHOD OF SPEEDING UP ACCESS TO A MEMORY PAGE USING A NUMBER OF M PAGE TAG REGISTERS TO TRACK A STATE OF PHYSICAL PAGES IN A MEMORY DEVICE HAVING N MEMORY BANKS WHERE N IS GREATER THAN M
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03/25/2003
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09439867
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11/12/1999
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METHODS AND APPARATUS FOR PREDICTION OF THE TIME BETWEEN TWO CONSECUTIVE MEMORY ACCESSES
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10/02/2001
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09440721
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11/15/1999
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CIRCUIT CONFIGURATION WITH A TEMPERATURE-DEPENDENT SEMICONDUCTOR COMPONENT TEST AND REPAIR LOGIC CIRCUIT
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10/24/2000
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09440818
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11/15/1999
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FERROELECTRIC MEMORY CONFIGURATION
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05/15/2001
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09442890
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11/18/1999
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OPTIMIZED DECOUPLING CAPACITOR USING LITHOGRAPHIC DUMMY FILLER
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09/04/2001
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09442982
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11/18/1999
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MEMORY CELL
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03/19/2002
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09443751
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11/19/1999
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MAGNETIC MEMORY
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11/27/2001
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09449716
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11/24/1999
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SEMICONDUCTOR COMPONENT HAVING AT LEAST ONE CAPACITOR AND METHODS FOR FABRICATING IT
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10/24/2000
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09450403
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11/29/1999
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INPUT CIRCUIT FOR AN INTEGRATED CIRCUIT
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06/11/2002
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09455118
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12/06/1999
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01/03/2002
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FUSE LATCH HAVING MULTIPLEXERS WITH REDUCED SIZES AND LOWER POWER CONSUMPTION
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05/13/2003
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09455855
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12/07/1999
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ADVANCED BIT FAIL MAP COMPRESSION WITH FAIL SIGNATURE ANALYSIS
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05/29/2001
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09456588
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12/08/1999
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SDRAM WITH A MASKABLE INPUT
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05/22/2001
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09458878
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12/10/1999
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HIGH PERFORMANCE CMOS WORD-LINE DRIVER
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03/26/2002
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09460318
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12/14/1999
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SELF-ALIGNED LDD FORMATION WITH ONE-STEP IMPLANTATION FOR TRANSISTOR FORMATION
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07/05/2005
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01/14/2000
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INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR THE MANUFACTURE THEREOF
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08/21/2001
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09465726
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12/17/1999
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CONFIGURATION OF MEMORY CELLS AND METHOD OF CHECKING THE OPERATION OF MEMORY CELLS
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09/25/2001
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09469922
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12/22/1999
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SLURRY-LESS CHEMICAL-MECHANICAL POLISHING
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07/03/2001
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09470310
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12/22/1999
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INTEGRATED CIRCUIT HAVING A DECODER
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10/30/2001
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09472221
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12/27/1999
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SEMICONDUCTOR CIRCUIT APPARATUS AND METHOD FOR FABRICATING THE SEMICONDUCTOR CIRCUIT APPARATUS
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08/13/2002
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09476449
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12/30/1999
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AUTOMATED CREATION OF SPECIFIC TEST PROGRAMS FROM COMPLEX TEST PROGRAMS
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12/24/2002
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09476450
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12/30/1999
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Title:
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USAGE OF REDUNDANCY DATA FOR DISPLAYING FAILURE BIT MAPS FOR SEMICONDUCTOR DEVICES
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01/01/2002
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09476726
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12/30/1999
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METHOD FOR MAKING AN ANTI-FUSE
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|
03/27/2001
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Application #:
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09478270
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Filing Dt:
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01/05/2000
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Title:
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HIGH DIELECTRIC CONSTANT MATERIAL DEPOSITION TO ACHIEVE HIGH CAPACITANCE
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09478312
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Filing Dt:
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01/06/2000
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Title:
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STACK CAPACITOR WITH IMPROVED PLUG CUNDUCTIVITY
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09481637
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Filing Dt:
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01/12/2000
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Title:
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PROCESS FOR PRODUCING ULTRA-PURE WATER, AND CONFIGURATION FOR CARRYING OUT A PROCESS OF THIS NATURE
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09481639
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Filing Dt:
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01/12/2000
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Title:
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CONVEYING SYSTEM
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09481769
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Filing Dt:
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01/11/2000
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Title:
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UNIFORM RECESS DEPTH OF RECESSED RESIST LAYERS IN TRENCH STRUCTURE
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09481770
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Filing Dt:
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01/11/2000
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Title:
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METHOD FOR DETECTING AND CLASSIFYING SCRATCHES OCCURING DURING WAFER SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
|
03/05/2002
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Application #:
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09482064
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Filing Dt:
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01/13/2000
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Title:
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METHOD OF FORMING DRAM CELL ARRANGEMENT
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09483738
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Filing Dt:
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01/14/2000
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Title:
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Mehtod for repairing defective memory cells of an integrated semiconductor memory
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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09484781
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Filing Dt:
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01/18/2000
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT AND METHOD FOR FUNCTIONAL TESTING OF PAD CELLS
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Patent #:
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Issue Dt:
|
01/08/2002
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Application #:
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09487411
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Filing Dt:
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01/18/2000
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Title:
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Method of producing a vertical mos transistor
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09489771
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Filing Dt:
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01/21/2000
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Title:
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Method to prevent oxygen Out-Diffusion from BSTO containing Micro-Electronic device
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09489865
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Filing Dt:
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01/21/2000
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Title:
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Maskless process for self-aligned contacts
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09491296
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Filing Dt:
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01/25/2000
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Title:
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POLISHING AGENT FOR SEMICONDUCTOR SUBSTRATES
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09491408
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Filing Dt:
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01/26/2000
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Title:
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TECHNIQUES FOR IMPROVING MEMORY ACCESS IN A VIRTUAL MEMORY SYSTEM
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09491635
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Filing Dt:
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01/27/2000
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Title:
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Full swing voltage input/full swing output bi-directional repeaters for high resistance or high capacitance bi-directional signal lines and methods therefor
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|
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Patent #:
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Issue Dt:
|
03/19/2002
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Application #:
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09491645
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Filing Dt:
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01/27/2000
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Title:
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Mixed swing voltage repeaters for high resistance or high capacitance signal lines and methods therefor
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Patent #:
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Issue Dt:
|
10/29/2002
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Application #:
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09492541
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Filing Dt:
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01/27/2000
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Title:
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PLANARIZATION PROCESS TO ACHIEVE IMPROVED UNIFORMITY ACROSS SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
|
01/08/2002
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Application #:
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09492654
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Filing Dt:
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01/27/2000
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Title:
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Method for improving the quality of metal conductor tracks on semiconductor structures
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Patent #:
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Issue Dt:
|
09/24/2002
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Application #:
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09492655
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Filing Dt:
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01/27/2000
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Title:
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METHOD FOR PRODUCING STRUCTURES ON THE SURFACE OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09492656
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Filing Dt:
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01/27/2000
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Title:
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Method for improving the readability of alignment marks
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Patent #:
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Issue Dt:
|
07/03/2001
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Application #:
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09494774
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Filing Dt:
|
01/31/2000
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Title:
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Method for fabricating an isolation trench using an auxiliary layer
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Patent #:
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Issue Dt:
|
10/16/2001
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Application #:
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09494775
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Filing Dt:
|
01/31/2000
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Title:
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READ-ONLY MEMORY AND FABRICATION METHOD
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Patent #:
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Issue Dt:
|
07/17/2001
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Application #:
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09495795
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Filing Dt:
|
02/01/2000
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Title:
|
Wafer marking
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Patent #:
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Issue Dt:
|
05/28/2002
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Application #:
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09498532
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Filing Dt:
|
02/04/2000
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Title:
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Integrated electrical circuit with passivation layer
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Patent #:
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Issue Dt:
|
07/17/2001
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Application #:
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09501479
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Filing Dt:
|
02/09/2000
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Title:
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Easy to remove hard mask layer for semiconductor device fabrication
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Patent #:
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|
Issue Dt:
|
03/19/2002
|
Application #:
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09503992
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Filing Dt:
|
02/14/2000
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|
Title:
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Apparatus and method for forming controlled deep trench top isolation layers
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|
|
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Patent #:
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|
Issue Dt:
|
09/03/2002
|
Application #:
|
09504274
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Filing Dt:
|
02/15/2000
|
|
Title:
|
EXHAUST APPARATUS
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|
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|
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Patent #:
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|
Issue Dt:
|
10/30/2001
|
Application #:
|
09504275
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Filing Dt:
|
02/15/2000
|
|
Title:
|
Electrical test structure on a semiconductor substrate and test method
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/11/2001
|
Application #:
|
09504409
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Filing Dt:
|
02/15/2000
|
|
Title:
|
Method for probing semiconductor devices for active measuring of electrical characteristics
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/13/2001
|
Application #:
|
09505379
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Filing Dt:
|
02/16/2000
|
|
Title:
|
SEMICONDUCTOR MEMORY HAVING MEMORY BANK DECODERS DISPOSED SYMMETRICALLY ON A CHIP
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|
