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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09617649
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Filing Dt:
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07/17/2000
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Title:
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Synchronous integrated memory
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09617652
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Filing Dt:
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07/17/2000
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Title:
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Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09618124
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Filing Dt:
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07/17/2000
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Title:
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Integrated memory
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09619075
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Filing Dt:
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07/17/2000
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Title:
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Automated bad socket masking in real-time for test handlers
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09621430
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Filing Dt:
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07/21/2000
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT WITH AN INCREASED OPERATING VOLTAGE
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09621433
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Filing Dt:
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07/21/2000
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Title:
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Method for fabricating stacked vias
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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09621905
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Filing Dt:
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07/24/2000
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Title:
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SYNCHRONOUS INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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04/15/2003
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09630972
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Filing Dt:
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08/02/2000
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Title:
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ARRANGEMENT AND METHOD FOR TESTING A MULTIPLICITY OF SEMICONDUCTOR CHIPS AT THE WAFER LEVEL
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09633704
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Filing Dt:
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08/07/2000
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Title:
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CONTACT CONNECTION OF METAL INTERCONNECTS OF AN INTEGRATED SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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09/02/2003
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09636521
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Filing Dt:
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08/10/2000
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Title:
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OPTICAL STRUCTURE AND METHOD FOR PRODUCING THE SAME
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09636522
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Filing Dt:
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08/10/2000
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Title:
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METHOD FOR FABRICATING A MICROTECHNICAL STRUCTURE
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Patent #:
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Issue Dt:
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03/25/2003
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09638309
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Filing Dt:
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08/14/2000
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Title:
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PROCESS FOR IMPROVING THE THICKNESS UNIFORMITY OF A THIN OXIDE LAYER IN SEMICONDUCTOR WAFER FABRICATION
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09638722
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Filing Dt:
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08/10/2000
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Title:
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Wiring through terminal via fuse
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Patent #:
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Issue Dt:
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07/16/2002
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09638725
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Filing Dt:
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08/14/2000
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Title:
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RETAINING RING FOR CHEMICAL-MECHANICAL POLISHING (CMP) HEAD, POLISHING APPARATUS, SLURRY CYCLE SYSTEM, AND METHOD
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02/03/2004
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09639986
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Filing Dt:
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08/16/2000
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Title:
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CMP UNIFORMITY
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Patent #:
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Issue Dt:
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05/21/2002
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09641143
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Filing Dt:
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08/17/2000
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Title:
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WAFER CONTAINER HAVING ELECTRICALLY CONDUCTIVE KINEMATIC COUPLING GROOVE, SUPPORT SURFACE WITH ELECTRICALLY CONDUCTIVE KINEMATIC COUPLING PIN, TRANSPORTATION SYSTEM, AND METHOD
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05/21/2002
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09641153
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Filing Dt:
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08/17/2000
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Title:
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WAFER CONTAINER HAVING ELECTRICALLY CONDUCTIVE KINEMATIC COUPLING GROOVE TO DETECT THE PRESENCE OF THE WAFER CONTAINER ON A SUPPORT SURFACE, THE SUPPORT SURFACE, AND METHOD
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Issue Dt:
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04/09/2002
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09642325
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Filing Dt:
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08/21/2000
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Title:
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Method for fabricating a microelectronic structure
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09642326
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Filing Dt:
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08/21/2000
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Title:
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CONFIGURATION AND METHOD FOR PRODUCING TEST SIGNALS FOR TESTING A MULTIPLICITY OF SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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11/13/2001
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09642328
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Filing Dt:
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08/21/2000
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Title:
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METHOD FOR FABRICATING A MEMORY CELL HAVING A MOS TRANSISTOR
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09642734
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Filing Dt:
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08/17/2000
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Title:
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Test circuit for testing a digital semiconductor circuit configuration
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09645424
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Filing Dt:
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08/24/2000
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Title:
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DISPOSABLE SPACER TECHNOLOGY FOR DEVICE TAILORING
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Issue Dt:
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08/20/2002
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09645765
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Filing Dt:
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08/25/2000
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Title:
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METHOD OF FABRICATING INTEGRATED CIRCUITS HAVING TRANSISTORS AND FURTHER SEMICONDUCTOR ELEMENTS
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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09648939
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Filing Dt:
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08/28/2000
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Title:
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METHOD FOR GENERATING A SEQUENCE OF RANDOM NUMBER OF A 1/F- NOSE
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Issue Dt:
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12/04/2001
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Application #:
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09651492
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Filing Dt:
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08/30/2000
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Title:
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Epitaxy layer and method for its production
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09655461
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09/05/2000
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Title:
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CHIP CRACK STOP DESIGN FOR SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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10/07/2003
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09655603
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Filing Dt:
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09/05/2000
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Title:
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MODULARLY EXPANDABLE MULT-LAYERED SEMICONDUCTOR COMPONENT
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Issue Dt:
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05/11/2004
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09658152
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09/08/2000
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Title:
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CONVEYING ELEMENT AND CONVEYOR MEANS FOR CONVEYING WAFER RECEPTACLES, AND METHOD
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Issue Dt:
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06/18/2002
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09658713
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Filing Dt:
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09/11/2000
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Title:
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METHOD FOR PRODUCING AN ELECTRICAL CONNECTION BETWEEN THE FRONT AND REAR SIDES OF SEMICONDUCTOR CHIPS
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02/08/2005
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09659872
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09/13/2000
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Title:
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LEVEL-SHIFTING CIRCUITRY HAVING "HIGH" OUTPUT IMPEDANCE DURING DISABLE MODE
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Issue Dt:
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04/30/2002
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Application #:
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09659946
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Filing Dt:
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09/13/2000
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Title:
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Combined tracking of wll and vpp with low threshold voltage in dram array
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09660453
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Filing Dt:
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09/12/2000
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Title:
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DRAM CELL ARRANGEMENT AND METHOD FOR FABRICATING IT
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Patent #:
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Issue Dt:
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11/08/2005
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09660703
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09/13/2000
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Title:
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METHOD AND APPARATUS FOR FAST AUTOMATED FAILURE CLASSIFICATION FOR SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09662255
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09/14/2000
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Title:
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Integrated memory with two burst operation types
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09662256
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Filing Dt:
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09/14/2000
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Title:
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Integrated memory having memory cells and reference cells
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09662257
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Filing Dt:
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09/14/2000
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Title:
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Integrated memory with at least two plate segments
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09662424
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Filing Dt:
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09/14/2000
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Title:
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SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION INCLUDING FORMING ALUMINUM COLUMNS
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09662691
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Filing Dt:
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09/14/2000
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Title:
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SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09662957
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09/15/2000
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Title:
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INPUT BUFFER OF AN INTEGRATED SEMICONDUCTOR CIRCUIT
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09663569
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Filing Dt:
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09/15/2000
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Title:
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PATTERNING OF CONTACT AREAS IN MULTILAYER METALIZATION CONFIGURATIONS OF SEMICONDUCTOR COMPONENTS
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09663583
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Filing Dt:
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09/18/2000
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Title:
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Segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit lines
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Issue Dt:
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03/16/2004
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Application #:
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09664825
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Filing Dt:
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09/19/2000
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Title:
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CONTROL OF SEPARATION BETWEEN TRANSFER GATE AND STORAGE NODE IN VERTICAL DRAM
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09664826
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Filing Dt:
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09/19/2000
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Title:
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LEVEL-SHIFTING CIRCUITRY HAVING "LOW" OUTPUT DURING DISABLE MODE
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09666526
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Filing Dt:
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09/18/2000
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Title:
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DEPOSITION OF VARIOUS BASE LAYERS FOR SELECTIVE LAYER GROWTH IN SEMICONDUCTOR PRODUCTION
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09667053
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Filing Dt:
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09/21/2000
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Title:
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DUAL THICKNESS GATE OXIDE FABRICATION METHOD USING PLASMA SURFACE TREATMENT
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09668485
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09/25/2000
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Title:
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Memory cell configuration and method for fabricating it
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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09669585
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Filing Dt:
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09/26/2000
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Title:
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TRENCH CAPACITOR MEMORY CELL
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09670741
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09/27/2000
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PROCESS FOR PROTECTING ARRAY TOP OXIDE
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Issue Dt:
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01/07/2003
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Application #:
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09670742
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Filing Dt:
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09/27/2000
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Title:
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DOUBLE GATED TRANSISTOR
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09670745
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Filing Dt:
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09/27/2000
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Title:
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SELF-ALIGNED BURIED STRAP FOR VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09671452
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Filing Dt:
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09/27/2000
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Title:
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CONFIGURATION FOR VOLTAGE BUFFERING IN A DYNAMIC MEMORY USING CMOS TECHNOLOGY
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09671915
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Filing Dt:
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09/28/2000
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Title:
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LEVEL-SHIFTING CIRCUITRY HAVING "HIGH" OUTPUT DURING DISABLE MODE
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09672625
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Filing Dt:
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09/28/2000
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Title:
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CONFIGURATION FOR REDUCING THE NUMBER OF MEASURING PADS ON A SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09675246
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Filing Dt:
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09/29/2000
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Title:
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SEMICONDUCTOR FUSES AND ANTIFUSES IN VERTICAL DRAMS
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09675432
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Filing Dt:
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09/29/2000
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Title:
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INTEGRATED CIRCUIT COMPRISING A SELF ALIGNED TRENCH, AND METHOD OF FORMING THEREOF
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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09675435
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Filing Dt:
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09/29/2000
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Title:
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EXTENDIBLE PROCESS FOR IMPROVED TOP OXIDE LAYER FOR DRAM ARRAY AND THE GATE INTERCONNECTS WHILE PROVIDING SELF-ALIGNED GATE CONTACTS
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Issue Dt:
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07/29/2003
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Application #:
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09675953
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Filing Dt:
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09/29/2000
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Title:
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METHOD TO DESCRAMBLE THE DATA MAPPING IN MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09676864
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Filing Dt:
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09/29/2000
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Title:
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BUFFERS WITH REDUCED VOLTAGE INPUT/OUTPUT SIGNALS
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09677324
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Filing Dt:
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09/29/2000
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Title:
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TRENCH CAPACITOR CONFIGURATION AND METHOD OF PRODUCING IT
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09677357
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Filing Dt:
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10/02/2000
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Title:
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Integrated dynamic semiconductor memory having redundant units of memory cells, and a method for self-repair
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Patent #:
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Issue Dt:
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12/10/2002
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09677368
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Filing Dt:
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01/08/2001
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Title:
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DRAM INCLUDING AN ADDRESS SPACE DIVIDED INTO INDIVIDUAL BLOCKS HAVING MEMORY CELLS ACTIVATED BY ROW ADDRESS SIGNALS
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Issue Dt:
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02/25/2003
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Application #:
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09677433
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Filing Dt:
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10/02/2000
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Title:
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INTEGRATED CIRCUIT CONFIGURATION WITH AT LEAST ONE CAPACITOR AND METHOD FOR PRODUCING THE SAME
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Issue Dt:
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04/01/2003
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Application #:
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09680736
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Filing Dt:
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10/06/2000
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Title:
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METHOD OF POSITIONING A COMPONENT MOUNTED ON A LEAD FRAME IN A TEST SOCKET
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Patent #:
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Issue Dt:
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12/04/2007
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09680923
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10/06/2000
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Title:
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SYSTEM AND METHOD FOR MANAGING RISK AND OPPORTUNITY
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Issue Dt:
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12/10/2002
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Application #:
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09685659
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10/10/2000
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Title:
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CONFIGURATION AND METHOD FOR CONNECTING CONDUCTOR TRACKS
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Issue Dt:
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06/04/2002
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Application #:
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09687883
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Filing Dt:
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10/13/2000
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Title:
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PULSE WIDTH DETECTION
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09690298
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Filing Dt:
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10/17/2000
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Title:
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MEMORY CONFIGURATION HAVING REDUNDANT MEMORY LOCATIONS AND METHOD FOR ACCESSING REDUNDANT MEMORY LOCATIONS
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Issue Dt:
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07/30/2002
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Application #:
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09691953
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Filing Dt:
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10/19/2000
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Title:
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AREA EFFICIENT METHOD FOR PROGRAMMING ELECTRICAL FUSES
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Patent #:
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03/26/2002
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Application #:
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09692118
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10/19/2000
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Title:
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Dram cell circuit
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Issue Dt:
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03/05/2002
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Application #:
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09693769
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Filing Dt:
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10/20/2000
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Title:
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controlling transistor threshold potentials using substrate potentials
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Issue Dt:
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09/04/2001
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Application #:
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09693778
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Filing Dt:
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10/20/2000
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Title:
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Voltage generator with superimposed reference voltage and deactivation signal
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Issue Dt:
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09/25/2001
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Application #:
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09699982
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Filing Dt:
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10/30/2000
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Title:
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Integrated memory
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|
|
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09699983
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Filing Dt:
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10/30/2000
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Title:
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Integrated memory having cells of the two-transistor/two-capacitor type
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09702311
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Filing Dt:
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10/31/2000
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Title:
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SLURRY-LESS CHEMICAL-MECHANICAL POLISHING
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09705599
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Filing Dt:
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11/03/2000
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Title:
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NEEDLE-CARD ADJUSTING DEVICE FOR PLANARIZING NEEDLE SETS ON A NEEDLE CARD
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09706641
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Filing Dt:
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11/06/2000
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Title:
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Dual gate oxide process for uniform oxide thickness
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09708279
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Filing Dt:
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11/08/2000
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Title:
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SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09711864
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Filing Dt:
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11/13/2000
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Title:
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Memory device
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Patent #:
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Issue Dt:
|
07/01/2003
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Application #:
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09712993
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Filing Dt:
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11/14/2000
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Title:
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APPARATUS FOR DETECTIND DATA COLLISION ON DATA BUS FOR OUT-OF-ORDER MEMORY ACCESSES WITH ACCESS EXECUTION TIME BASED IN PART ON CHARACTERIZATION DATA SPECIFIC TO MEMORY
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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09714356
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Filing Dt:
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11/16/2000
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Title:
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NITROGEN IMPLANTATION USING A SHADOW EFFECT TO CONTROL GATE OXIDE THICKNESS IN DRAM SEMICONDUCTOR
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09716336
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Filing Dt:
|
11/20/2000
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Title:
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INTEGRATED CIRCUIT CONFIGURATION HAVING AT LEAST ONE TRANSISTOR AND ONE CAPACITOR, AND METHOD FOR FABRICATING IT
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09716871
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Filing Dt:
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11/20/2000
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Title:
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Method for carrying out auto refresh sequences on a DRAM
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Patent #:
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Issue Dt:
|
12/03/2002
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Application #:
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09716901
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Filing Dt:
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11/20/2000
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Title:
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STANDBY VOLTAGE CONTROLLER AND VOLTAGE DIVIDER IN A CONFIGURATION FOR SUPPLYING VOLTAGES TO AN ELECTRONIC CIRCUIT
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Patent #:
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Issue Dt:
|
09/25/2001
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Application #:
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09718211
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Filing Dt:
|
11/21/2000
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Title:
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Method for forming and filling isolation trenches
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Patent #:
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Issue Dt:
|
08/20/2002
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Application #:
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09718937
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Filing Dt:
|
11/22/2000
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Title:
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INTEGRATED MEMORY HAVING MEMORY CELLS AND REFERENCE CELLS
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Patent #:
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Issue Dt:
|
09/24/2002
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Application #:
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09722118
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Filing Dt:
|
11/27/2000
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Title:
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METHOD OF TESTING MEMORY CELLS WITH A HYSTERESIS CURVE
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Patent #:
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Issue Dt:
|
07/15/2003
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Application #:
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09723151
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Filing Dt:
|
11/27/2000
|
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Title:
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METHOD FOR DETERMINING AN ENDPOINT AND SEMICONDUCTOR WAFER
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|
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Patent #:
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Issue Dt:
|
07/15/2003
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Application #:
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09723802
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Filing Dt:
|
11/28/2000
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Title:
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TWO STEP CHEMICAL MECHANICAL POLISHING PROCESS
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Patent #:
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Issue Dt:
|
02/03/2004
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Application #:
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09725346
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Filing Dt:
|
11/29/2000
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Publication #:
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Pub Dt:
|
06/07/2001
| | | | |
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Title:
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SUBSTRATE WITH AT LEAST TWO METAL STRUCTURES DEPOSITED THEREON, AND METHOD FOR FABRICATING THE SAME
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|
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Patent #:
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Issue Dt:
|
07/10/2001
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Application #:
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09725412
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Filing Dt:
|
11/29/2000
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Title:
|
Embedded vertical dram cells and dual workfunction logic gates
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Patent #:
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Issue Dt:
|
12/03/2002
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Application #:
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09726889
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Filing Dt:
|
11/30/2000
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Publication #:
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Pub Dt:
|
09/26/2002
| | | | |
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Title:
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CIRCUIT FOR RECEIVING AND DRIVING A CLOCK-SIGNAL
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Patent #:
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Issue Dt:
|
10/01/2002
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Application #:
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09726960
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Filing Dt:
|
11/30/2000
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Publication #:
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Pub Dt:
|
06/21/2001
| | | | |
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Title:
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METHOD FOR FABRICATING A FIELD-EFFECT TRANSISTOR HAVING AN ANTI-PUNCH-THROUGH IMPLANTATION REGION
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Patent #:
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Issue Dt:
|
12/10/2002
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Application #:
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09726984
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Filing Dt:
|
11/30/2000
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Publication #:
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Pub Dt:
|
05/30/2002
| | | | |
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Title:
|
RECEIVER IMMUNE TO SLOPE-REVERSAL NOISE
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Patent #:
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Issue Dt:
|
02/03/2004
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Application #:
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09729062
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Filing Dt:
|
12/04/2000
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Publication #:
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Pub Dt:
|
09/13/2001
| | | | |
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Title:
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LITHOGRAPHY METHOD AND LITHOGRAPHY MASK
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|
|
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Patent #:
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Issue Dt:
|
10/16/2001
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Application #:
|
09729066
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Filing Dt:
|
12/04/2000
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|
Publication #:
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Pub Dt:
|
06/07/2001
| | | | |
|
Title:
|
Method for producing a metal layer with a given thickness
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|
|
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Patent #:
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|
Issue Dt:
|
08/14/2001
|
Application #:
|
09729068
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Filing Dt:
|
12/04/2000
|
|
Publication #:
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Pub Dt:
|
05/03/2001
| | | | |
|
Title:
|
Method of programming a semiconductor memory
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|
|
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Patent #:
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|
Issue Dt:
|
05/17/2005
|
Application #:
|
09729636
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Filing Dt:
|
12/04/2000
|
|
Publication #:
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Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
ASSEMBLY COMPRISING A PLURALITY OF MASK CONTAINERS, MANUFACTURING SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICES, AND METHOD
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|
|
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Patent #:
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|
Issue Dt:
|
09/16/2003
|
Application #:
|
09731343
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Filing Dt:
|
12/06/2000
|
|
Publication #:
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Pub Dt:
|
06/06/2002
| | | | |
|
Title:
|
DRAM WITH VERTICAL TRANSISTOR AND TRENCH CAPACITOR MEMORY CELLS AND METHOD OF FABRICATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09732136
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Filing Dt:
|
12/07/2000
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2001
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT HAVING A PARTICULAR FUNCTIONALITY REQUIRED BY A USER OF THE CIRCUIT AND HAVING FIRST STRUCTURE TO PRODUCE THE PARTICULAR FUNCTIONALITY AND SECOND STRUCTURES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/27/2005
|
Application #:
|
09733665
|
Filing Dt:
|
12/08/2000
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2002
| | | | |
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Title:
|
SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
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|
