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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:035872/0344   Pages: 152
Recorded: 06/09/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 20
1
Patent #:
9523976
Issue Dt:
12/20/2016
Application #:
13678255
Filing Dt:
11/15/2012
Title:
METHOD AND SYSTEM FOR PROCESSING A SEMICONDUCTOR WAFER USING DATA ASSOCIATED WITH PREVIOUSLY PROCESSED WAFERS
2
Patent #:
NONE
Issue Dt:
Application #:
13682826
Filing Dt:
11/21/2012
Publication #:
US20140138790
Pub Dt:
05/22/2014
Title:
Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same
3
Patent #:
NONE
Issue Dt:
Application #:
13685222
Filing Dt:
11/26/2012
Publication #:
US20140148009
Pub Dt:
05/29/2014
Title:
Forming a Substantially Uniform Wing Height Among Elements in a Charge Trap Semiconductor Device
4
Patent #:
9021186
Issue Dt:
04/28/2015
Application #:
13709479
Filing Dt:
12/10/2012
Publication #:
US20130124789
Pub Dt:
05/16/2013
Title:
PARTIAL ALLOCATE PAGING MECHANISM USING A CONTROLLER AND A BUFFER
5
Patent #:
NONE
Issue Dt:
Application #:
13715181
Filing Dt:
12/14/2012
Publication #:
US20140167220
Pub Dt:
06/19/2014
Title:
THREE DIMENSIONAL CAPACITOR
6
Patent #:
9966477
Issue Dt:
05/08/2018
Application #:
13715185
Filing Dt:
12/14/2012
Publication #:
US20140170843
Pub Dt:
06/19/2014
Title:
Charge Trapping Split Gate Device and Method of Fabricating Same
7
Patent #:
9368606
Issue Dt:
06/14/2016
Application #:
13715577
Filing Dt:
12/14/2012
Publication #:
US20140167140
Pub Dt:
06/19/2014
Title:
MEMORY FIRST PROCESS FLOW AND DEVICE
8
Patent #:
NONE
Issue Dt:
Application #:
13715582
Filing Dt:
12/14/2012
Publication #:
US20140167141
Pub Dt:
06/19/2014
Title:
Charge Trapping Split Gate Embedded Flash Memory and Associated Methods
9
Patent #:
NONE
Issue Dt:
Application #:
13715673
Filing Dt:
12/14/2012
Publication #:
US20140167142
Pub Dt:
06/19/2014
Title:
Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells
10
Patent #:
NONE
Issue Dt:
Application #:
13715729
Filing Dt:
12/14/2012
Publication #:
US20140167136
Pub Dt:
06/19/2014
Title:
Charge Trapping Device with Improved Select Gate to Memory Gate Isoloation
11
Patent #:
9209197
Issue Dt:
12/08/2015
Application #:
13715828
Filing Dt:
12/14/2012
Publication #:
US20140167128
Pub Dt:
06/19/2014
Title:
MEMORY GATE LANDING PAD MADE FROM DUMMY FEATURES
12
Patent #:
9230548
Issue Dt:
01/05/2016
Application #:
13725173
Filing Dt:
12/21/2012
Publication #:
US20140180690
Pub Dt:
06/26/2014
Title:
HYBRID HASHING SCHEME FOR ACTIVE HMMS
13
Patent #:
9224384
Issue Dt:
12/29/2015
Application #:
13725224
Filing Dt:
12/21/2012
Publication #:
US20140180693
Pub Dt:
06/26/2014
Title:
HISTOGRAM BASED PRE-PRUNING SCHEME FOR ACTIVE HMMS
14
Patent #:
9514739
Issue Dt:
12/06/2016
Application #:
13725260
Filing Dt:
12/21/2012
Publication #:
US20140180694
Pub Dt:
06/26/2014
Title:
Phoneme Score Accelerator
15
Patent #:
9305614
Issue Dt:
04/05/2016
Application #:
13725415
Filing Dt:
12/21/2012
Publication #:
US20140177375
Pub Dt:
06/26/2014
Title:
Memory Device with Internal Combination Logic
16
Patent #:
9318498
Issue Dt:
04/19/2016
Application #:
13735156
Filing Dt:
01/07/2013
Publication #:
US20140193972
Pub Dt:
07/10/2014
Title:
BURIED HARD MASK FOR EMBEDDED SEMICONDUCTOR DEVICE PATTERNING
17
Patent #:
9431364
Issue Dt:
08/30/2016
Application #:
13735650
Filing Dt:
01/07/2013
Publication #:
US20140191417
Pub Dt:
07/10/2014
Title:
Multi-Chip Package Assembly with Improved Bond Wire Separation
18
Patent #:
NONE
Issue Dt:
Application #:
13736618
Filing Dt:
01/08/2013
Publication #:
US20140195233
Pub Dt:
07/10/2014
Title:
Distributed Speech Recognition System
19
Patent #:
9042150
Issue Dt:
05/26/2015
Application #:
13737321
Filing Dt:
01/09/2013
Publication #:
US20140192581
Pub Dt:
07/10/2014
Title:
PROGRAMMABLE AND FLEXIBLE REFERENCE CELL SELECTION METHOD FOR MEMORY DEVICES
20
Patent #:
9373621
Issue Dt:
06/21/2016
Application #:
13746477
Filing Dt:
01/22/2013
Publication #:
US20130140642
Pub Dt:
06/06/2013
Title:
ANALOG CIRCUIT CELL ARRAY HAVING SOME TRANSISTORS THAT INCLUDE TWO CONNECTED GATE ELECTRODES AND TWO CONNECTED SOURCE REGIONS
Assignor
1
SPANSION LLC
Exec Dt:
06/01/2015
Assignee
1
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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