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Total properties:
17
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11394986
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Filing Dt:
|
03/30/2006
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Publication #:
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Pub Dt:
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10/05/2006
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Title:
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Stacked-type semiconductor device and method of manufacturing the same
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|
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11399158
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Filing Dt:
|
04/06/2006
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Publication #:
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Pub Dt:
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10/25/2007
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Title:
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Methods for erasing memory devices and multi-level programming memory device
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11423643
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Filing Dt:
|
06/12/2006
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Publication #:
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Pub Dt:
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05/29/2008
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Title:
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METHOD AND APPARATUS FOR VERSATILE HIGH VOLTAGE LEVEL DETECTION WITH RELATIVE NOISE IMMUNITY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11423649
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Filing Dt:
|
06/12/2006
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Publication #:
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Pub Dt:
|
12/13/2007
| | | | |
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Title:
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METHOD AND APPARATUS FOR DRAIN PUMP POWER CONSERVATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11441771
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Filing Dt:
|
05/26/2006
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
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Title:
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Semiconductor device and method for fabricating the same
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|
|
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11501870
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Filing Dt:
|
08/10/2006
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Publication #:
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Pub Dt:
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09/27/2007
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Title:
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Method and apparatus for supporting software tuning for multi-core processor, and computer product
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|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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11529805
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Filing Dt:
|
09/29/2006
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Publication #:
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Pub Dt:
|
04/05/2007
| | | | |
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Title:
|
Semiconductor device and fabrication method therefor
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
11546688
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Filing Dt:
|
10/12/2006
|
|
Publication #:
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Pub Dt:
|
02/08/2007
| | | | |
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Title:
|
Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
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Application #:
|
11595237
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Filing Dt:
|
11/09/2006
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Publication #:
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Pub Dt:
|
05/31/2007
| | | | |
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Title:
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SRAM devices based on resonant tunneling
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
11614839
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Filing Dt:
|
12/21/2006
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Publication #:
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Pub Dt:
|
06/26/2008
| | | | |
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Title:
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MEMORY SYSTEM WITH SELECT GATE ERASE
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|
|
|
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
11616385
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Filing Dt:
|
12/27/2006
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|
Publication #:
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Pub Dt:
|
07/03/2008
| | | | |
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Title:
|
PERSONAL DIGITAL RIGHTS MANAGEMENT AGENT-SERVER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
11634777
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Filing Dt:
|
12/06/2006
|
|
Publication #:
|
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Pub Dt:
|
06/12/2008
| | | | |
|
Title:
|
Barrier region underlying source/drain regions for dual-bit memory devices
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/13/2015
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Application #:
|
11639666
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Filing Dt:
|
12/15/2006
|
|
Publication #:
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Pub Dt:
|
06/19/2008
| | | | |
|
Title:
|
METHOD FOR FABRICATING MEMORY CELLS HAVING SPLIT CHARGE STORAGE NODES
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11641506
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Filing Dt:
|
12/19/2006
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
|
Title:
|
Stress management in BGA packaging
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11650907
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Filing Dt:
|
01/08/2007
|
|
Publication #:
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|
Pub Dt:
|
01/01/2009
| | | | |
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Title:
|
Structure and method for wire bond integrity check on BGA substrates using indirect electrical interconnectivity pathway between wire bonds and ground
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
11652785
|
Filing Dt:
|
01/11/2007
|
|
Title:
|
Shallow bipolar junction transistor
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11685711
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Filing Dt:
|
03/13/2007
|
|
Publication #:
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|
Pub Dt:
|
07/19/2007
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TRENCH
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|
