USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	036025/0453			Pages:	153
		Recorded:	06/29/2015
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 50

Patent #:	6535960	Issue Dt:	03/18/2003	Application #:	09074317	Filing Dt:	05/08/1998
Title:	INFORMATION PROCESSING DEVICE

Patent #:	6507068	Issue Dt:	01/14/2003	Application #:	09160046	Filing Dt:	09/25/1998
Publication #:	US20010019149	Pub Dt:	09/06/2001
Title:	FLASH MEMORY DEVICE AND A FABRICATION PROCESS THEREOF

Patent #:	6515328	Issue Dt:	02/04/2003	Application #:	09244429	Filing Dt:	02/04/1999
Title:	SEMICONDUCTOR DEVICES WITH REDUCED CONTROL GATE DIMENSIONS

Patent #:	6530068	Issue Dt:	03/04/2003	Application #:	09366369	Filing Dt:	08/03/1999
Title:	DEVICE MODELING AND CHARACTERIZATION STRUCTURE WITH MULTIPLEXED PADS

Patent #:	6506683	Issue Dt:	01/14/2003	Application #:	09413621	Filing Dt:	10/06/1999
Title:	IN-SITU PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INTEGRAL REMOVAL OF ANTIREFLECTION AND ETCH STOP LAYERS

Patent #:	6516378	Issue Dt:	02/04/2003	Application #:	09426757	Filing Dt:	10/26/1999
Title:	MICROPROCESSOR FOR CONTROLLING BUSSES

Patent #:	6518072	Issue Dt:	02/11/2003	Application #:	09476906	Filing Dt:	01/03/2000
Title:	DEPOSITED SCREEN OXIDE FOR REDUCING GATE EDGE LIFTING

Patent #:	6509604	Issue Dt:	01/21/2003	Application #:	09491457	Filing Dt:	01/26/2000
Title:	NOVEL NITRIDATION BARRIERS FOR NITRIDATED TUNNEL OXIDE FOR CIRCUITRY FOR FLASH TECHNOLOGY AND FOR LOCOS/STI ISOLATION

Patent #:	6529083	Issue Dt:	03/04/2003	Application #:	09538523	Filing Dt:	03/30/2000
Publication #:	US20020047748	Pub Dt:	04/25/2002
Title:	CLOCK CONTROL CIRCUIT

Patent #:	6530997	Issue Dt:	03/11/2003	Application #:	09543484	Filing Dt:	04/06/2000
Title:	USE OF GASEOUS SILICON HYDRIDES AS A REDUCING AGENT TO REMOVE RE-SPUTTERED SILICON OXIDE

Patent #:	6534411	Issue Dt:	03/18/2003	Application #:	09548616	Filing Dt:	04/13/2000
Title:	METHOD OF HIGH DENSITY PLASMA METAL ETCHING

Patent #:	6512264	Issue Dt:	01/28/2003	Application #:	09594207	Filing Dt:	06/14/2000
Title:	FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER AND METHOD OF FORMING

Patent #:	6529410	Issue Dt:	03/04/2003	Application #:	09665916	Filing Dt:	09/20/2000
Title:	NAND ARRAY STRUCTURE AND METHOD WITH BURIED LAYER

Patent #:	6506640	Issue Dt:	01/14/2003	Application #:	09667686	Filing Dt:	09/22/2000
Title:	MULTIPLE CHANNEL IMPLANTATION TO FORM RETROGRADE CHANNEL PROFILE AND TO ENGINEER THRESHOLD VOLTAGE AND SUB-SURFACE PUNCH-THROUGH

Patent #:	6501681	Issue Dt:	12/31/2002	Application #:	09684694	Filing Dt:	10/04/2000
Title:	USING A LOW DRAIN BIAS DURING ERASE VERIFY TO ENSURE COMPLETE REMOVAL OF RESIDUAL CHARGE IN THE NITRIDE IN SONOS NON-VOLATILE MEMORIES

Patent #:	6537881	Issue Dt:	03/25/2003	Application #:	09688504	Filing Dt:	10/16/2000
Title:	PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE

Patent #:	6537866	Issue Dt:	03/25/2003	Application #:	09691643	Filing Dt:	10/18/2000
Title:	METHOD OF FORMING NARROW INSULATING SPACERS FOR USE IN REDUCING MINIMUM COMPONENT SIZE

Patent #:	6515344	Issue Dt:	02/04/2003	Application #:	09698485	Filing Dt:	10/30/2000
Title:	THIN OXIDE ANTI-FUSE

Patent #:	6507527	Issue Dt:	01/14/2003	Application #:	09698614	Filing Dt:	10/27/2000
Title:	MEMORY LINE DISCHARGE BEFORE SENSING

Patent #:	6500768	Issue Dt:	12/31/2002	Application #:	09699531	Filing Dt:	10/30/2000
Title:	METHOD FOR SELECTIVE REMOVAL OF ONO LAYER

Patent #:	6524914	Issue Dt:	02/25/2003	Application #:	09699972	Filing Dt:	10/30/2000
Title:	SOURCE SIDE BORON IMPLANTING AND DIFFUSING DEVICE ARCHITECTURE FOR DEEP SUB 0.18 MICRON FLASH MEMORY

Patent #:	6538270	Issue Dt:	03/25/2003	Application #:	09721031	Filing Dt:	11/22/2000
Title:	STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL

Patent #:	6538923	Issue Dt:	03/25/2003	Application #:	09794482	Filing Dt:	02/26/2001
Title:	STAIRCASE PROGRAM VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS

Patent #:	6528390	Issue Dt:	03/04/2003	Application #:	09798667	Filing Dt:	03/02/2001
Publication #:	US20020132446	Pub Dt:	09/19/2002
Title:	PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE

Patent #:	6534363	Issue Dt:	03/18/2003	Application #:	09803400	Filing Dt:	03/12/2001
Publication #:	US20020127799	Pub Dt:	09/12/2002
Title:	HIGH VOLTAGE OXIDATION METHOD FOR HIGHLY RELIABLE FLASH MEMORY DEVICES

Patent #:	6515525	Issue Dt:	02/04/2003	Application #:	09809208	Filing Dt:	03/16/2001
Publication #:	US20010052804	Pub Dt:	12/20/2001
Title:	FRACTIONAL-N-PILL FREQUENCY SYNTHESIZER AND PHASE ERROR CANCELING METHOD THEREFOR

Patent #:	6518845	Issue Dt:	02/11/2003	Application #:	09809221	Filing Dt:	03/16/2001
Publication #:	US20020008586	Pub Dt:	01/24/2002
Title:	PLL FREQUENCY SYNTHESIZER CIRCUIT

Patent #:	6514822	Issue Dt:	02/04/2003	Application #:	09844692	Filing Dt:	04/27/2001
Publication #:	US20020158284	Pub Dt:	10/31/2002
Title:	METHOD AND SYSTEM FOR REDUCING THINNING OF FIELD ISOLATION STRUCTURES IN A FLASH MEMORY DEVICE

Patent #:	6509229	Issue Dt:	01/21/2003	Application #:	09850484	Filing Dt:	05/07/2001
Title:	METHOD FOR FORMING SELF-ALIGNED CONTACTS USING CONSUMABLE SPACERS

Patent #:	6519672	Issue Dt:	02/11/2003	Application #:	09854351	Filing Dt:	05/10/2001
Publication #:	US20020026493	Pub Dt:	02/28/2002
Title:	SHARED MEMORY APPARATUS AND METHOD FOR MULTIPROCESSOR SYSTEMS

Patent #:	6510085	Issue Dt:	01/21/2003	Application #:	09861031	Filing Dt:	05/18/2001
Title:	METHOD OF CHANNEL HOT ELECTRON PROGRAMMING FOR SHORT CHANNEL NOR FLASH ARRAYS

Patent #:	6515902	Issue Dt:	02/04/2003	Application #:	09873643	Filing Dt:	06/04/2001
Title:	METHOD AND APPARATUS FOR BOOSTING BITLINES FOR LOW VCC READ

Patent #:	6509202	Issue Dt:	01/21/2003	Application #:	09875073	Filing Dt:	06/05/2001
Title:	METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE

Patent #:	6512701	Issue Dt:	01/28/2003	Application #:	09886861	Filing Dt:	06/21/2001
Title:	ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH

Patent #:	6525368	Issue Dt:	02/25/2003	Application #:	09892685	Filing Dt:	06/27/2001
Title:	HIGH DENSITY FLASH EEPROM ARRAY WITH SOURCE SIDE INJECTION

Patent #:	6519182	Issue Dt:	02/11/2003	Application #:	09902332	Filing Dt:	07/10/2001
Title:	USING HOT CARRIER INJECTION TO CONTROL OVER-PROGRAMMING IN A NON-VOLATILE MEMORY CELL HAVING AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE

Patent #:	6535419	Issue Dt:	03/18/2003	Application #:	09905421	Filing Dt:	07/13/2001
Publication #:	US20010038553	Pub Dt:	11/08/2001
Title:	MIXED MODE MULTI LEVEL MODE INDICTOR

Patent #:	6535424	Issue Dt:	03/18/2003	Application #:	09915018	Filing Dt:	07/25/2001
Publication #:	US20030021152	Pub Dt:	01/30/2003
Title:	VOLTAGE BOOST CIRCUIT USING SUPPLY VOLTAGE DETECTION TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS IN READ MODE VOLTAGES

Patent #:	6525959	Issue Dt:	02/25/2003	Application #:	09917178	Filing Dt:	07/30/2001
Title:	NOR ARRAY WITH BURIED TRENCH SOURCE LINE

Patent #:	6541338	Issue Dt:	04/01/2003	Application #:	09917182	Filing Dt:	07/30/2001
Publication #:	US20030022440	Pub Dt:	01/30/2003
Title:	LOW DEFECT DENSITY PROCESS FOR DEEP SUB-0.18UM FLASH MEMORY TECHNOLOGIES

Patent #:	6525969	Issue Dt:	02/25/2003	Application #:	09928059	Filing Dt:	08/10/2001
Title:	DECODER APPARATUS AND METHODS FOR PRE-CHARGING BIT LINES

Patent #:	6509232	Issue Dt:	01/21/2003	Application #:	09969573	Filing Dt:	10/01/2001
Title:	FORMATION OF STI (SHALLOW TRENCH ISOLATION) STRUCTURES WITHIN CORE AND PERIPHERY AREAS OF FLASH MEMORY DEVICE

Patent #:	6510082	Issue Dt:	01/21/2003	Application #:	09999869	Filing Dt:	10/23/2001
Title:	DRAIN SIDE SENSING SCHEME FOR VIRTUAL GROUND FLASH EPROM ARRAY WITH ADJACENT BIT CHARGE AND HOLD

Patent #:	6525966	Issue Dt:	02/25/2003	Application #:	10010985	Filing Dt:	12/05/2001
Title:	METHOD AND APPARATUS FOR ADJUSTING ON-CHIP CURRENT REFERENCE FOR EEPROM SENSING

Patent #:	6514830	Issue Dt:	02/04/2003	Application #:	10044510	Filing Dt:	01/11/2002
Title:	METHOD OF MANUFACTURING HIGH VOLTAGE TRANSISTOR WITH MODIFIED FIELD IMPLANT MASK

Patent #:	6515903	Issue Dt:	02/04/2003	Application #:	10050254	Filing Dt:	01/16/2002
Title:	NEGATIVE PUMP REGULATOR USING MOS CAPACITOR

Patent #:	6529412	Issue Dt:	03/04/2003	Application #:	10050257	Filing Dt:	01/16/2002
Title:	SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE

Patent #:	6532175	Issue Dt:	03/11/2003	Application #:	10050650	Filing Dt:	01/16/2002
Title:	METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE

Patent #:	6510090	Issue Dt:	01/21/2003	Application #:	10103721	Filing Dt:	03/25/2002
Title:	SEMICONDUCTOR MEMORY DEVICE

Patent #:	6538834	Issue Dt:	03/25/2003	Application #:	10187944	Filing Dt:	07/03/2002
Publication #:	US20020180628	Pub Dt:	12/05/2002
Title:	SERVO CONTROLLER AND SERVO CONTROL METHOD

Assignor

SPANSION, LLC

Exec Dt:

06/01/2015

Assignee

CYPRESS SEMICONDUCTOR CORPORATION

198 CHAMPION COURT

SAN JOSE, CALIFORNIA 95134

Correspondence name and address
	CYPRESS SEMICONDUCTOR CORPORATION
	198 CHAMPION COURT
	SAN JOSE, CA 95134

Search Results as of: 05/09/2024 03:46 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6