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Patent Assignment Details
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Reel/Frame:036029/0370   Pages: 152
Recorded: 06/29/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
Issue Dt:
02/06/2001
Application #:
08993062
Filing Dt:
12/18/1997
Title:
DEVICE INITIALIZING SYSTEM WITH PROGRAMMABLE ARRAY LOGIC CONFIGURED TO CAUSE NON-VOLATILE MEMORY TO OUTPUT ADDRESS AND DATA INFORMATION TO THE DEVICE IN A PRESCRIBED SEQUENCE
2
Patent #:
Issue Dt:
02/13/2001
Application #:
09006757
Filing Dt:
01/14/1998
Title:
FLASH EPROM CELL WITH REDUCED SHORT CHANNEL EFFECT AND METHOD FOR PROVIDING SAME
3
Patent #:
Issue Dt:
02/13/2001
Application #:
09033642
Filing Dt:
03/03/1998
Title:
METHOD AND APPARATUS FOR CONTROLLING THE THICKNESS OF A GATE OXIDE IN A SEMICONDUCTOR MANUFACTURING PROCESS
4
Patent #:
Issue Dt:
03/20/2001
Application #:
09166384
Filing Dt:
10/05/1998
Title:
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
5
Patent #:
Issue Dt:
02/06/2001
Application #:
09263701
Filing Dt:
03/05/1999
Title:
METHOD TO ELIMATE SILICIDE CRACKING FOR NAND TYPE FLASH MEMORY DEVICES BY IMPLANTING A POLISH RATE IMPROVER INTO THE SECOND POLYSILICON LAYER AND POLISHING IT
6
Patent #:
Issue Dt:
02/13/2001
Application #:
09307259
Filing Dt:
05/06/1999
Title:
RAMPED OR STEPPED GATE CHANNEL ERASE FOR FLASH MEMORY APPLICATION
7
Patent #:
Issue Dt:
03/20/2001
Application #:
09349603
Filing Dt:
07/09/1999
Title:
METHOD OF FORMING SELECT GATE TO IMPROVE RELIABILITY AND PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES
8
Patent #:
Issue Dt:
02/13/2001
Application #:
09369600
Filing Dt:
08/06/1999
Title:
MULTI STATE SENSING OF NAND MEMORY CELLS BY VARYING SOURCE BIAS
9
Patent #:
Issue Dt:
03/13/2001
Application #:
09409542
Filing Dt:
09/30/1999
Title:
METHOD AND APPARATUS FOR MEASURING SUBTHRESHOLD CURRENT IN A MEMORY ARRAY
10
Patent #:
Issue Dt:
03/06/2001
Application #:
09417130
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED MASKING AND WITHOUT ARC LOSS IN PERIPHERAL CIRCUITRY REGION
11
Patent #:
Issue Dt:
03/13/2001
Application #:
09417132
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITHOUT ARC LOSS IN PERIPHERAL CIRCUIT REGION
12
Patent #:
Issue Dt:
02/06/2001
Application #:
09420209
Filing Dt:
10/18/1999
Title:
PROGRAMMABLE CURRENT SOURCE
13
Patent #:
Issue Dt:
03/13/2001
Application #:
09421142
Filing Dt:
10/19/1999
Title:
LATCHING CAM DATA IN A FLASH MEMORY DEVICE
14
Patent #:
Issue Dt:
02/06/2001
Application #:
09421984
Filing Dt:
10/19/1999
Title:
REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
15
Patent #:
Issue Dt:
01/30/2001
Application #:
09426240
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE USING RAPID-THERMAL-CHEMICAL-VAPOR-DEPOSITION
16
Patent #:
Issue Dt:
03/27/2001
Application #:
09426255
Filing Dt:
10/25/1999
Title:
METHOD OF USING SOURCE/DRAIN NITRIDE FOR PERIPHERY FIELD OXIDE AND BIT-LINE OXIDE
17
Patent #:
Issue Dt:
01/30/2001
Application #:
09468938
Filing Dt:
12/22/1999
Title:
SEMICONDUCTOR DEVICE HAVING CURRENT AUXILIARY CIRCUIT FOR OUTPUT CIRCUIT
18
Patent #:
Issue Dt:
03/06/2001
Application #:
09495215
Filing Dt:
01/31/2000
Title:
APDE scheme for flash memory application
19
Patent #:
Issue Dt:
03/20/2001
Application #:
09504558
Filing Dt:
02/15/2000
Title:
System and method for detecting flash memory threshold voltages
20
Patent #:
Issue Dt:
03/20/2001
Application #:
09512854
Filing Dt:
02/25/2000
Title:
Dynamic memory cell programming voltage
21
Patent #:
Issue Dt:
03/27/2001
Application #:
09516472
Filing Dt:
03/01/2000
Title:
FLASH MEMORY CELLS HAVING A MODULATION DOPED HETEROJUNCTION STRUCTURE
22
Patent #:
Issue Dt:
03/27/2001
Application #:
09547556
Filing Dt:
04/12/2000
Title:
Address transition detect timing architecture for a simultaneous operation flash memory device
23
Patent #:
Issue Dt:
02/27/2001
Application #:
09556306
Filing Dt:
04/24/2000
Title:
Charge and discharge control circuit and apparatus for secondary battery
24
Patent #:
Issue Dt:
03/13/2001
Application #:
09558764
Filing Dt:
04/26/2000
Title:
Apparatus and method to characterize the threshold distribution in an nrom virtual ground array
25
Patent #:
Issue Dt:
03/20/2001
Application #:
09610764
Filing Dt:
07/06/2000
Title:
Temperature-compensated bias generator
Assignor
1
Exec Dt:
06/01/2015
Assignee
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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