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Total properties:
25
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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08885140
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Filing Dt:
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06/30/1997
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Title:
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METHOD AND APPARATUS FOR CONTROLLING THE THICKNESS OF A GATE OXIDE IN A SEMICONDUCTOR MANUFACTURING PROCESS
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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08992960
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR IMPROVED FORMATION OF CONTROL AND FLOATING GATES IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09040823
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Filing Dt:
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03/18/1998
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Title:
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PROCESS FOR FABRICATING A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09047237
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Filing Dt:
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03/25/1998
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Title:
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CAPACITOR FOR USE IN A CAPACITOR DIVIDER THAT HAS A FLOATING GATE TRANSISTOR AS A CORRESPONDING CAPACITOR
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09163315
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Filing Dt:
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09/30/1998
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Title:
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VIABLE MEMORY CELL FORMED USING RAPID THERMAL ANNEALING
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09221989
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Filing Dt:
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12/29/1998
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Title:
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TRANSISTOR OUTPUT CIRCUIT
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09364982
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Filing Dt:
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07/31/1999
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Title:
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METHOD FOR INHIBITING TUNNEL OXIDE GROWTH AT THE EDGES OF A FLOATING GATE DURING SEMICONDUCOR DEVICE PROCESSING
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09377183
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Filing Dt:
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08/19/1999
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Title:
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NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING ASSYMETRICALLY NITROGEN DOPED GATE OXIDE
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09410512
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Filing Dt:
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09/30/1999
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Title:
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DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09416563
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Filing Dt:
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10/12/1999
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Title:
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MULTIPLE BYTE CHANNEL HOT ELECTRON PROGRAMMING USING RAMPED GATE AND SOURCE BIAS VOLTAGE
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09420220
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Filing Dt:
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10/18/1999
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Title:
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NITRIDE PLUG TO REDUCE GATE EDGE LIFTING
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09422198
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Filing Dt:
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10/19/1999
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Title:
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SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09426205
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09426672
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Filing Dt:
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10/25/1999
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Title:
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HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09476121
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Filing Dt:
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01/03/2000
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09504695
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Filing Dt:
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02/16/2000
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Title:
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Method of erasing non-volatile memory cells
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09547747
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Filing Dt:
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04/12/2000
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Title:
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Charge sharing to help boost the wordlines during apde verify
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09557728
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Filing Dt:
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04/26/2000
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Title:
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Matching loading between sensing reference and memory cell with reduced transistor count in a dual-bank flash memory
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09596449
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Filing Dt:
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06/19/2000
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Title:
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Dual bit isolation scheme for flash devices
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09602328
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Filing Dt:
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06/23/2000
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Title:
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Apparatus and method of direct current sensing from source side in a virtual ground array
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09661356
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Filing Dt:
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09/14/2000
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Title:
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Output buffer for external voltage
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09661358
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Filing Dt:
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09/14/2000
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Title:
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Chip enable input buffer
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09685968
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Filing Dt:
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10/10/2000
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Title:
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Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09692881
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Filing Dt:
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10/23/2000
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Title:
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Automatic program disturb with intelligent soft programming for flash cells
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09694729
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Filing Dt:
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10/23/2000
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Title:
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Method of programming a non-volatile memory cell using a current limiter
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