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Patent Assignment Details
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Reel/Frame:036031/0691   Pages: 152
Recorded: 06/29/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
Issue Dt:
08/28/2001
Application #:
08993344
Filing Dt:
12/18/1997
Title:
MANUFACTURING PROCESS TO ELIMINATE ONO FENCE MATERIAL IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
2
Patent #:
Issue Dt:
09/04/2001
Application #:
09052057
Filing Dt:
03/30/1998
Title:
TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS
3
Patent #:
Issue Dt:
08/14/2001
Application #:
09159489
Filing Dt:
09/23/1998
Title:
BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
4
Patent #:
Issue Dt:
09/04/2001
Application #:
09257040
Filing Dt:
02/25/1999
Title:
SHARED MEMORY ACCESS DEVICE AND METHOD
5
Patent #:
Issue Dt:
09/25/2001
Application #:
09273430
Filing Dt:
03/19/1999
Title:
SHARED MEMORY APPARATUS AND METHOD FOR MULTIPROCESSOR SYSTEMS
6
Patent #:
Issue Dt:
10/09/2001
Application #:
09368073
Filing Dt:
08/03/1999
Title:
METHOD FOR REDUCED GATE ASPECT RATIO TO IMPROVE GAP-FILL AFTER SPACER ETCH
7
Patent #:
Issue Dt:
09/11/2001
Application #:
09392675
Filing Dt:
09/08/1999
Title:
PROCESS FOR FABRICATING AN MNOS FLASH MEMORY DEVICE
8
Patent #:
Issue Dt:
09/04/2001
Application #:
09399526
Filing Dt:
09/20/1999
Title:
PROCESS TO REDUCE POST CYCLING PROGRAM VT DISPERSION FOR NAND FLASH MEMORY DEVICES
9
Patent #:
Issue Dt:
09/18/2001
Application #:
09416382
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS BEFORE CONTACT CMP
10
Patent #:
Issue Dt:
09/04/2001
Application #:
09421471
Filing Dt:
10/19/1999
Title:
OUTPUT SWITCHING IMPLEMENTATION FOR A FLASH MEMORY DEVICE
11
Patent #:
Issue Dt:
10/02/2001
Application #:
09426743
Filing Dt:
10/25/1999
Title:
PROCESS FOR FORMING A BIT-LINE IN A MONOS DEVICE
12
Patent #:
Issue Dt:
09/25/2001
Application #:
09495213
Filing Dt:
01/31/2000
Title:
Nitridization of the pre-ddi screen oxide
13
Patent #:
Issue Dt:
09/04/2001
Application #:
09495216
Filing Dt:
01/31/2000
Title:
Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells
14
Patent #:
Issue Dt:
09/04/2001
Application #:
09506351
Filing Dt:
02/17/2000
Title:
High speed sensing to detect write protect state in a flash memory device
15
Patent #:
Issue Dt:
10/02/2001
Application #:
09513402
Filing Dt:
02/25/2000
Title:
MODE INDICATOR FOR MULTI-LEVEL MEMORY
16
Patent #:
Issue Dt:
09/04/2001
Application #:
09523816
Filing Dt:
03/13/2000
Title:
Wordline voltage protection
17
Patent #:
Issue Dt:
09/25/2001
Application #:
09586254
Filing Dt:
05/31/2000
Title:
Semiconductor manufacturing method using a high extinction coefficient dielectric photomask
18
Patent #:
Issue Dt:
09/04/2001
Application #:
09609468
Filing Dt:
07/03/2000
Title:
Species implantation for minimizing interface defect density in flash memory devices
19
Patent #:
Issue Dt:
10/02/2001
Application #:
09652742
Filing Dt:
08/31/2000
Title:
Method and apparatus for eliminating false data in a page mode memory device
20
Patent #:
Issue Dt:
09/04/2001
Application #:
09663909
Filing Dt:
09/18/2000
Title:
Address transition detector architecture for a high density flash memory device
21
Patent #:
Issue Dt:
09/11/2001
Application #:
09675940
Filing Dt:
09/29/2000
Title:
Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider
22
Patent #:
Issue Dt:
09/18/2001
Application #:
09696652
Filing Dt:
10/25/2000
Title:
Power saving on the fly during reading of data from a memory device
23
Patent #:
Issue Dt:
08/21/2001
Application #:
09708982
Filing Dt:
11/01/2000
Title:
Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant
24
Patent #:
Issue Dt:
10/02/2001
Application #:
09712382
Filing Dt:
11/13/2000
Title:
Acceleration voltage implementation for a high density flash memory device
25
Patent #:
Issue Dt:
08/14/2001
Application #:
09774509
Filing Dt:
01/31/2001
Title:
Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
Assignor
1
Exec Dt:
06/01/2015
Assignee
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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