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Total properties:
50
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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08690848
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Filing Dt:
|
08/01/1996
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Title:
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SILICON NITRIDE ETCH PROCESS WITH CRITICAL GAIN
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Patent #:
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Issue Dt:
|
04/29/2003
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Application #:
|
08991448
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Filing Dt:
|
12/16/1997
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Title:
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FLASH MEMORY GATE COUPLING USING HSG POLYSILICON
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Patent #:
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Issue Dt:
|
06/24/2003
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Application #:
|
09314574
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Filing Dt:
|
05/18/1999
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Title:
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DATA PRE-READING AND ERROR CORRECTION CIRCUIT FOR A MEMORY DEVICE
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
|
09372406
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Filing Dt:
|
08/10/1999
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Title:
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METHOD OF REDUCING PROGRAM DISTURBS IN NAND TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
|
06/10/2003
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Application #:
|
09387710
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Filing Dt:
|
08/30/1999
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Title:
|
INTEGRATED CIRCUIT HAVING OPTIMIZED GATE COUPLING CAPACITANCE
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Patent #:
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Issue Dt:
|
04/15/2003
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Application #:
|
09421470
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Filing Dt:
|
10/19/1999
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Title:
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ARRAY VT MODE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
|
05/27/2003
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Application #:
|
09421758
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Filing Dt:
|
10/19/1999
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|
Title:
|
MULTIPLE PURPOSE BUS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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|
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Patent #:
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Issue Dt:
|
04/22/2003
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Application #:
|
09430845
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Filing Dt:
|
11/01/1999
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|
Title:
|
DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
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|
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Patent #:
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Issue Dt:
|
04/08/2003
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Application #:
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09452718
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Filing Dt:
|
12/03/1999
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Title:
|
SEMICONDUCTOR MEMORY AND OUTPUT SIGNAL CONTROL METHOD AND CIRCUIT IN SEMICONDUCTOR MEMORY
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|
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Patent #:
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Issue Dt:
|
04/01/2003
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Application #:
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09531871
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Filing Dt:
|
03/21/2000
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Title:
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METHOD AND APPARATUS FOR EQUALIZATION OF ADDRESS TRANSITION DETECTION PULSE WIDTH
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|
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Patent #:
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|
Issue Dt:
|
05/06/2003
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Application #:
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09609793
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Filing Dt:
|
07/03/2000
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Title:
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AUTOMATED DETERMINATION AND DISPLAY OF THE PHYSICAL LOCATION OF A FAILED CELL IN AN ARRAY OF MEMORY CELLS
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|
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Patent #:
|
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Issue Dt:
|
06/17/2003
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Application #:
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09619231
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Filing Dt:
|
07/19/2000
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Title:
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ELIMINATION OF N+ CONTACT IMPLANT FROM FLASH TECHNOLOGIES BY REPLACEMENT WITH STANDARD DOUBLE-DIFFUSED AND N+ IMPLANTS
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
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09634991
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Filing Dt:
|
08/08/2000
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|
Title:
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SOURCE BUS FORMATION FOR A FLASH MEMORY USING SILICIDE
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/20/2003
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Application #:
|
09644359
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Filing Dt:
|
08/23/2000
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|
Title:
|
PHYSICAL MEMORY LAYOUT WITH VARIOUS SIZED MEMORY SECTORS
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|
|
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Patent #:
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|
Issue Dt:
|
05/13/2003
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Application #:
|
09651704
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Filing Dt:
|
08/31/2000
|
|
Title:
|
BIT-LINE OXIDATION BY REMOVING ONO OXIDE PRIOR TO BIT-LINE IMPLANT
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/01/2003
|
Application #:
|
09654965
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Filing Dt:
|
09/05/2000
|
|
Title:
|
METHOD OF MICRO-ARCHITECTURAL IMPLEMENTATION OF INTERFACE BETWEEN BIST STATE MACHINE AND TESTER INTERFACE TO ENABLE BIST CYCLING
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/15/2003
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Application #:
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09657143
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Filing Dt:
|
09/07/2000
|
|
Title:
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USING A NEGATIVE GATE ERASE VOLTAGE APPLIED IN STEPS OF DECREASING AMOUNTS TO REDUCE ERASE TIME FOR A NON-VOLATILE MEMORY CELL WITH AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
06/24/2003
|
Application #:
|
09688936
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Filing Dt:
|
10/16/2000
|
|
Title:
|
SIDEWALL NROM AND METHOD OF MANUFACTURE THEREOF FOR NON-VOLATILE MEMORY CELLS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09689144
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Filing Dt:
|
10/11/2000
|
|
Title:
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METHOD FOR SIMULTANEOUS DEPOSITION AND SPUTTERING OF TEOS AND DEVICE THEREBY FORMED
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/20/2003
|
Application #:
|
09689714
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Filing Dt:
|
10/13/2000
|
|
Title:
|
A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING A CHARGE STORING INSULATION FILM AND DATA HOLDING METHOD THEREFOR
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|
|
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|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09718771
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Filing Dt:
|
11/22/2000
|
|
Title:
|
STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09727656
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Filing Dt:
|
11/30/2000
|
|
Title:
|
ERASE VERIFY MODE TO EVALUATE NEGATIVE VT'S
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09779794
|
Filing Dt:
|
02/08/2001
|
|
Title:
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PIGGYBACK PROGRAMMING USING AN EXTENDED FIRST PULSE FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/01/2003
|
Application #:
|
09779821
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Filing Dt:
|
02/08/2001
|
|
Title:
|
PIGGYBACK PROGRAMMING USING VOLTAGE CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09810155
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Filing Dt:
|
03/16/2001
|
|
Title:
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PROCESS FOR MAKING A DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09884204
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Filing Dt:
|
06/19/2001
|
|
Title:
|
METHOD OF FORMING ZERO MARKS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/08/2003
|
Application #:
|
09904089
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Filing Dt:
|
07/12/2001
|
|
Title:
|
OXIDE/NITRIDE OR OXIDE/NITRIDE/OXIDE THICKNESS MEASUREMENT USING SCATTEROMETRY
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/06/2003
|
Application #:
|
09927387
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Filing Dt:
|
08/13/2001
|
|
Publication #:
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|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY AND ITS DRIVING METHOD
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|
|
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|
Patent #:
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|
Issue Dt:
|
05/20/2003
|
Application #:
|
09968465
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Filing Dt:
|
10/01/2001
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|
Publication #:
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Pub Dt:
|
05/08/2003
| | | | |
|
Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
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|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09998624
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Filing Dt:
|
11/30/2001
|
|
Title:
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DIE SEAL FOR SEMICONDUCTOR DEVICE MOISTURE PROTECTION
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Patent #:
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|
Issue Dt:
|
05/20/2003
|
Application #:
|
10032630
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Filing Dt:
|
12/27/2001
|
|
Title:
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SHALLOW TRENCH ISOLATION SPACER FOR WEFF IMPROVEMENT
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Patent #:
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|
Issue Dt:
|
05/20/2003
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Application #:
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10050483
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Filing Dt:
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01/16/2002
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Title:
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CHARGE INJECTION
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|
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Patent #:
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|
Issue Dt:
|
06/03/2003
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Application #:
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10052484
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Filing Dt:
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01/18/2002
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|
Publication #:
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Pub Dt:
|
05/01/2003
| | | | |
|
Title:
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METHOD AND DEVICE FOR READING DUAL BIT MEMORY CELLS USING MULTIPLE REFERENCE CELLS WITH TWO SIDE READ
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Patent #:
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Issue Dt:
|
04/22/2003
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Application #:
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10061156
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Filing Dt:
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02/04/2002
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Publication #:
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Pub Dt:
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10/31/2002
| | | | |
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
|
04/15/2003
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Application #:
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10067765
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Filing Dt:
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02/08/2002
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Publication #:
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Pub Dt:
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06/13/2002
| | | | |
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Title:
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PLANARIZATION OF A POLYSILICON LAYER SURFACE BY CHEMICAL MECHANICAL POLISH TO IMPROVE LITHOGRAPHY AND SILICIDE FORMATION
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Patent #:
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Issue Dt:
|
06/03/2003
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Application #:
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10097924
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Filing Dt:
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03/15/2002
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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SEMICONDUCTOR MEMORY AND ITS USAGE
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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10102722
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Filing Dt:
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03/22/2002
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Publication #:
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Pub Dt:
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02/20/2003
| | | | |
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Title:
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OPERATIONAL AMPLIFIER HAVING OFFSET CANCEL FUNCTION
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10103077
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Filing Dt:
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03/20/2002
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Title:
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MEMORY DEVICE HAVING IMPROVED PROGRAMMABILITY
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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10112976
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Filing Dt:
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03/28/2002
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Title:
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A TEST STRUCTURE APPARATUS FOR MEASURING STANDBY CURRENT IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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10126330
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Filing Dt:
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04/19/2002
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Title:
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PROGRAMMING WITH FLOATING SOURCE FOR LOW POWER, LOW LEAKAGE AND HIGH DENSITY FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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10126363
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Filing Dt:
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04/19/2002
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Title:
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NOVEL METHOD TO DISTINGUISH AN STI OUTER EDGE CURRENT COMPONENT WITH AN STI NORMAL CURRENT COMPONENT
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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10143449
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Filing Dt:
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05/10/2002
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Title:
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SYSTEM FOR READING A DOUBLE-BIT MEMORY CELL
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10147622
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Filing Dt:
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05/16/2002
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Title:
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NON-VOLATILE MEMORY DIELECTRIC AS CHARGE PUMP DIELECTRIC
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10173262
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Filing Dt:
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06/17/2002
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Title:
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HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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10178106
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Filing Dt:
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06/24/2002
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Title:
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INNOVATIVE NARROW GATE FORMATION FOR FLOATING GATE FLASH TECHNOLOGY
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10179061
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Filing Dt:
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06/24/2002
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Title:
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NOVEL CAPPING LAYER
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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10180673
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Filing Dt:
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06/26/2002
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Title:
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2BIT/CELL ARCHITECTURE FOR FLOATING GATE FLASH MEMORY PRODUCT AND ASSOCIATED METHOD
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10180772
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Filing Dt:
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06/25/2002
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Title:
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CHARGE GAIN/CHARGE LOSS JUNCTION LEAKAGE PREVENTION FOR FLASH TECHNOLOGY BY USING DOUBLE ISOLATION/CAPPING LAYER BETWEEN LIGHTLY DOPED DRAIN AND GATE
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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10223195
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Filing Dt:
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08/19/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10223486
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Filing Dt:
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08/19/2002
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Title:
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SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
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|
