skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036036/0490   Pages: 153
Recorded: 06/30/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 50
1
Patent #:
Issue Dt:
11/23/2004
Application #:
08974971
Filing Dt:
11/20/1997
Title:
NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
2
Patent #:
Issue Dt:
10/26/2004
Application #:
09019409
Filing Dt:
02/05/1998
Title:
METHOD FOR FORMING ISOLATION IN FLASH MEMORY WAFER
3
Patent #:
Issue Dt:
10/26/2004
Application #:
09376659
Filing Dt:
08/18/1999
Title:
METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
4
Patent #:
Issue Dt:
11/02/2004
Application #:
09492243
Filing Dt:
01/27/2000
Title:
METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF FLASH MEMORY CELL DEVICES
5
Patent #:
Issue Dt:
09/28/2004
Application #:
09607675
Filing Dt:
06/30/2000
Title:
DUAL-PURPOSE ANTI-REFLECTIVE COATING AND SPACER FOR FLASH MEMORY AND OTHER DUAL GATE TECHNOLOGIES AND METHOD OF FORMING
6
Patent #:
Issue Dt:
11/02/2004
Application #:
09676623
Filing Dt:
10/02/2000
Title:
I/O BASED COLUMN REDUNDANCY FOR VIRTUAL GROUND WITH 2-BIT CELL FLASH MEMORY
7
Patent #:
Issue Dt:
11/30/2004
Application #:
09766001
Filing Dt:
01/19/2001
Publication #:
Pub Dt:
10/25/2001
Title:
INTERFACE APPARATUS
8
Patent #:
Issue Dt:
01/04/2005
Application #:
09825027
Filing Dt:
04/02/2001
Title:
CLOCKED BASED METHOD AND DEVICES FOR MEASURING VOLTAGE-VARIABLE CAPACITANCES AND OTHER ON-CHIP PARAMETERS
9
Patent #:
Issue Dt:
12/07/2004
Application #:
10022798
Filing Dt:
12/20/2001
Publication #:
Pub Dt:
06/26/2003
Title:
MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
10
Patent #:
Issue Dt:
10/26/2004
Application #:
10045354
Filing Dt:
11/07/2001
Title:
INNOVATIVE METHOD OF HARD MASK REMOVAL
11
Patent #:
Issue Dt:
12/28/2004
Application #:
10074495
Filing Dt:
02/11/2002
Title:
PARTIAL PAGE PROGRAMMING OF MULTI LEVEL FLASH
12
Patent #:
Issue Dt:
12/07/2004
Application #:
10101976
Filing Dt:
03/21/2002
Publication #:
Pub Dt:
04/10/2003
Title:
REGULATOR CIRCUIT AND CONTROL METHOD THEREOF
13
Patent #:
Issue Dt:
10/12/2004
Application #:
10109234
Filing Dt:
03/27/2002
Title:
LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
14
Patent #:
Issue Dt:
10/19/2004
Application #:
10120116
Filing Dt:
04/09/2002
Title:
ISOLATION TRENCH FILL PROCESS
15
Patent #:
Issue Dt:
11/23/2004
Application #:
10126193
Filing Dt:
04/19/2002
Title:
METHOD OF DETECTING AND DISTINGUISHING STACK GATE EDGE DEFECTS AT THE SOURCE OR DRAIN JUNCTION
16
Patent #:
Issue Dt:
11/30/2004
Application #:
10126814
Filing Dt:
04/19/2002
Title:
METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON THIN GATE OXIDES TO IMPROVE PERIPHERAL TRANSISTOR RELIABILITY AND PERFORMANCE FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
17
Patent #:
Issue Dt:
11/09/2004
Application #:
10136034
Filing Dt:
04/29/2002
Publication #:
Pub Dt:
10/30/2003
Title:
SYSTEM FOR CONTROL OF PRE-CHARGE LEVELS IN A MEMORY DEVICE
18
Patent #:
Issue Dt:
09/28/2004
Application #:
10136173
Filing Dt:
05/01/2002
Publication #:
Pub Dt:
11/06/2003
Title:
SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
19
Patent #:
Issue Dt:
10/19/2004
Application #:
10150255
Filing Dt:
05/15/2002
Title:
METHOD AND SYSTEM FOR SCALING NONVOLATILE MEMORY CELLS
20
Patent #:
Issue Dt:
11/02/2004
Application #:
10165383
Filing Dt:
06/06/2002
Title:
METHOD AND SYSTEM FOR DETERMINING FLOW RATES FOR CONTACT FORMATION
21
Patent #:
Issue Dt:
11/02/2004
Application #:
10197116
Filing Dt:
07/16/2002
Publication #:
Pub Dt:
01/22/2004
Title:
SYSTEM FOR USING A DYNAMIC REFERENCE IN A DOUBLE-BIT CELL MEMORY
22
Patent #:
Issue Dt:
10/26/2004
Application #:
10217403
Filing Dt:
08/14/2002
Title:
REFLOWABLE-DOPED HDP FILM
23
Patent #:
Issue Dt:
11/16/2004
Application #:
10224028
Filing Dt:
08/19/2002
Title:
METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED
24
Patent #:
Issue Dt:
12/07/2004
Application #:
10232487
Filing Dt:
08/30/2002
Title:
FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
25
Patent #:
Issue Dt:
09/28/2004
Application #:
10244369
Filing Dt:
09/16/2002
Title:
METHODS FOR FABRICATING AND PLANARIZING DUAL POLY SCALABLE SONOS FLASH MEMORY
26
Patent #:
Issue Dt:
11/09/2004
Application #:
10260061
Filing Dt:
09/27/2002
Title:
FLASH MEMORY HAVING IMPROVED CORE FIELD ISOLATION IN SELECT GATE REGIONS
27
Patent #:
Issue Dt:
12/21/2004
Application #:
10265001
Filing Dt:
10/04/2002
Title:
METHOD FOR REDUCING DRAIN INDUCED BARRIER LOWERING IN A MEMORY DEVICE
28
Patent #:
Issue Dt:
12/28/2004
Application #:
10284769
Filing Dt:
10/31/2002
Title:
SYSTEM AND METHOD OF FORMING A PASSIVE LAYER BY A CMP PROCESS
29
Patent #:
Issue Dt:
11/16/2004
Application #:
10285909
Filing Dt:
10/31/2002
Title:
MEMORY DEVICE HAVING RESISTIVE ELEMENT COUPLED TO REFERENCE CELL FOR IMPROVED RELIABILITY
30
Patent #:
Issue Dt:
09/28/2004
Application #:
10305889
Filing Dt:
11/26/2002
Publication #:
Pub Dt:
05/27/2004
Title:
MOCVD FORMATION OF CU2S
31
Patent #:
Issue Dt:
11/02/2004
Application #:
10306667
Filing Dt:
11/26/2002
Title:
METHOD OF DETERMINING CHARGE LOSS ACTIVATION ENERGY OF A MEMORY ARRAY
32
Patent #:
Issue Dt:
10/12/2004
Application #:
10308518
Filing Dt:
12/03/2002
Title:
ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
33
Patent #:
Issue Dt:
12/07/2004
Application #:
10315458
Filing Dt:
12/09/2002
Title:
DISCONTINUOUS NITRIDE STRUCTURE FOR NON-VOLATILE TRANSISTORS
34
Patent #:
Issue Dt:
10/26/2004
Application #:
10339536
Filing Dt:
01/08/2003
Title:
METHOD AND SYSTEM FOR TESTING TUNNEL OXIDE ON A MEMORY-RELATED STRUCTURE
35
Patent #:
Issue Dt:
09/28/2004
Application #:
10342032
Filing Dt:
01/14/2003
Title:
FLASH MEMORY DEVICES WITH OXYNITRIDE DIELECTRIC AS THE CHARGE STORAGE MEDIA
36
Patent #:
Issue Dt:
11/16/2004
Application #:
10389149
Filing Dt:
03/13/2003
Title:
APPARATUS AND METHOD FOR A SENSE AMPLIFIER CIRCUIT THAT SAMPLES AND HOLDS A REFERENCE VOLTAGE
37
Patent #:
Issue Dt:
11/30/2004
Application #:
10405272
Filing Dt:
04/02/2003
Title:
PHOTOSENSITIVE POLYMERIC MEMORY ELEMENTS
38
Patent #:
Issue Dt:
09/28/2004
Application #:
10406415
Filing Dt:
04/03/2003
Publication #:
Pub Dt:
10/07/2004
Title:
FAST, ACCURATE AND LOW POWER SUPPLY VOLTAGE BOOSTER USING A/D CONVERTER
39
Patent #:
Issue Dt:
10/19/2004
Application #:
10419206
Filing Dt:
04/21/2003
Publication #:
Pub Dt:
11/20/2003
Title:
FREQUENCY SYNTHESIZER CIRCUIT
40
Patent #:
Issue Dt:
11/23/2004
Application #:
10422090
Filing Dt:
04/24/2003
Title:
METHOD OF CONTROLLING PROGRAM THRESHOLD VOLTAGE DISTRIBUTION OF A DUAL CELL MEMORY DEVICE
41
Patent #:
Issue Dt:
01/04/2005
Application #:
10455310
Filing Dt:
06/06/2003
Publication #:
Pub Dt:
12/09/2004
Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
42
Patent #:
Issue Dt:
12/21/2004
Application #:
10460282
Filing Dt:
06/12/2003
Title:
STRUCTURE AND METHOD FOR PREVENTING PROCESS-INDUCED UV RADIATION DAMAGE IN A MEMORY CELL
43
Patent #:
Issue Dt:
10/12/2004
Application #:
10614484
Filing Dt:
07/07/2003
Title:
SILICON CONTAINING MATERIAL FOR PATTERNING POLYMERIC MEMORY ELEMENT
44
Patent #:
Issue Dt:
12/28/2004
Application #:
10619797
Filing Dt:
07/14/2003
Title:
PARTIALLY DE-COUPLED CORE AND PERIPHERY GATE MODULE PROCESS
45
Patent #:
Issue Dt:
10/12/2004
Application #:
10646080
Filing Dt:
08/22/2003
Title:
USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
46
Patent #:
Issue Dt:
11/02/2004
Application #:
10660420
Filing Dt:
09/10/2003
Title:
HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
47
Patent #:
Issue Dt:
01/11/2005
Application #:
10728510
Filing Dt:
12/05/2003
Title:
NEUTRON DETECTING DEVICE
48
Patent #:
Issue Dt:
11/30/2004
Application #:
10759809
Filing Dt:
01/16/2004
Title:
STRUCTURE FOR INCREASING DRIVE CURRENT IN A MEMORY ARRAY AND RELATED METHOD
49
Patent #:
Issue Dt:
11/16/2004
Application #:
10762071
Filing Dt:
01/20/2004
Title:
METHOD FOR ERASING A MEMORY SECTOR IN VIRTUAL GROUND ARCHITECTURE WITH REDUCED LEAKAGE CURRENT
50
Patent #:
Issue Dt:
12/21/2004
Application #:
10863673
Filing Dt:
06/08/2004
Title:
MEMORY DEVICE AND METHODS OF USING NEGATIVE GATE STRESS TO CORRECT OVER-ERASED MEMORY CELLS
Assignor
1
Exec Dt:
06/01/2015
Assignee
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

Search Results as of: 05/09/2024 10:05 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT