Total properties:
50
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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08974971
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Filing Dt:
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11/20/1997
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Title:
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NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09019409
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Filing Dt:
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02/05/1998
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Title:
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METHOD FOR FORMING ISOLATION IN FLASH MEMORY WAFER
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09376659
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Filing Dt:
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08/18/1999
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Title:
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METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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09492243
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Filing Dt:
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01/27/2000
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Title:
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METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF FLASH MEMORY CELL DEVICES
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09607675
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Filing Dt:
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06/30/2000
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Title:
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DUAL-PURPOSE ANTI-REFLECTIVE COATING AND SPACER FOR FLASH MEMORY AND OTHER DUAL GATE TECHNOLOGIES AND METHOD OF FORMING
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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09676623
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Filing Dt:
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10/02/2000
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Title:
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I/O BASED COLUMN REDUNDANCY FOR VIRTUAL GROUND WITH 2-BIT CELL FLASH MEMORY
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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09766001
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Filing Dt:
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01/19/2001
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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INTERFACE APPARATUS
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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09825027
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Filing Dt:
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04/02/2001
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Title:
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CLOCKED BASED METHOD AND DEVICES FOR MEASURING VOLTAGE-VARIABLE CAPACITANCES AND OTHER ON-CHIP PARAMETERS
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10022798
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Filing Dt:
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12/20/2001
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Publication #:
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Pub Dt:
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06/26/2003
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Title:
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MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10045354
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Filing Dt:
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11/07/2001
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Title:
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INNOVATIVE METHOD OF HARD MASK REMOVAL
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10074495
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Filing Dt:
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02/11/2002
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Title:
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PARTIAL PAGE PROGRAMMING OF MULTI LEVEL FLASH
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10101976
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Filing Dt:
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03/21/2002
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Publication #:
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Pub Dt:
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04/10/2003
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Title:
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REGULATOR CIRCUIT AND CONTROL METHOD THEREOF
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10109234
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Filing Dt:
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03/27/2002
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Title:
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LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10120116
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Filing Dt:
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04/09/2002
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Title:
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ISOLATION TRENCH FILL PROCESS
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10126193
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Filing Dt:
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04/19/2002
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Title:
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METHOD OF DETECTING AND DISTINGUISHING STACK GATE EDGE DEFECTS AT THE SOURCE OR DRAIN JUNCTION
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10126814
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Filing Dt:
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04/19/2002
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Title:
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METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON THIN GATE OXIDES TO IMPROVE PERIPHERAL TRANSISTOR RELIABILITY AND PERFORMANCE FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10136034
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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10/30/2003
| | | | |
Title:
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SYSTEM FOR CONTROL OF PRE-CHARGE LEVELS IN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10136173
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Filing Dt:
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05/01/2002
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Publication #:
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Pub Dt:
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11/06/2003
| | | | |
Title:
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SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10150255
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Filing Dt:
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05/15/2002
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Title:
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METHOD AND SYSTEM FOR SCALING NONVOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10165383
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Filing Dt:
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06/06/2002
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Title:
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METHOD AND SYSTEM FOR DETERMINING FLOW RATES FOR CONTACT FORMATION
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10197116
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Filing Dt:
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07/16/2002
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Publication #:
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Pub Dt:
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01/22/2004
| | | | |
Title:
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SYSTEM FOR USING A DYNAMIC REFERENCE IN A DOUBLE-BIT CELL MEMORY
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10217403
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Filing Dt:
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08/14/2002
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Title:
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REFLOWABLE-DOPED HDP FILM
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10224028
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Filing Dt:
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08/19/2002
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Title:
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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10232487
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Filing Dt:
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08/30/2002
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Title:
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FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10244369
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Filing Dt:
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09/16/2002
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Title:
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METHODS FOR FABRICATING AND PLANARIZING DUAL POLY SCALABLE SONOS FLASH MEMORY
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10260061
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Filing Dt:
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09/27/2002
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Title:
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FLASH MEMORY HAVING IMPROVED CORE FIELD ISOLATION IN SELECT GATE REGIONS
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Patent #:
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|
Issue Dt:
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12/21/2004
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Application #:
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10265001
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Filing Dt:
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10/04/2002
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Title:
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METHOD FOR REDUCING DRAIN INDUCED BARRIER LOWERING IN A MEMORY DEVICE
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|
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Patent #:
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|
Issue Dt:
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12/28/2004
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Application #:
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10284769
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Filing Dt:
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10/31/2002
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Title:
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SYSTEM AND METHOD OF FORMING A PASSIVE LAYER BY A CMP PROCESS
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|
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Patent #:
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|
Issue Dt:
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11/16/2004
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Application #:
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10285909
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Filing Dt:
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10/31/2002
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Title:
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MEMORY DEVICE HAVING RESISTIVE ELEMENT COUPLED TO REFERENCE CELL FOR IMPROVED RELIABILITY
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Patent #:
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|
Issue Dt:
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09/28/2004
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Application #:
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10305889
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Filing Dt:
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11/26/2002
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Publication #:
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Pub Dt:
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05/27/2004
| | | | |
Title:
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MOCVD FORMATION OF CU2S
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Patent #:
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|
Issue Dt:
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11/02/2004
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Application #:
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10306667
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Filing Dt:
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11/26/2002
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Title:
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METHOD OF DETERMINING CHARGE LOSS ACTIVATION ENERGY OF A MEMORY ARRAY
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Patent #:
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|
Issue Dt:
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10/12/2004
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Application #:
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10308518
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Filing Dt:
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12/03/2002
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Title:
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
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|
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10315458
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Filing Dt:
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12/09/2002
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Title:
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DISCONTINUOUS NITRIDE STRUCTURE FOR NON-VOLATILE TRANSISTORS
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10339536
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Filing Dt:
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01/08/2003
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Title:
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METHOD AND SYSTEM FOR TESTING TUNNEL OXIDE ON A MEMORY-RELATED STRUCTURE
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10342032
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Filing Dt:
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01/14/2003
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Title:
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FLASH MEMORY DEVICES WITH OXYNITRIDE DIELECTRIC AS THE CHARGE STORAGE MEDIA
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10389149
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Filing Dt:
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03/13/2003
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Title:
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APPARATUS AND METHOD FOR A SENSE AMPLIFIER CIRCUIT THAT SAMPLES AND HOLDS A REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10405272
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Filing Dt:
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04/02/2003
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Title:
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PHOTOSENSITIVE POLYMERIC MEMORY ELEMENTS
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10406415
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Filing Dt:
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04/03/2003
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Publication #:
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Pub Dt:
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10/07/2004
| | | | |
Title:
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FAST, ACCURATE AND LOW POWER SUPPLY VOLTAGE BOOSTER USING A/D CONVERTER
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10419206
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Filing Dt:
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04/21/2003
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
Title:
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FREQUENCY SYNTHESIZER CIRCUIT
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10422090
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Filing Dt:
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04/24/2003
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Title:
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METHOD OF CONTROLLING PROGRAM THRESHOLD VOLTAGE DISTRIBUTION OF A DUAL CELL MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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10455310
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Filing Dt:
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06/06/2003
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
Title:
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NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10460282
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Filing Dt:
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06/12/2003
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Title:
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STRUCTURE AND METHOD FOR PREVENTING PROCESS-INDUCED UV RADIATION DAMAGE IN A MEMORY CELL
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10614484
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Filing Dt:
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07/07/2003
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Title:
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SILICON CONTAINING MATERIAL FOR PATTERNING POLYMERIC MEMORY ELEMENT
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10619797
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Filing Dt:
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07/14/2003
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Title:
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PARTIALLY DE-COUPLED CORE AND PERIPHERY GATE MODULE PROCESS
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10646080
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Filing Dt:
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08/22/2003
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Title:
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USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10660420
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Filing Dt:
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09/10/2003
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Title:
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HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10728510
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Filing Dt:
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12/05/2003
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Title:
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NEUTRON DETECTING DEVICE
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10759809
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Filing Dt:
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01/16/2004
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Title:
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STRUCTURE FOR INCREASING DRIVE CURRENT IN A MEMORY ARRAY AND RELATED METHOD
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10762071
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Filing Dt:
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01/20/2004
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Title:
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METHOD FOR ERASING A MEMORY SECTOR IN VIRTUAL GROUND ARCHITECTURE WITH REDUCED LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10863673
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Filing Dt:
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06/08/2004
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Title:
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MEMORY DEVICE AND METHODS OF USING NEGATIVE GATE STRESS TO CORRECT OVER-ERASED MEMORY CELLS
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