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Total properties:
50
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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09492931
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Filing Dt:
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01/27/2000
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Title:
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NITRIDATED TUNNEL OXIDE BARRIERS FOR FLASH MEMORY TECHOLOGY CIRCUITRY
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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09732616
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Filing Dt:
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12/07/2000
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Title:
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INTERNAL SELF-TEST CIRCUIT FOR A MEMORY ARRAY
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Patent #:
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Issue Dt:
|
08/10/2004
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Application #:
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09768348
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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03/07/2002
| | | | |
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Title:
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CACHE SYSTEM WITH LIMITED NUMBER OF TAG MEMORY ACCESSES
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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09824345
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Filing Dt:
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04/02/2001
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Publication #:
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Pub Dt:
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05/02/2002
| | | | |
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Title:
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DOT-INVERSION DATA DRIVER FOR LIQUID CRYSTAL DISPLAY DEVICE
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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09912870
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Filing Dt:
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07/25/2001
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Publication #:
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Pub Dt:
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02/07/2002
| | | | |
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Title:
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RESOURCE LOCKING AND THREAD SYNCHRONIZATION IN A MULTIPROCESSOR ENVIRONMENT
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Patent #:
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Issue Dt:
|
09/07/2004
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Application #:
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09973767
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Filing Dt:
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10/11/2001
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
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Title:
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DIFFERENTIAL SIGNAL OUTPUT APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING THE DIFFERENTIAL SIGNAL OUTPUT APPARATUS, AND DIFFERENTIAL SIGNAL TRANSMISSION SYSTEM
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Patent #:
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Issue Dt:
|
08/03/2004
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Application #:
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10050394
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Filing Dt:
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01/16/2002
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Title:
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DIODE FABRICATION FOR ESD/EOS PROTECTION
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10073132
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Filing Dt:
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02/13/2002
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
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Title:
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LOGIC CIRCUIT FOR FAST CARRY/BORROW
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Patent #:
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Issue Dt:
|
07/27/2004
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Application #:
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10095739
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Filing Dt:
|
03/12/2002
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Title:
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LOW COLUMN LEAKAGE FLASH MEMORY ARRAY
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Patent #:
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Issue Dt:
|
08/24/2004
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Application #:
|
10096338
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Filing Dt:
|
03/11/2002
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Publication #:
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Pub Dt:
|
09/11/2003
| | | | |
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Title:
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SYSTEM FOR SETTING MEMORY VOLTAGE THRESHOLD
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|
|
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Patent #:
|
|
Issue Dt:
|
08/31/2004
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Application #:
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10113259
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Filing Dt:
|
03/28/2002
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|
Title:
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METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL TRAPPING
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/20/2004
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Application #:
|
10126840
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Filing Dt:
|
04/19/2002
|
|
Title:
|
METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON TUNNEL OXIDES USING PARTIAL NITRIDE STRIP AND SMALL BIRD'S BEAK FORMATION FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
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|
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Patent #:
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|
Issue Dt:
|
08/17/2004
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Application #:
|
10174734
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Filing Dt:
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06/18/2002
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|
Title:
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TEST STRUCTURE TO MEASURE INTERLAYER DIELECTRIC EFFECTS AND BREAKDOWN AND DETECT METAL DEFECTS IN FLASH MEMORIES
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|
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Patent #:
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|
Issue Dt:
|
08/31/2004
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Application #:
|
10179723
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Filing Dt:
|
06/25/2002
|
|
Title:
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PROCESS TO IMPROVE THE VSS LINE FORMATION FOR HIGH DENSITY FLASH MEMORY AND RELATED STRUCTURE ASSOCIATED THEREWITH
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|
|
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Patent #:
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|
Issue Dt:
|
08/03/2004
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Application #:
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10190397
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Filing Dt:
|
07/02/2002
|
|
Title:
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METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY CMP STOP LAYER FORMATION
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|
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Patent #:
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|
Issue Dt:
|
08/03/2004
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Application #:
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10226912
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Filing Dt:
|
08/22/2002
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|
Publication #:
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Pub Dt:
|
02/26/2004
| | | | |
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Title:
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PRECHARGING SCHEME FOR READING A MEMORY CELL
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|
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Patent #:
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Issue Dt:
|
07/20/2004
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Application #:
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10237805
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Filing Dt:
|
09/10/2002
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Publication #:
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Pub Dt:
|
01/09/2003
| | | | |
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Title:
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METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY AND NON-VOLATILE SEMICONDUCTOR MEMORY MANUFACTURED THEREBY
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Patent #:
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|
Issue Dt:
|
08/10/2004
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Application #:
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10243108
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Filing Dt:
|
09/13/2002
|
|
Title:
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MEMORY WORDLINE SPACER
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|
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Patent #:
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|
Issue Dt:
|
08/03/2004
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Application #:
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10254381
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Filing Dt:
|
09/25/2002
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|
Title:
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IMPLEMENTING REFERENCE CURRENT MEASUREMENT MODE WITHIN REFERENCE ARRAY PROGRAMMING MODE OR REFERENCE ARRAY ERASE MODE IN A SEMICONDUCTOR
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|
|
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Patent #:
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|
Issue Dt:
|
07/27/2004
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Application #:
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10259761
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Filing Dt:
|
09/30/2002
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|
Publication #:
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Pub Dt:
|
06/12/2003
| | | | |
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Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING PROGRAMMING VOLTAGE OF NONVOLATILE SEMICONDUCTOR MEMORY
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/24/2004
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Application #:
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10282459
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Filing Dt:
|
10/29/2002
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|
Title:
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BUFFER DRIVER CIRCUIT FOR PRODUCING A FAST, STABLE, AND ACCURATE REFERENCE VOLTAGE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10283590
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Filing Dt:
|
10/30/2002
|
|
Title:
|
METHOD FOR READING A NON-VOLATILE MEMORY CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10302672
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Filing Dt:
|
11/22/2002
|
|
Publication #:
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Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
CASCODE AMPLIFIER CIRCUIT FOR PRODUCING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10307667
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Filing Dt:
|
12/02/2002
|
|
Title:
|
SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10307749
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Filing Dt:
|
12/02/2002
|
|
Publication #:
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|
Pub Dt:
|
06/03/2004
| | | | |
|
Title:
|
PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10313494
|
Filing Dt:
|
12/05/2002
|
|
Title:
|
METHODS OF FORMING PASSIVE LAYERS IN ORGANIC MEMORY CELLS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/03/2004
|
Application #:
|
10314054
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Filing Dt:
|
12/05/2002
|
|
Title:
|
IMPLANTATION FOR THE FORMATION OF CUX LAYER IN AN ORGANIC MEMORY DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/20/2004
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Application #:
|
10327094
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Filing Dt:
|
12/24/2002
|
|
Publication #:
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Pub Dt:
|
07/10/2003
| | | | |
|
Title:
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PULSE WIDTH DETECTION CIRCUIT FILTERING THE INPUT SIGNAL AND GENERATING A BINARY SIGNAL
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/27/2004
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Application #:
|
10352658
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Filing Dt:
|
01/28/2003
|
|
Title:
|
NOVEL NON-VOLATILE MEMORY CELL AND METHOD OF PROGRAMMING FOR IMPROVED DATA RETENTION
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|
|
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Patent #:
|
|
Issue Dt:
|
08/03/2004
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Application #:
|
10353558
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Filing Dt:
|
01/29/2003
|
|
Title:
|
METHOD FOR READING A NON-VOLATILE MEMORY CELL ADJACENT TO AN INACTIVE REGION OF A NON-VOLATILE MEMORY CELL ARRAY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/20/2004
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Application #:
|
10356496
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Filing Dt:
|
02/03/2003
|
|
Publication #:
|
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Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING OUT DATA
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
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Application #:
|
10358587
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Filing Dt:
|
02/05/2003
|
|
Title:
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METHODS OF CONTROLLING VSS IMPLANTS ON MEMORY DEVICES, AND SYSTEM FOR PERFORMING SAME
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
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10358589
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Filing Dt:
|
02/05/2003
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|
Publication #:
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Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10360731
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Filing Dt:
|
02/10/2003
|
|
Publication #:
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Pub Dt:
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06/26/2003
| | | | |
|
Title:
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SEMICONDUCTOR MEMORY AND OUTPUT SIGNAL CONTROL METHOD AND CIRCUIT IN SEMICONDUCTOR MEMORY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10361378
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Filing Dt:
|
02/10/2003
|
|
Title:
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SELECTION CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/27/2004
|
Application #:
|
10364569
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Filing Dt:
|
02/10/2003
|
|
Title:
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STRUCTURE AND METHOD FOR SUPPRESSING OXIDE ENCROACHMENT IN A FLOATING GATE MEMORY CELL
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|
|
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Patent #:
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|
Issue Dt:
|
08/24/2004
|
Application #:
|
10379885
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Filing Dt:
|
03/05/2003
|
|
Title:
|
METHOD OF PROGRAMMING A MEMORY CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
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Application #:
|
10382726
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Filing Dt:
|
03/05/2003
|
|
Publication #:
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Pub Dt:
|
09/09/2004
| | | | |
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Title:
|
CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE FORMATION
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|
|
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Patent #:
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|
Issue Dt:
|
08/24/2004
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Application #:
|
10382744
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Filing Dt:
|
03/05/2003
|
|
Title:
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METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY
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|
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Patent #:
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|
Issue Dt:
|
07/20/2004
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Application #:
|
10384936
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Filing Dt:
|
03/10/2003
|
|
Title:
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METHOD AND SYSTEM FOR DETECTING DEFECTIVE MATERIAL SURROUNDING FLASH MEMORY CELLS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
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Application #:
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10418174
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Filing Dt:
|
04/18/2003
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|
Publication #:
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|
Pub Dt:
|
10/23/2003
| | | | |
|
Title:
|
AMPLIFICATION CIRCUIT AND OPTICAL COMMUNICATION APPARATUS PROVIDED WITH THE AMPLIFICATION CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
|
08/17/2004
|
Application #:
|
10422092
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Filing Dt:
|
04/24/2003
|
|
Title:
|
METHOD OF DUAL CELL MEMORY DEVICE OPERATION FOR IMPROVED END-OF-LIFE READ MARGIN
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10422276
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Filing Dt:
|
04/24/2003
|
|
Title:
|
METHOD OF PROGRAMMING AND READING A DUAL CELL MEMORY DEVICE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/10/2004
|
Application #:
|
10422489
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Filing Dt:
|
04/24/2003
|
|
Title:
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METHOD OF PROGRAMMING A DUAL CELL MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10429150
|
Filing Dt:
|
05/03/2003
|
|
Title:
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METHOD FOR REDUCING SHORT CHANNEL EFFECTS IN MEMORY CELLS AND RELATED STRUCTURE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/14/2004
|
Application #:
|
10431320
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Filing Dt:
|
05/06/2003
|
|
Title:
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NON-VOLATILE MEMORY READ CIRCUIT WITH END OF LIFE SIMULATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
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10454630
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Filing Dt:
|
06/05/2003
|
|
Publication #:
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|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
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NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA ERASING METHOD
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/20/2004
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Application #:
|
10460279
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Filing Dt:
|
06/12/2003
|
|
Title:
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STRUCTURE AND METHOD FOR PREVENTING UV RADIATION DAMAGE AND INCREASING DATA RETENTION IN MEMORY CELLS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10614397
|
Filing Dt:
|
07/07/2003
|
|
Title:
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POLYMER MEMORY DEVICE FORMED IN VIA OPENING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10635974
|
Filing Dt:
|
08/07/2003
|
|
Title:
|
MEMORY CIRCUIT FOR PROVIDING WORD LINE REDUNDANCY IN A MEMORY SECTOR
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|
