Total properties:
50
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
09266869
|
Filing Dt:
|
03/12/1999
|
Title:
|
MICROCONTROLLER HAVING PREFETCH FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
09891885
|
Filing Dt:
|
06/26/2001
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
Title:
|
ESD IMPLANT FOLLOWING SPACER DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
09904042
|
Filing Dt:
|
07/11/2001
|
Title:
|
RECESSED TUNNEL OXIDE PROFILE FOR IMPROVED RELIABILITY IN NAND DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
09960519
|
Filing Dt:
|
09/24/2001
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
Title:
|
MICROCOMPUTER WITH DEBUG SUPPORTING FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10057867
|
Filing Dt:
|
01/29/2002
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
Title:
|
MICROCONTROLLER WITH DEBUG SUPPORT UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10060185
|
Filing Dt:
|
02/01/2002
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10108341
|
Filing Dt:
|
03/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
OPERATIONAL AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10119366
|
Filing Dt:
|
04/08/2002
|
Title:
|
ERASE METHOD FOR A DUAL BIT MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10247641
|
Filing Dt:
|
09/18/2002
|
Title:
|
A MULTI-BIT SILICON NITRIDE CHARGE-TRAPPING NON-VOLATILE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10284946
|
Filing Dt:
|
10/31/2002
|
Title:
|
MULTI-CELL ORGANIC MEMORY ELEMENT AND METHODS OF OPERATING AND FABRICATING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10301649
|
Filing Dt:
|
11/22/2002
|
Publication #:
|
|
Pub Dt:
|
06/05/2003
| | | | |
Title:
|
OFFSET CANCEL CIRCUIT OF VOLTAGE FOLLOWER EQUIPPED WITH OPERATIONAL AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10305750
|
Filing Dt:
|
11/26/2002
|
Title:
|
METHOD OF PROTECTING A MEMORY ARRAY FROM CHARGE DAMAGE DURING FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10306252
|
Filing Dt:
|
11/27/2002
|
Publication #:
|
|
Pub Dt:
|
09/02/2004
| | | | |
Title:
|
METHOD AND SYSTEM FOR ERASING A NITRIDE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10331938
|
Filing Dt:
|
12/30/2002
|
Title:
|
TREATMENT OF DIELECTRIC MATERIAL TO ENHANCE ETCH RATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10359872
|
Filing Dt:
|
02/07/2003
|
Title:
|
METHOD OF FORMATION OF SEMICONDUCTOR RESISTANT TO HOT CARRIER INJECTION STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10387064
|
Filing Dt:
|
03/11/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10387774
|
Filing Dt:
|
03/12/2003
|
Title:
|
MEMORY DEVICE HAVING REVERSE LDD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2005
|
Application #:
|
10392912
|
Filing Dt:
|
03/21/2003
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY THAT IS BASED ON A VIRTUAL GROUND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10412427
|
Filing Dt:
|
04/14/2003
|
Publication #:
|
|
Pub Dt:
|
10/16/2003
| | | | |
Title:
|
METHOD FOR PREDICTING REMAINING CHARGE OF PORTABLE ELECTRONICS BATTERY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10431065
|
Filing Dt:
|
05/06/2003
|
Title:
|
METHOD TO OBTAIN TEMPERATURE INDEPENDENT PROGRAM THRESHOLD VOLTAGE DISTRIBUTION USING TEMPERATURE DEPENDENT VOLTAGE REFERENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10437896
|
Filing Dt:
|
05/15/2003
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10454517
|
Filing Dt:
|
06/05/2003
|
Title:
|
SEMICONDUTOR DEVICE HAVING CONDUCTIVE STRUCTURES FORMED NEAR A GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10616804
|
Filing Dt:
|
07/09/2003
|
Title:
|
METHOD FOR FABRICATING A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10617971
|
Filing Dt:
|
07/10/2003
|
Title:
|
PROGRAMMING OF A FLASH MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10618191
|
Filing Dt:
|
07/10/2003
|
Title:
|
FLASH MEMORY CELL HAVING REDUCED LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10618514
|
Filing Dt:
|
07/11/2003
|
Title:
|
METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING TRIPLE LDD STRUCTURE AND LOWER GATE RESISTANCE FORMED WITH A SINGLE IMPLANT PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10631812
|
Filing Dt:
|
08/01/2003
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
Title:
|
NONVOLATILE MEMORY HAVING A TRAP LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10636162
|
Filing Dt:
|
08/07/2003
|
Title:
|
TEST STRUCTURE FOR DETERMINING ELECTROMIGRATION AND INTERLAYER DIELECTRIC FAILURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10648272
|
Filing Dt:
|
08/27/2003
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ADJUSTMENT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10649994
|
Filing Dt:
|
08/28/2003
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
Title:
|
SEMICONDUCTOR MEMORY CAPABLE OF BEING DRIVEN AT LOW VOLTAGE AND ITS MANUFACTURE METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10654739
|
Filing Dt:
|
09/03/2003
|
Title:
|
PATTERNING FOR ELONGATED VSS CONTACT ON FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10655936
|
Filing Dt:
|
09/04/2003
|
Title:
|
METHOD OF FABRICATING A FLOATING GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10658506
|
Filing Dt:
|
09/09/2003
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
Title:
|
MEMORY DEVICE HAVING HIGH WORK FUNCTION GATE AND METHOD OF ERASING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10661720
|
Filing Dt:
|
09/11/2003
|
Title:
|
A FLASH MEMORY CELL WITH DRAIN AND SOURCE FORMED BY DIFFUSION OF A DOPANT FROM A SILICIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10676612
|
Filing Dt:
|
10/01/2003
|
Title:
|
ORGANIC MEMORY CELL FORMATION ON AG SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10678446
|
Filing Dt:
|
10/03/2003
|
Title:
|
EFFICIENT AND ACCURATE SENSING CIRCUIT AND TECHNIQUE FOR LOW VOLTAGE FLASH MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10684890
|
Filing Dt:
|
10/14/2003
|
Title:
|
NON VOLATILE CHARGE TRAPPING DIELECTRIC MEMORY CELL STRUCTURE WITH GATE HOLE INJECTION ERASE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10685044
|
Filing Dt:
|
10/14/2003
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10696234
|
Filing Dt:
|
10/28/2003
|
Title:
|
METHOD FOR FORMING A DIELECTRIC SPACER IN A NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10700454
|
Filing Dt:
|
11/05/2003
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
Title:
|
FREQUENCY MEASUREMENT CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10706664
|
Filing Dt:
|
11/12/2003
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10716209
|
Filing Dt:
|
11/18/2003
|
Title:
|
TIGHTLY SPACED GATE FORMATION THROUGH DAMASCENE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10716230
|
Filing Dt:
|
11/18/2003
|
Title:
|
DUAL CELL MEMORY DEVICE HAVING A TOP DIELECTRIC STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10717622
|
Filing Dt:
|
11/21/2003
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE STORING TWO-BIT INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10726508
|
Filing Dt:
|
12/04/2003
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10731494
|
Filing Dt:
|
12/09/2003
|
Title:
|
PROCESS FOR FABRICATION OF SPACER LAYER WITH REDUCED HYDROGEN CONTENT IN SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10770673
|
Filing Dt:
|
02/02/2004
|
Title:
|
BITLINE HARD MASK SPACER FLOW FOR MEMORY CELL SCALING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10821312
|
Filing Dt:
|
04/08/2004
|
Title:
|
NARROW WIDE SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10863933
|
Filing Dt:
|
06/09/2004
|
Title:
|
RAMP SOURCE HOT-HOLE PROGRAMMING FOR TRAP BASED NON-VOLATILE MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10882538
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
Title:
|
CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
|
|