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Total properties:
50
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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09727714
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Filing Dt:
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11/28/2000
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Title:
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FLASH NVROM DEVICES WITH UV CHARGE IMMUNITY
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Patent #:
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Issue Dt:
|
11/15/2005
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Application #:
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09836065
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Filing Dt:
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04/16/2001
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Publication #:
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Pub Dt:
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10/17/2002
| | | | |
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Title:
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SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS
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Patent #:
|
|
Issue Dt:
|
12/27/2005
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Application #:
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09941370
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Filing Dt:
|
08/28/2001
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Title:
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FLASH MEMORY DEVICE AND A METHOD OF FABRICATION THEREOF
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Patent #:
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Issue Dt:
|
01/24/2006
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Application #:
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10146074
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Filing Dt:
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05/16/2002
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Publication #:
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Pub Dt:
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03/27/2003
| | | | |
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Title:
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METHOD FOR ERROR DETECTION/CORRECTION OF MULTILEVEL CELL MEMORY AND MULTILEVEL CELL MEMORY HAVING ERROR DETECTION/CORRECTION FUNCTION
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Patent #:
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Issue Dt:
|
02/07/2006
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Application #:
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10283685
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Filing Dt:
|
10/29/2002
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Title:
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SEMICONDUCTOR MANUFACTURING RESOLUTION ENHANCEMENT SYSTEM AND METHOD FOR SIMULTANEOUSLY PATTERNING DIFFERENT FEATURE TYPES
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Patent #:
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Issue Dt:
|
01/31/2006
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Application #:
|
10306382
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Filing Dt:
|
11/27/2002
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Title:
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METHOD FOR PRODUCING A LOW DEFECT HOMOGENEOUS OXYNITRIDE
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Patent #:
|
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Issue Dt:
|
11/22/2005
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Application #:
|
10349106
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Filing Dt:
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01/23/2003
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Publication #:
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Pub Dt:
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08/07/2003
| | | | |
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Title:
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DC OFFSET CANCEL CIRCUIT
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Patent #:
|
|
Issue Dt:
|
10/11/2005
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Application #:
|
10358756
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Filing Dt:
|
02/05/2003
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Title:
|
REDUCED SILICON GOUGING AND COMMON SOURCE LINE RESISTANCE IN SEMICONDUCTOR DEVICES
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|
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Patent #:
|
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Issue Dt:
|
11/29/2005
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Application #:
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10404081
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Filing Dt:
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04/02/2003
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Publication #:
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Pub Dt:
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10/23/2003
| | | | |
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Title:
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SEMICONDUCTOR DEVICE LOW TEMPERATURE TEST APPARATUS USING ELECTRONIC COOLING ELEMENT
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|
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Patent #:
|
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Issue Dt:
|
10/18/2005
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Application #:
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10413800
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Filing Dt:
|
04/15/2003
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
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Title:
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METHOD OF PROGRAMMING DUAL CELL MEMORY DEVICE TO STORE MULTIPLE DATA STATES PER CELL
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/01/2005
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Application #:
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10436786
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Filing Dt:
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05/13/2003
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|
Publication #:
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Pub Dt:
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11/18/2004
| | | | |
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Title:
|
ERASING AND PROGRAMMING AN ORGANIC MEMORY DEVICE AND METHOD OF FABRICATING
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|
|
|
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Patent #:
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|
Issue Dt:
|
12/20/2005
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Application #:
|
10452877
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Filing Dt:
|
06/02/2003
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|
Publication #:
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Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
PLANAR POLYMER MEMORY DEVICE
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|
|
|
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Patent #:
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Issue Dt:
|
11/08/2005
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Application #:
|
10459576
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Filing Dt:
|
06/12/2003
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Publication #:
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Pub Dt:
|
12/16/2004
| | | | |
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Title:
|
NON-VOLATILE MEMORY DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10603136
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Filing Dt:
|
06/23/2003
|
|
Title:
|
SIMULTANEOUS EXECUTION COMMAND MODES IN A FLASH MEMORY DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10614066
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Filing Dt:
|
07/08/2003
|
|
Publication #:
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Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE FOR DIFFERENTIAL DATA AMPLIFICATION AND METHOD THEREFOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10634042
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Filing Dt:
|
08/04/2003
|
|
Title:
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A METHOD OF FABRICATING A DUAL-LEVEL STACKED FLASH MEMORY CELL WITH A MOSFET STORAGE TRANSISTOR
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|
|
|
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Patent #:
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Issue Dt:
|
01/24/2006
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Application #:
|
10634857
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Filing Dt:
|
08/06/2003
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|
Publication #:
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Pub Dt:
|
02/26/2004
| | | | |
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Title:
|
DESIGN METHOD FOR INTEGRATED CIRCUIT HAVING SCAN FUNCTION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10635781
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Filing Dt:
|
08/06/2003
|
|
Title:
|
MEMORY DEVICE HAVING SILICIDED BITLINES AND METHOD OF FORMING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10650049
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Filing Dt:
|
08/26/2003
|
|
Title:
|
CAM (CONTENT ADDRESSABLE MEMORY) CELLS AS PART OF CORE ARRAY IN FLASH MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10650072
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Filing Dt:
|
08/28/2003
|
|
Publication #:
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|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A MEMORY INTEGRATED CIRCUIT DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10655179
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Filing Dt:
|
09/04/2003
|
|
Title:
|
MEMORY CELL STRUCTURE HAVING NITRIDE LAYER WITH REDUCED CHARGE LOSS AND METHOD FOR FABRICATING SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10677031
|
Filing Dt:
|
10/01/2003
|
|
Title:
|
MEMORY DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10677073
|
Filing Dt:
|
10/01/2003
|
|
Title:
|
MEMORY DEVICE AND METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10677790
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Filing Dt:
|
10/02/2003
|
|
Publication #:
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|
Pub Dt:
|
04/07/2005
| | | | |
|
Title:
|
MEMORY DEVICE AND METHOD USING POSITIVE GATE STRESS TO RECOVER OVERERASED CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10679179
|
Filing Dt:
|
10/03/2003
|
|
Title:
|
CIRCUIT AND TECHNIQUE FOR ACCURATELY SENSING LOW VOLTAGE FLASH MEMORY DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10679774
|
Filing Dt:
|
10/06/2003
|
|
Title:
|
FLASH MEMORY DEVICE AND METHOD OF FABRICATION THEREOF INCLUDING A BOTTOM OXIDE LAYER WITH TWO REGIONS WITH DIFFERENT CONCENTRATIONS OF NITROGEN
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10683631
|
Filing Dt:
|
10/10/2003
|
|
Title:
|
RECESSED CHANNEL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
|
Application #:
|
10683649
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Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
RECESS CHANNEL FLASH ARCHITECTURE FOR REDUCED SHORT CHANNEL EFFECT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10700021
|
Filing Dt:
|
11/03/2003
|
|
Title:
|
MEMORY ELEMENT FORMATION WITH PHOTOSENSITIVE POLYMER DIELECTRIC
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10703860
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Filing Dt:
|
11/07/2003
|
|
Title:
|
METHOD AND SYSTEM FOR TESTING ARTICLES OF MANUFACTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10718707
|
Filing Dt:
|
11/24/2003
|
|
Title:
|
METHODS FOR FORMING NITROGEN-RICH REGIONS IN NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10721643
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Filing Dt:
|
11/24/2003
|
|
Title:
|
READING FLASH MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10726829
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Filing Dt:
|
12/03/2003
|
|
Title:
|
POST CMP PRECURSOR TREATMENT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/08/2005
|
Application #:
|
10729732
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Filing Dt:
|
12/05/2003
|
|
Title:
|
HARD MASK SPACER FOR SUBLITHOGRAPHIC BITLINE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10731659
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Filing Dt:
|
12/09/2003
|
|
Title:
|
PROCESS FOR FABRICATION OF NITRIDE LAYER WITH REDUCED HYDROGEN CONTENT IN ONO STRUCTURE IN SEMICONDUCTOR DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
10738301
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Filing Dt:
|
12/16/2003
|
|
Title:
|
METHOD AND DEVICE FOR PROGRAMMING CELLS IN A MEMORY ARRAY IN A NARROW DISTRIBUTION
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/13/2005
|
Application #:
|
10743188
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Filing Dt:
|
12/23/2003
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|
Publication #:
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Pub Dt:
|
07/15/2004
| | | | |
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Title:
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SPREAD SPECTRUM CLOCK GENERATION CIRCUIT, JITTER GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
11/29/2005
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Application #:
|
10747692
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Filing Dt:
|
12/30/2003
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|
Publication #:
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|
Pub Dt:
|
09/16/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
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Application #:
|
10755740
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Filing Dt:
|
01/12/2004
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|
Publication #:
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Pub Dt:
|
07/14/2005
| | | | |
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Title:
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POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL
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|
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Patent #:
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|
Issue Dt:
|
01/17/2006
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Application #:
|
10768188
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Filing Dt:
|
02/02/2004
|
|
Publication #:
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|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10770010
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Filing Dt:
|
02/03/2004
|
|
Title:
|
NON -VOLATILE MEMORY DEVICE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/24/2006
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Application #:
|
10770260
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Filing Dt:
|
02/02/2004
|
|
Title:
|
FLASH MEMORY CELL WITH UV PROTECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
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Application #:
|
10843289
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Filing Dt:
|
05/11/2004
|
|
Publication #:
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Pub Dt:
|
11/17/2005
| | | | |
|
Title:
|
BITLINE IMPLANT UTILIZING DUAL POLY
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|
|
|
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Patent #:
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|
Issue Dt:
|
12/27/2005
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Application #:
|
10848679
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Filing Dt:
|
05/19/2004
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|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/07/2006
|
Application #:
|
10878091
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Filing Dt:
|
06/28/2004
|
|
Publication #:
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|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
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MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10883924
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Filing Dt:
|
07/01/2004
|
|
Title:
|
FLOATING GATE SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
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|
|
|
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Patent #:
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|
Issue Dt:
|
01/17/2006
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Application #:
|
10885268
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Filing Dt:
|
07/06/2004
|
|
Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
|
Title:
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METHOD OF IMPROVING ERASE VOLTAGE DISTRIBUTION FOR A FLASH MEMORY ARRAY HAVING DUMMY WORDLINES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
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10889424
|
Filing Dt:
|
07/12/2004
|
|
Title:
|
ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10919119
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Filing Dt:
|
08/16/2004
|
|
Title:
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TEST STRUCTURE FOR CHARACTERIZING JUNCTION LEAKAGE CURRENT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/15/2005
|
Application #:
|
11029454
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Filing Dt:
|
01/06/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
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Title:
|
SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE CONTROL METHOD
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|
