Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 036132/0780 | |
| Pages: | 3 |
| | Recorded: | 07/20/2015 | | |
| Attorney Dkt #: | 2163.4001 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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09/06/2016
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Application #:
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14619494
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Filing Dt:
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02/11/2015
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Publication #:
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Pub Dt:
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09/10/2015
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Title:
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LAYOUT VERIFICATION METHOD AND VERIFICATION APPARATUS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14621545
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Filing Dt:
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02/13/2015
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Publication #:
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Pub Dt:
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07/02/2015
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Title:
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SECURE PROCESSOR SYSTEM WITHOUT NEED FOR MANUFACTURER AND USER TO KNOW ENCRYPTION INFORMATION OF EACH OTHER
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Patent #:
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Issue Dt:
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05/23/2017
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Application #:
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14629910
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Filing Dt:
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02/24/2015
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Publication #:
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Pub Dt:
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10/01/2015
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Title:
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DESIGN METHOD AND DESIGN APPARATUS
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Assignee
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| 2-10-23, SHIN-YOKOHAMA, KOHOKU-KU |
| YOKOHAMA-SHI, KANAGAWA, JAPAN 222-0033 |
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Correspondence name and address
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STAAS & HALSEY LLP
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1201 NEW YORK AVE.
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SUITE 700
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WASHINGTON, DC 20005
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