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Reel/Frame:036293/0932   Pages: 10
Recorded: 08/06/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 107
Page 1 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
01/12/1999
Application #:
08825312
Filing Dt:
03/28/1997
Title:
FLEXIBLE FUSE PLACEMENT IN REDUNANT SEMICONDUCTOR MEMORY
2
Patent #:
Issue Dt:
07/20/1999
Application #:
08829255
Filing Dt:
03/31/1997
Title:
METHOD FOR FORMING A STRUCTURE
3
Patent #:
Issue Dt:
12/29/1998
Application #:
08829257
Filing Dt:
03/31/1997
Title:
METHOD FOR FORMING METALLIZATION IN SEMICONDUCTOR DEVICES WITH A SELF- PLANARIZING MATERIAL
4
Patent #:
Issue Dt:
02/15/2000
Application #:
08829371
Filing Dt:
03/31/1997
Title:
DEVICE WITH ASYMMETRICAL CHANNEL DOPANT PROFILE
5
Patent #:
Issue Dt:
02/15/2000
Application #:
08829575
Filing Dt:
03/31/1997
Title:
ETCHING OF CONTACT HOLES
6
Patent #:
Issue Dt:
10/05/1999
Application #:
08846924
Filing Dt:
04/30/1997
Title:
METHOD OF PLANARIZING THE SEMICONDUCTOR STRUCTURE
7
Patent #:
Issue Dt:
12/10/2002
Application #:
08846925
Filing Dt:
04/30/1997
Title:
INTEGRATED CIRCUITS AND MANUFACTURING METHODS
8
Patent #:
Issue Dt:
12/14/1999
Application #:
08868555
Filing Dt:
06/04/1997
Title:
METHOD FOR FORMING A CAPACITAR
9
Patent #:
Issue Dt:
11/03/1998
Application #:
08879726
Filing Dt:
06/20/1997
Title:
IMPROVED REDUNDANT CIRCUITS AND METHODS THEREFOR
10
Patent #:
Issue Dt:
06/13/2000
Application #:
08882057
Filing Dt:
06/25/1997
Title:
METHOD OF REDUCING THE FORMATION OF WATERMARKS ON SEMICONDUCTOR WAFERS
11
Patent #:
Issue Dt:
07/21/1998
Application #:
08883356
Filing Dt:
06/26/1997
Title:
INTEGRATED CIRCUIT DEVICES INCLUDING SHALLOW TRENCH ISOLATION
12
Patent #:
Issue Dt:
03/23/1999
Application #:
08884118
Filing Dt:
06/27/1997
Title:
IMPROVED CHEMICAL MECHANICAL POLISHING PAD CONDITIONER
13
Patent #:
Issue Dt:
06/22/1999
Application #:
08884119
Filing Dt:
06/27/1997
Title:
MITIGATION OF CMP-INDUCED BPSG SURFACE DAMAGE BY AN INTEGRATED ANNEAL AND SILICON DIOXIDE DEPOSITION
14
Patent #:
Issue Dt:
03/07/2000
Application #:
08884729
Filing Dt:
06/30/1997
Title:
IMPROVED DUAL DAMASCENE STRUCTURE
15
Patent #:
Issue Dt:
04/18/2000
Application #:
08884732
Filing Dt:
06/30/1997
Title:
FORMATION OF SUB-GROUNDRULE FEATURES
16
Patent #:
Issue Dt:
11/03/1998
Application #:
08884854
Filing Dt:
06/30/1997
Title:
TECHNIQUES FOR REDUCING REDUNDANT ELEMENT FUSES IN A DYNAMIC RANDOM ACCESS MEMORY ARRAY
17
Patent #:
Issue Dt:
02/23/1999
Application #:
08884855
Filing Dt:
06/30/1997
Title:
DYNAMIC ACCESS MEMORY EQUALIZER CIRCUITS AND METHODS THEREFOR
18
Patent #:
Issue Dt:
08/10/1999
Application #:
08884860
Filing Dt:
06/30/1997
Title:
CMOS INTEGRATED CIRCUITS WITH REDUCED SUBSTRATE DEFECTS
19
Patent #:
Issue Dt:
10/09/2001
Application #:
08884861
Filing Dt:
06/30/1997
Title:
METHOD OF FORMING MULTI-LEVEL COPLANAR METAL/INSULATOR FILMS USING DUAL DAMASCENE WITH SACRIFICIAL FLOWABLE OXIDE
20
Patent #:
Issue Dt:
03/30/1999
Application #:
08885329
Filing Dt:
06/30/1997
Title:
OCD WITH LOW OUTPUT CAPACITANCE
21
Patent #:
Issue Dt:
10/12/1999
Application #:
08901986
Filing Dt:
07/29/1997
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE HAVING A CRYSTALLINE LAYER
22
Patent #:
Issue Dt:
02/09/1999
Application #:
08923300
Filing Dt:
09/04/1997
Title:
TEMPERATURE INDEPENDENT OSCILLATOR
23
Patent #:
Issue Dt:
11/10/1998
Application #:
08923459
Filing Dt:
09/04/1997
Title:
DIMENSION PROGRAMMABLE FUSEBANKS AND METHODS FOR MAKING THE SAME
24
Patent #:
Issue Dt:
03/07/2000
Application #:
08932925
Filing Dt:
09/19/1997
Title:
APPARATUS AND METHOD FOR HIGH-SPEED WORDLINE DRIVING WITH LOW AREA OVERHEAD
25
Patent #:
Issue Dt:
06/20/2000
Application #:
08937570
Filing Dt:
09/25/1997
Title:
SEMICONDUCTOR MEMORY HAVING REDUNDANCY CIRCUIT
26
Patent #:
Issue Dt:
09/28/1999
Application #:
08937571
Filing Dt:
09/25/1997
Title:
A METHOD AND APPARATUS FOR REDUCING THE BIAS CURRENT IN A REFERENCE VOLTAGE CIRCUIT
27
Patent #:
Issue Dt:
05/30/2000
Application #:
08937764
Filing Dt:
09/25/1997
Title:
METHOD OF MAXIMIZING CHIP YIELD FOR SEMICONDUCTOR WAFERS
28
Patent #:
Issue Dt:
10/24/2000
Application #:
08937781
Filing Dt:
09/25/1997
Title:
METHOD OF FABRICATING SEMICONDUCTOR CHIPS WITH SILICIDE AND IMPLANTED JUNCTIONS
29
Patent #:
Issue Dt:
04/04/2000
Application #:
08938072
Filing Dt:
09/26/1997
Title:
METALIZATION SYSTEM HAVING AN ENHANCED THERMAL CONDUCTIVITY
30
Patent #:
Issue Dt:
08/10/1999
Application #:
08939148
Filing Dt:
09/29/1997
Title:
DEPOSITION OF CARBON INTO NITRIDE LAYER FOR IMPROVED SELECTIVITY OF OXIDE TO NITRIDE ETCHRATE FOR SELF ALIGNED CONTACT ETCHING
31
Patent #:
Issue Dt:
11/02/1999
Application #:
08939208
Filing Dt:
09/29/1997
Title:
MULTI-LEVEL CONDUCTIVE STRUCTURE INCLUDING LOW CAPACITANCE MATERIAL
32
Patent #:
Issue Dt:
09/28/1999
Application #:
08939546
Filing Dt:
09/29/1997
Title:
APPARATUS AND METHOD FOR IMPLEMENTING A BANK INTERLOCK SCHEME AND RELATED TEST MODE FOR MULTIBANK MEMORY DEVICES
33
Patent #:
Issue Dt:
05/15/2001
Application #:
08940806
Filing Dt:
09/30/1997
Title:
METHODS FOR PERFORMING PLANARIZATION AND RECESS ETCHES AND APPARATUS THEREFOR
34
Patent #:
Issue Dt:
07/13/1999
Application #:
08940861
Filing Dt:
09/29/1997
Title:
SPACE-EFFICIENT SEMICONDUCTOR MEMORY HAVING HIERARCHICAL COLUMN SELECT LINE ARCHITECTURE
35
Patent #:
Issue Dt:
08/17/1999
Application #:
08940862
Filing Dt:
09/29/1997
Title:
CONSTANT CURRENT CMOS OUTPUT DRIVER CIRCUIT WITH DUAL GATE TRANSISTOR DEVICES
36
Patent #:
Issue Dt:
09/21/1999
Application #:
08941093
Filing Dt:
09/30/1997
Title:
ENDPOINT DETECTION METHOD AND APPARATUS
37
Patent #:
Issue Dt:
02/02/1999
Application #:
08943910
Filing Dt:
09/30/1997
Title:
REDUCING OXIDATION STRESS IN THE FABRICATION OF DEVICES
38
Patent #:
Issue Dt:
05/16/2000
Application #:
08999926
Filing Dt:
06/23/1997
Title:
CONTROL OF CRITICAL DIMENSIONS THROUGH MEASUREMENT OF ABOSRBED RADIATION
39
Patent #:
Issue Dt:
06/15/1999
Application #:
09067766
Filing Dt:
04/29/1998
Title:
METHOD FOR PRODUCING A CMOS CIRCUIT
40
Patent #:
Issue Dt:
07/03/2001
Application #:
09071798
Filing Dt:
05/04/1998
Title:
DRAM CELL CONFIGURATION AND METHOD FOR ITS PRODUCTION
41
Patent #:
Issue Dt:
04/23/2002
Application #:
09079020
Filing Dt:
05/14/1998
Title:
INTEGRATED CIRCUIT HAVING AT LEAST TWO VERTICAL MOS TRANSISTORS AND METHOD FOR MANUFACTURING SAME
42
Patent #:
Issue Dt:
04/11/2000
Application #:
09089539
Filing Dt:
06/03/1998
Title:
DRAM CELL ARRANGEMENT HAVING DYNAMIC SELF-AMPLIFYING MEMORY CELLS, AND METHOD FOR MANUFACTURING SAME
43
Patent #:
Issue Dt:
07/11/2000
Application #:
09093572
Filing Dt:
06/08/1998
Title:
DRAM CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
44
Patent #:
Issue Dt:
05/16/2000
Application #:
09095261
Filing Dt:
06/10/1998
Title:
CIRCUIT CONFIGURATION FOR GENERATING DIGITAL SIGNALS
45
Patent #:
Issue Dt:
08/08/2000
Application #:
09106237
Filing Dt:
06/29/1998
Title:
METHOD OF PRODUCING A BARRIER LAYER IN A SEMICONDUCTOR BODY
46
Patent #:
Issue Dt:
02/13/2001
Application #:
09115618
Filing Dt:
07/13/1998
Title:
REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORIES
47
Patent #:
Issue Dt:
11/14/2000
Application #:
09128387
Filing Dt:
08/03/1998
Title:
CONFIGURATION FOR THE AUTOMATIC INSCRIPTION OR REINSCRIPTION OF WAFERS
48
Patent #:
Issue Dt:
10/02/2001
Application #:
09128388
Filing Dt:
08/03/1998
Title:
STRUCTURING PROCESS
49
Patent #:
Issue Dt:
09/24/2002
Application #:
09128389
Filing Dt:
08/03/1998
Title:
STRUCTURING METHOD
50
Patent #:
Issue Dt:
05/09/2000
Application #:
09128806
Filing Dt:
08/04/1998
Title:
DATABUS
51
Patent #:
Issue Dt:
09/03/2002
Application #:
09128807
Filing Dt:
08/04/1998
Title:
METHOD AND CIRCUIT CONFIGURATION FOR PROCESSING DIGITAL SIGNALS
52
Patent #:
Issue Dt:
08/01/2000
Application #:
09133704
Filing Dt:
08/13/1998
Title:
CIRCUIT APPARATUS FOR EVALUATING THE DATA CONTENT OF MEMORY CELLS
53
Patent #:
Issue Dt:
11/06/2001
Application #:
09133893
Filing Dt:
08/14/1998
Title:
SEMICONDUCTOR COMPONENT AND METHOD FOR TESTING AND OPERATING A SEMICONDUCTOR COMPONENT
54
Patent #:
Issue Dt:
05/09/2000
Application #:
09138160
Filing Dt:
08/21/1998
Title:
CIRCUIT ARRANGEMENT WITH AT LEAST FOUR TRANSISTORS, AND METHOD FOR THE MANUFACTURE THEREOF
55
Patent #:
Issue Dt:
01/09/2001
Application #:
09140972
Filing Dt:
08/27/1998
Title:
DRAM CELL ARRANGEMENT AND METHOD FOR THE MANUFACTURE THEREOF
56
Patent #:
Issue Dt:
01/30/2001
Application #:
09143122
Filing Dt:
08/28/1998
Title:
FUSE CONFIGURATION FOR A SEMICONDUCTOR STORAGE DEVICE
57
Patent #:
Issue Dt:
11/13/2001
Application #:
09146636
Filing Dt:
09/03/1998
Title:
STRUCTURING METHOD
58
Patent #:
Issue Dt:
04/03/2001
Application #:
09149829
Filing Dt:
09/08/1998
Title:
METHOD FOR PRODUCING STRUCTURES HAVING A HIGH ASPECT RATIO AND STRUCTURE HAVING A HIGH ASPECT RATIO
59
Patent #:
Issue Dt:
11/30/1999
Application #:
09150789
Filing Dt:
09/10/1998
Title:
LEVEL CONVERTING CIRCUIT
60
Patent #:
Issue Dt:
05/30/2000
Application #:
09160851
Filing Dt:
09/25/1998
Title:
CIRCUIT CONFIGURATION FOR REDUCING DISTURBANCES DUE TO A SWITCHING OF AN OUTPUT DRIVER
61
Patent #:
Issue Dt:
03/28/2000
Application #:
09160862
Filing Dt:
09/25/1998
Title:
PULSE SHAPER CIRCUIT
62
Patent #:
Issue Dt:
12/07/1999
Application #:
09160875
Filing Dt:
09/24/1998
Title:
O-AMINO (THIO) PHENOLCARBOXYLIC ACIDS AND THEIR PREPARATION
63
Patent #:
Issue Dt:
11/30/1999
Application #:
09160880
Filing Dt:
09/25/1998
Title:
RS FLIP-FLOP WITH ENABLE INPUTS
64
Patent #:
Issue Dt:
11/21/2000
Application #:
09161144
Filing Dt:
09/24/1998
Title:
BIS-O-AMINO(THIO)PHENOLS, AND THEIR PREPARATION
65
Patent #:
Issue Dt:
10/30/2001
Application #:
09161147
Filing Dt:
09/24/1998
Title:
O-AMINO (THIO) PHENOLCARBOXYLIC ACIDS, AND THEIR PREPARATION
66
Patent #:
Issue Dt:
11/28/2000
Application #:
09161148
Filing Dt:
09/24/1998
Title:
POLYBENZOXAZOLE AND POLYBENZOTHIAZOLE PRECURSORS
67
Patent #:
Issue Dt:
11/20/2001
Application #:
09161149
Filing Dt:
09/24/1998
Title:
O-NITRO(THIO)PHENOL DERIVATIVES, AND THEIR PREPARATION
68
Patent #:
Issue Dt:
09/19/2000
Application #:
09161202
Filing Dt:
09/24/1998
Title:
POLYBENZOXAZOLE AND POLYBENZOTHIAZOLE PRECURSORS
69
Patent #:
Issue Dt:
12/05/2000
Application #:
09161549
Filing Dt:
09/24/1998
Title:
BIS-O-AMINO (THIO) PHENOLS, AND THEIR PREPARATION
70
Patent #:
Issue Dt:
12/12/2000
Application #:
09162608
Filing Dt:
09/29/1998
Title:
ASSOCIATIVE MEMORY AND METHOD FOR THE OPERATION THEREOF
71
Patent #:
Issue Dt:
03/02/2004
Application #:
09163874
Filing Dt:
09/30/1998
Title:
METHOD FOR THE LINEAR CONFIGURATION OF METALLIC FUSE SECTIONS ON WAFERS
72
Patent #:
Issue Dt:
12/05/2000
Application #:
09164115
Filing Dt:
09/30/1998
Title:
PROCESS FOR PRODUCING A CERAMIC LAYER
73
Patent #:
Issue Dt:
10/03/2000
Application #:
09164119
Filing Dt:
09/30/1998
Title:
PROCESS FOR PRODUCING A CERAMIC LAYER CONTAINING BI
74
Patent #:
Issue Dt:
08/27/2002
Application #:
09176558
Filing Dt:
10/21/1998
Title:
INTEGRATED CIRCUIT CONFIGURATION HAVING AT LEAST ONE CAPACITOR AND METHOD FOR PRODUCING THE SAME
75
Patent #:
Issue Dt:
11/02/1999
Application #:
09191482
Filing Dt:
11/13/1998
Title:
DRAM CELL ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
76
Patent #:
Issue Dt:
01/18/2000
Application #:
09197391
Filing Dt:
11/20/1998
Title:
MICROSTRUCTURE AND METHODS FOR FABRICATING SUCH STRUCTURE
77
Patent #:
Issue Dt:
03/14/2000
Application #:
09200071
Filing Dt:
11/25/1998
Title:
SRAM CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
78
Patent #:
Issue Dt:
01/09/2001
Application #:
09201728
Filing Dt:
11/30/1998
Title:
CHEMICALLY AMPLIFIED RESIST
79
Patent #:
Issue Dt:
06/24/2003
Application #:
09201733
Filing Dt:
11/30/1998
Title:
MEMORY CELL USING AMORPHOUS MATERIAL TO STABILIZE THE BOUNDARY FACE BETWEEN POLYCHRYSTALLINE SEMICONDUCTOR MATERIAL OF A CAPACITOR AND MONCRYSTALLINE SEMICONDUCTOR MATERIAL OF A TRANSISTOR
80
Patent #:
Issue Dt:
03/12/2002
Application #:
09251616
Filing Dt:
02/17/1999
Title:
DEVICE WITH ASYMMETRICAL CHANNEL DOPANT PROFILE
81
Patent #:
Issue Dt:
09/17/2002
Application #:
09281021
Filing Dt:
03/30/1999
Title:
REDUCED SIGNAL TEST FOR DYNAMIC RANDOM ACCESS MEMORY
82
Patent #:
Issue Dt:
08/01/2000
Application #:
09388274
Filing Dt:
09/01/1999
Title:
O-AMINO(THIO) PHENOLCARBOXYLIC ACIDS, AND THEIR PREPARATION
83
Patent #:
Issue Dt:
02/11/2003
Application #:
09423864
Filing Dt:
11/15/1999
Title:
INTEGRATED CMOS CIRCUIT CONFIGURATION, AND PRODUCTION OF SAME
84
Patent #:
Issue Dt:
04/16/2002
Application #:
09438305
Filing Dt:
09/13/1999
Title:
BACKING FILM FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OF A SEMICONDUCTOR WAFER
85
Patent #:
Issue Dt:
10/24/2000
Application #:
09450403
Filing Dt:
11/29/1999
Title:
INPUT CIRCUIT FOR AN INTEGRATED CIRCUIT
86
Patent #:
Issue Dt:
07/05/2005
Application #:
09462994
Filing Dt:
01/14/2000
Title:
INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR THE MANUFACTURE THEREOF
87
Patent #:
Issue Dt:
08/21/2001
Application #:
09465726
Filing Dt:
12/17/1999
Title:
CONFIGURATION OF MEMORY CELLS AND METHOD OF CHECKING THE OPERATION OF MEMORY CELLS
88
Patent #:
Issue Dt:
10/30/2001
Application #:
09472221
Filing Dt:
12/27/1999
Title:
SEMICONDUCTOR CIRCUIT APPARATUS AND METHOD FOR FABRICATING THE SEMICONDUCTOR CIRCUIT APPARATUS
89
Patent #:
Issue Dt:
01/08/2002
Application #:
09487411
Filing Dt:
01/18/2000
Title:
Method of producing a vertical mos transistor
90
Patent #:
Issue Dt:
09/10/2002
Application #:
09491296
Filing Dt:
01/25/2000
Title:
POLISHING AGENT FOR SEMICONDUCTOR SUBSTRATES
91
Patent #:
Issue Dt:
10/16/2001
Application #:
09494775
Filing Dt:
01/31/2000
Title:
READ-ONLY MEMORY AND FABRICATION METHOD
92
Patent #:
Issue Dt:
07/17/2001
Application #:
09495795
Filing Dt:
02/01/2000
Title:
Wafer marking
93
Patent #:
Issue Dt:
05/28/2002
Application #:
09498532
Filing Dt:
02/04/2000
Title:
Integrated electrical circuit with passivation layer
94
Patent #:
Issue Dt:
05/14/2002
Application #:
09521396
Filing Dt:
03/08/2000
Title:
Digital circuit having a filter unit for suppressing glitches
95
Patent #:
Issue Dt:
12/03/2002
Application #:
09528159
Filing Dt:
03/17/2000
Title:
MEMORY CELL CONFIGURATION, MAGNETIC RAM, AND ASSOCIATIVE MEMORY
96
Patent #:
Issue Dt:
07/09/2002
Application #:
09528268
Filing Dt:
03/17/2000
Title:
MEMORY CELL CONFIGURATION AND FABRICATION METHOD
97
Patent #:
Issue Dt:
02/20/2001
Application #:
09528424
Filing Dt:
03/17/2000
Title:
Dynamic memory having two modes of operation
98
Patent #:
Issue Dt:
03/27/2001
Application #:
09536029
Filing Dt:
03/27/2000
Title:
Digital memory and method of operation for a digital memory
99
Patent #:
Issue Dt:
06/25/2002
Application #:
09539235
Filing Dt:
03/30/2000
Title:
PRODUCT INCLUDING A SILICON-CONTAINING FUNCTIONAL LAYER AND AN INSULATING LAYER MADE OF SILICON DIOXIDE, AND METHOD FABRICATING THE PRODUCT
100
Patent #:
Issue Dt:
10/22/2002
Application #:
09539237
Filing Dt:
03/30/2000
Title:
METHOD OF PRODUCING AN OPEN FORM
Assignor
1
Exec Dt:
07/08/2015
Assignee
1
29 EARLSFORT TERRACE, DUBLIN 2
DUBLIN, IRELAND
Correspondence name and address
POLARIS INNOVATIONS LIMITED
303 TERRY FOX DRIVE, SUITE 300
OTTAWA, K2K 3J1 CANADA

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