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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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08825312
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Filing Dt:
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03/28/1997
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Title:
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FLEXIBLE FUSE PLACEMENT IN REDUNANT SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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07/20/1999
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Application #:
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08829255
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Filing Dt:
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03/31/1997
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Title:
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METHOD FOR FORMING A STRUCTURE
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Patent #:
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Issue Dt:
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12/29/1998
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Application #:
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08829257
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Filing Dt:
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03/31/1997
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Title:
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METHOD FOR FORMING METALLIZATION IN SEMICONDUCTOR DEVICES WITH A SELF- PLANARIZING MATERIAL
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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08829371
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Filing Dt:
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03/31/1997
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Title:
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DEVICE WITH ASYMMETRICAL CHANNEL DOPANT PROFILE
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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08829575
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Filing Dt:
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03/31/1997
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Title:
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ETCHING OF CONTACT HOLES
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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08846924
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Filing Dt:
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04/30/1997
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Title:
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METHOD OF PLANARIZING THE SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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08846925
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Filing Dt:
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04/30/1997
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Title:
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INTEGRATED CIRCUITS AND MANUFACTURING METHODS
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08868555
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Filing Dt:
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06/04/1997
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Title:
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METHOD FOR FORMING A CAPACITAR
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08879726
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Filing Dt:
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06/20/1997
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Title:
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IMPROVED REDUNDANT CIRCUITS AND METHODS THEREFOR
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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08882057
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Filing Dt:
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06/25/1997
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Title:
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METHOD OF REDUCING THE FORMATION OF WATERMARKS ON SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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07/21/1998
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Application #:
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08883356
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Filing Dt:
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06/26/1997
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Title:
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INTEGRATED CIRCUIT DEVICES INCLUDING SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08884118
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Filing Dt:
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06/27/1997
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Title:
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IMPROVED CHEMICAL MECHANICAL POLISHING PAD CONDITIONER
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08884119
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Filing Dt:
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06/27/1997
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Title:
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MITIGATION OF CMP-INDUCED BPSG SURFACE DAMAGE BY AN INTEGRATED ANNEAL AND SILICON DIOXIDE DEPOSITION
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08884729
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Filing Dt:
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06/30/1997
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Title:
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IMPROVED DUAL DAMASCENE STRUCTURE
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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08884732
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Filing Dt:
|
06/30/1997
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Title:
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FORMATION OF SUB-GROUNDRULE FEATURES
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Patent #:
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Issue Dt:
|
11/03/1998
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Application #:
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08884854
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Filing Dt:
|
06/30/1997
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Title:
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TECHNIQUES FOR REDUCING REDUNDANT ELEMENT FUSES IN A DYNAMIC RANDOM ACCESS MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08884855
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Filing Dt:
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06/30/1997
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Title:
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DYNAMIC ACCESS MEMORY EQUALIZER CIRCUITS AND METHODS THEREFOR
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08884860
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Filing Dt:
|
06/30/1997
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Title:
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CMOS INTEGRATED CIRCUITS WITH REDUCED SUBSTRATE DEFECTS
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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08884861
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Filing Dt:
|
06/30/1997
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Title:
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METHOD OF FORMING MULTI-LEVEL COPLANAR METAL/INSULATOR FILMS USING DUAL DAMASCENE WITH SACRIFICIAL FLOWABLE OXIDE
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Patent #:
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Issue Dt:
|
03/30/1999
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Application #:
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08885329
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Filing Dt:
|
06/30/1997
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Title:
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OCD WITH LOW OUTPUT CAPACITANCE
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08901986
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Filing Dt:
|
07/29/1997
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE HAVING A CRYSTALLINE LAYER
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Patent #:
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|
Issue Dt:
|
02/09/1999
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Application #:
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08923300
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Filing Dt:
|
09/04/1997
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Title:
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TEMPERATURE INDEPENDENT OSCILLATOR
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Patent #:
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Issue Dt:
|
11/10/1998
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Application #:
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08923459
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Filing Dt:
|
09/04/1997
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Title:
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DIMENSION PROGRAMMABLE FUSEBANKS AND METHODS FOR MAKING THE SAME
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Patent #:
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|
Issue Dt:
|
03/07/2000
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Application #:
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08932925
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Filing Dt:
|
09/19/1997
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Title:
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APPARATUS AND METHOD FOR HIGH-SPEED WORDLINE DRIVING WITH LOW AREA OVERHEAD
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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08937570
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Filing Dt:
|
09/25/1997
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Title:
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SEMICONDUCTOR MEMORY HAVING REDUNDANCY CIRCUIT
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Patent #:
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|
Issue Dt:
|
09/28/1999
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Application #:
|
08937571
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Filing Dt:
|
09/25/1997
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Title:
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A METHOD AND APPARATUS FOR REDUCING THE BIAS CURRENT IN A REFERENCE VOLTAGE CIRCUIT
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Patent #:
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|
Issue Dt:
|
05/30/2000
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Application #:
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08937764
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Filing Dt:
|
09/25/1997
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Title:
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METHOD OF MAXIMIZING CHIP YIELD FOR SEMICONDUCTOR WAFERS
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Patent #:
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|
Issue Dt:
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10/24/2000
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Application #:
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08937781
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Filing Dt:
|
09/25/1997
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Title:
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METHOD OF FABRICATING SEMICONDUCTOR CHIPS WITH SILICIDE AND IMPLANTED JUNCTIONS
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Patent #:
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|
Issue Dt:
|
04/04/2000
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Application #:
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08938072
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Filing Dt:
|
09/26/1997
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Title:
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METALIZATION SYSTEM HAVING AN ENHANCED THERMAL CONDUCTIVITY
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Patent #:
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|
Issue Dt:
|
08/10/1999
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Application #:
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08939148
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Filing Dt:
|
09/29/1997
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Title:
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DEPOSITION OF CARBON INTO NITRIDE LAYER FOR IMPROVED SELECTIVITY OF OXIDE TO NITRIDE ETCHRATE FOR SELF ALIGNED CONTACT ETCHING
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|
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Patent #:
|
|
Issue Dt:
|
11/02/1999
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Application #:
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08939208
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Filing Dt:
|
09/29/1997
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Title:
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MULTI-LEVEL CONDUCTIVE STRUCTURE INCLUDING LOW CAPACITANCE MATERIAL
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Patent #:
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|
Issue Dt:
|
09/28/1999
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Application #:
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08939546
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Filing Dt:
|
09/29/1997
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Title:
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APPARATUS AND METHOD FOR IMPLEMENTING A BANK INTERLOCK SCHEME AND RELATED TEST MODE FOR MULTIBANK MEMORY DEVICES
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|
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Patent #:
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|
Issue Dt:
|
05/15/2001
|
Application #:
|
08940806
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Filing Dt:
|
09/30/1997
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Title:
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METHODS FOR PERFORMING PLANARIZATION AND RECESS ETCHES AND APPARATUS THEREFOR
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|
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Patent #:
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|
Issue Dt:
|
07/13/1999
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Application #:
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08940861
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Filing Dt:
|
09/29/1997
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Title:
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SPACE-EFFICIENT SEMICONDUCTOR MEMORY HAVING HIERARCHICAL COLUMN SELECT LINE ARCHITECTURE
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08940862
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Filing Dt:
|
09/29/1997
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Title:
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CONSTANT CURRENT CMOS OUTPUT DRIVER CIRCUIT WITH DUAL GATE TRANSISTOR DEVICES
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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08941093
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Filing Dt:
|
09/30/1997
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Title:
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ENDPOINT DETECTION METHOD AND APPARATUS
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Patent #:
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Issue Dt:
|
02/02/1999
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Application #:
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08943910
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Filing Dt:
|
09/30/1997
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Title:
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REDUCING OXIDATION STRESS IN THE FABRICATION OF DEVICES
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Patent #:
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|
Issue Dt:
|
05/16/2000
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Application #:
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08999926
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Filing Dt:
|
06/23/1997
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Title:
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CONTROL OF CRITICAL DIMENSIONS THROUGH MEASUREMENT OF ABOSRBED RADIATION
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Patent #:
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|
Issue Dt:
|
06/15/1999
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Application #:
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09067766
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Filing Dt:
|
04/29/1998
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Title:
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METHOD FOR PRODUCING A CMOS CIRCUIT
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Patent #:
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|
Issue Dt:
|
07/03/2001
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Application #:
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09071798
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Filing Dt:
|
05/04/1998
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Title:
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DRAM CELL CONFIGURATION AND METHOD FOR ITS PRODUCTION
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Patent #:
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|
Issue Dt:
|
04/23/2002
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Application #:
|
09079020
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Filing Dt:
|
05/14/1998
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Title:
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INTEGRATED CIRCUIT HAVING AT LEAST TWO VERTICAL MOS TRANSISTORS AND METHOD FOR MANUFACTURING SAME
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Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
09089539
|
Filing Dt:
|
06/03/1998
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Title:
|
DRAM CELL ARRANGEMENT HAVING DYNAMIC SELF-AMPLIFYING MEMORY CELLS, AND METHOD FOR MANUFACTURING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
09093572
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Filing Dt:
|
06/08/1998
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Title:
|
DRAM CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
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|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09095261
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Filing Dt:
|
06/10/1998
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Title:
|
CIRCUIT CONFIGURATION FOR GENERATING DIGITAL SIGNALS
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|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09106237
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Filing Dt:
|
06/29/1998
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Title:
|
METHOD OF PRODUCING A BARRIER LAYER IN A SEMICONDUCTOR BODY
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|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09115618
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Filing Dt:
|
07/13/1998
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Title:
|
REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORIES
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|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09128387
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Filing Dt:
|
08/03/1998
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Title:
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CONFIGURATION FOR THE AUTOMATIC INSCRIPTION OR REINSCRIPTION OF WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09128388
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Filing Dt:
|
08/03/1998
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Title:
|
STRUCTURING PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09128389
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Filing Dt:
|
08/03/1998
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Title:
|
STRUCTURING METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
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Application #:
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09128806
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Filing Dt:
|
08/04/1998
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Title:
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DATABUS
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Patent #:
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|
Issue Dt:
|
09/03/2002
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Application #:
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09128807
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Filing Dt:
|
08/04/1998
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Title:
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METHOD AND CIRCUIT CONFIGURATION FOR PROCESSING DIGITAL SIGNALS
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Patent #:
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|
Issue Dt:
|
08/01/2000
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Application #:
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09133704
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Filing Dt:
|
08/13/1998
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Title:
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CIRCUIT APPARATUS FOR EVALUATING THE DATA CONTENT OF MEMORY CELLS
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Patent #:
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Issue Dt:
|
11/06/2001
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Application #:
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09133893
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Filing Dt:
|
08/14/1998
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Title:
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SEMICONDUCTOR COMPONENT AND METHOD FOR TESTING AND OPERATING A SEMICONDUCTOR COMPONENT
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|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
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Application #:
|
09138160
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Filing Dt:
|
08/21/1998
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Title:
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CIRCUIT ARRANGEMENT WITH AT LEAST FOUR TRANSISTORS, AND METHOD FOR THE MANUFACTURE THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
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09140972
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Filing Dt:
|
08/27/1998
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Title:
|
DRAM CELL ARRANGEMENT AND METHOD FOR THE MANUFACTURE THEREOF
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|
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Patent #:
|
|
Issue Dt:
|
01/30/2001
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Application #:
|
09143122
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Filing Dt:
|
08/28/1998
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Title:
|
FUSE CONFIGURATION FOR A SEMICONDUCTOR STORAGE DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
11/13/2001
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Application #:
|
09146636
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Filing Dt:
|
09/03/1998
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Title:
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STRUCTURING METHOD
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Patent #:
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|
Issue Dt:
|
04/03/2001
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Application #:
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09149829
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Filing Dt:
|
09/08/1998
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Title:
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METHOD FOR PRODUCING STRUCTURES HAVING A HIGH ASPECT RATIO AND STRUCTURE HAVING A HIGH ASPECT RATIO
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|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
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Application #:
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09150789
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Filing Dt:
|
09/10/1998
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Title:
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LEVEL CONVERTING CIRCUIT
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|
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Patent #:
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|
Issue Dt:
|
05/30/2000
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Application #:
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09160851
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Filing Dt:
|
09/25/1998
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Title:
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CIRCUIT CONFIGURATION FOR REDUCING DISTURBANCES DUE TO A SWITCHING OF AN OUTPUT DRIVER
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|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
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Application #:
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09160862
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Filing Dt:
|
09/25/1998
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Title:
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PULSE SHAPER CIRCUIT
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Patent #:
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|
Issue Dt:
|
12/07/1999
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Application #:
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09160875
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Filing Dt:
|
09/24/1998
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Title:
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O-AMINO (THIO) PHENOLCARBOXYLIC ACIDS AND THEIR PREPARATION
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|
Patent #:
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|
Issue Dt:
|
11/30/1999
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Application #:
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09160880
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Filing Dt:
|
09/25/1998
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Title:
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RS FLIP-FLOP WITH ENABLE INPUTS
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|
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Patent #:
|
|
Issue Dt:
|
11/21/2000
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Application #:
|
09161144
|
Filing Dt:
|
09/24/1998
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Title:
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BIS-O-AMINO(THIO)PHENOLS, AND THEIR PREPARATION
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|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09161147
|
Filing Dt:
|
09/24/1998
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Title:
|
O-AMINO (THIO) PHENOLCARBOXYLIC ACIDS, AND THEIR PREPARATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09161148
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Filing Dt:
|
09/24/1998
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Title:
|
POLYBENZOXAZOLE AND POLYBENZOTHIAZOLE PRECURSORS
|
|
|
Patent #:
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|
Issue Dt:
|
11/20/2001
|
Application #:
|
09161149
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Filing Dt:
|
09/24/1998
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Title:
|
O-NITRO(THIO)PHENOL DERIVATIVES, AND THEIR PREPARATION
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|
Patent #:
|
|
Issue Dt:
|
09/19/2000
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Application #:
|
09161202
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Filing Dt:
|
09/24/1998
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Title:
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POLYBENZOXAZOLE AND POLYBENZOTHIAZOLE PRECURSORS
|
|
|
Patent #:
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|
Issue Dt:
|
12/05/2000
|
Application #:
|
09161549
|
Filing Dt:
|
09/24/1998
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Title:
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BIS-O-AMINO (THIO) PHENOLS, AND THEIR PREPARATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
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Application #:
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09162608
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Filing Dt:
|
09/29/1998
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Title:
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ASSOCIATIVE MEMORY AND METHOD FOR THE OPERATION THEREOF
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|
|
Patent #:
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|
Issue Dt:
|
03/02/2004
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Application #:
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09163874
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Filing Dt:
|
09/30/1998
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Title:
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METHOD FOR THE LINEAR CONFIGURATION OF METALLIC FUSE SECTIONS ON WAFERS
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Patent #:
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|
Issue Dt:
|
12/05/2000
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Application #:
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09164115
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Filing Dt:
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09/30/1998
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Title:
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PROCESS FOR PRODUCING A CERAMIC LAYER
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09164119
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Filing Dt:
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09/30/1998
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Title:
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PROCESS FOR PRODUCING A CERAMIC LAYER CONTAINING BI
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09176558
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Filing Dt:
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10/21/1998
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Title:
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INTEGRATED CIRCUIT CONFIGURATION HAVING AT LEAST ONE CAPACITOR AND METHOD FOR PRODUCING THE SAME
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|
Patent #:
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|
Issue Dt:
|
11/02/1999
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Application #:
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09191482
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Filing Dt:
|
11/13/1998
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Title:
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DRAM CELL ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
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Patent #:
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|
Issue Dt:
|
01/18/2000
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Application #:
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09197391
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Filing Dt:
|
11/20/1998
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Title:
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MICROSTRUCTURE AND METHODS FOR FABRICATING SUCH STRUCTURE
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Patent #:
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|
Issue Dt:
|
03/14/2000
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Application #:
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09200071
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Filing Dt:
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11/25/1998
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Title:
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SRAM CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
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|
|
Patent #:
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|
Issue Dt:
|
01/09/2001
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Application #:
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09201728
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Filing Dt:
|
11/30/1998
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Title:
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CHEMICALLY AMPLIFIED RESIST
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09201733
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Filing Dt:
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11/30/1998
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Title:
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MEMORY CELL USING AMORPHOUS MATERIAL TO STABILIZE THE BOUNDARY FACE BETWEEN POLYCHRYSTALLINE SEMICONDUCTOR MATERIAL OF A CAPACITOR AND MONCRYSTALLINE SEMICONDUCTOR MATERIAL OF A TRANSISTOR
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09251616
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Filing Dt:
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02/17/1999
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Title:
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DEVICE WITH ASYMMETRICAL CHANNEL DOPANT PROFILE
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09281021
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Filing Dt:
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03/30/1999
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Title:
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REDUCED SIGNAL TEST FOR DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09388274
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Filing Dt:
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09/01/1999
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Title:
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O-AMINO(THIO) PHENOLCARBOXYLIC ACIDS, AND THEIR PREPARATION
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09423864
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Filing Dt:
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11/15/1999
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Title:
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INTEGRATED CMOS CIRCUIT CONFIGURATION, AND PRODUCTION OF SAME
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09438305
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Filing Dt:
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09/13/1999
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Title:
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BACKING FILM FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09450403
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Filing Dt:
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11/29/1999
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Title:
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INPUT CIRCUIT FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/05/2005
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Application #:
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09462994
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Filing Dt:
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01/14/2000
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Title:
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INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR THE MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09465726
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Filing Dt:
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12/17/1999
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Title:
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CONFIGURATION OF MEMORY CELLS AND METHOD OF CHECKING THE OPERATION OF MEMORY CELLS
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09472221
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Filing Dt:
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12/27/1999
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Title:
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SEMICONDUCTOR CIRCUIT APPARATUS AND METHOD FOR FABRICATING THE SEMICONDUCTOR CIRCUIT APPARATUS
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09487411
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Filing Dt:
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01/18/2000
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Title:
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Method of producing a vertical mos transistor
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09491296
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Filing Dt:
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01/25/2000
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Title:
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POLISHING AGENT FOR SEMICONDUCTOR SUBSTRATES
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09494775
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Filing Dt:
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01/31/2000
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Title:
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READ-ONLY MEMORY AND FABRICATION METHOD
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09495795
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Filing Dt:
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02/01/2000
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Title:
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Wafer marking
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09498532
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Filing Dt:
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02/04/2000
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Title:
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Integrated electrical circuit with passivation layer
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09521396
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Filing Dt:
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03/08/2000
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Title:
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Digital circuit having a filter unit for suppressing glitches
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09528159
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Filing Dt:
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03/17/2000
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Title:
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MEMORY CELL CONFIGURATION, MAGNETIC RAM, AND ASSOCIATIVE MEMORY
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09528268
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Filing Dt:
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03/17/2000
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Title:
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MEMORY CELL CONFIGURATION AND FABRICATION METHOD
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09528424
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Filing Dt:
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03/17/2000
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Title:
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Dynamic memory having two modes of operation
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09536029
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Filing Dt:
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03/27/2000
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Title:
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Digital memory and method of operation for a digital memory
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09539235
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Filing Dt:
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03/30/2000
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Title:
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PRODUCT INCLUDING A SILICON-CONTAINING FUNCTIONAL LAYER AND AN INSULATING LAYER MADE OF SILICON DIOXIDE, AND METHOD FABRICATING THE PRODUCT
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09539237
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Filing Dt:
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03/30/2000
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Title:
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METHOD OF PRODUCING AN OPEN FORM
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