Patent Assignment Details
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Reel/Frame: | 036293/0932 | |
| Pages: | 10 |
| | Recorded: | 08/06/2015 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
107
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2
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2
Pages:
1 2
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09547683
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Filing Dt:
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04/12/2000
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Title:
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Method for testing bus connections of writable and readable integrated electronic circuits, in particular memory components
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09592225
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Filing Dt:
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06/12/2000
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Title:
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Buffer circuit
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09594911
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Filing Dt:
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06/15/2000
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Title:
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INTEGRATED MEMORY WITH A BUFFER CIRCUIT
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09729068
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Filing Dt:
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12/04/2000
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Publication #:
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Pub Dt:
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05/03/2001
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Title:
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Method of programming a semiconductor memory
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09851051
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Filing Dt:
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05/08/2001
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Title:
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METHOD FOR THE PRODUCTION OF A DRAM CELL CONFIGURATION
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09901218
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Filing Dt:
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07/09/2001
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Publication #:
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Pub Dt:
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12/27/2001
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Title:
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O-AMINOPHENOLCARBOXYLIC ACID AND O-AMINOTHIOPHENOLCARBOXYLIC ACID
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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10081902
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Filing Dt:
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02/22/2002
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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INTEGRATED CIRCUIT HAVING AT LEAST TWO VERTICAL MOS TRANSISTORS AND METHOD FOR MANUFACTURING SAME
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Assignee
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29 EARLSFORT TERRACE, DUBLIN 2 |
DUBLIN, IRELAND |
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Correspondence name and address
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POLARIS INNOVATIONS LIMITED
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303 TERRY FOX DRIVE, SUITE 300
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OTTAWA, K2K 3J1 CANADA
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