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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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08940233
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Filing Dt:
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09/30/1997
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Title:
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REDUCTION OF PAD EROSION
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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08940235
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Filing Dt:
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09/30/1997
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Title:
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RELIABLE POLICIDE GATE STACK WITH REDUCED SHEET RESISTANCE AND THICKNESS
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08940808
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Filing Dt:
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09/30/1997
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Title:
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DISHING RESISTANCE
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08940891
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Filing Dt:
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09/30/1997
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Title:
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HARD ETCH MASK
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Patent #:
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Issue Dt:
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06/06/2000
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Application #:
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08940892
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Filing Dt:
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09/30/1997
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Title:
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METHOD FOR PATTERNING INTEGRATED CIRCUIT CONDUCTORS
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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08940895
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Filing Dt:
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09/30/1997
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Title:
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DUAL DAMASCENE PROCESS FOR METAL LAYERS AND ORGANIC INTERMETAL LAYERS
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Patent #:
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Issue Dt:
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08/24/1999
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Application #:
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08940899
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Filing Dt:
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09/30/1997
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Title:
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POWER-ON DETECTION AND ENABLING CIRCUIT WITH VERY FAST DETECTION OF POWER-OFF
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08941606
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Filing Dt:
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09/30/1997
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Title:
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SECONDARY SENSE AMPLIFIER WITH WINDOW DISCRIMINATOR FOR SELF-TIMED OPERATION
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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08942273
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Filing Dt:
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09/30/1997
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Title:
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GAPFILL OF SEMICONDUCTOR STRUCTURE USING DOPED SILICATE GLASSES
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08942275
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Filing Dt:
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09/30/1997
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Title:
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SEMICONDUCTOR MEMORY HAVING HIERARCHICAL BIT LINE ARCHITECTURE WITH NON-UNIFORM LOCAL BIT LINES
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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08992378
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Filing Dt:
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12/17/1997
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Title:
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MEMORY WITH WORD LINE VOLTAGE CONTROL
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Patent #:
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Issue Dt:
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12/08/1998
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Application #:
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08992379
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Filing Dt:
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12/17/1997
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Title:
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MEMORY ARRAY WITH REDUCED CHARGING CURRENT
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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08994273
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Filing Dt:
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12/19/1997
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Title:
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METHOD FOR QUANTIFYING PROXIMITY EFFECTS BY MEASURING DEVICE PERFORMANCE
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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08994829
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Filing Dt:
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12/19/1997
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Title:
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SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY ARCHITECTURE FOR SEQUENTIAL BURST MODE
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08997682
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Filing Dt:
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12/23/1997
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Title:
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DUAL DAMASCENE WITH BOND PADS
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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08998856
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Filing Dt:
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12/29/1997
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Title:
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REDUCED PAD EROSION
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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09000626
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Filing Dt:
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12/30/1997
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Title:
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RECESSED SHALLOW TRENCH ISOLATION STRUCTURE NITRIDE LINER AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09030227
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Filing Dt:
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02/25/1998
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Title:
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CONTACT BETWEEN A MONOCRYSTALLINE SILICON REGION AND A POLYCRYSTALLINE SILICON STRUCTURE AND METHOD FOR PRODUCING SUCH A CONTACT
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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09030406
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Filing Dt:
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02/25/1998
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Title:
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METHOD FOR PRODUCING A POLYCRYSTALLINE SILICON STRUCTURE AND POLYCRYSTALLINE SILICON LAYER TO BE PRODUCED BY THE METHOD
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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09183246
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Filing Dt:
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10/30/1998
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Title:
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RECESSED SHALLOW TRENCH ISOLATION STRUCTURE NITRIDE LINER AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09197371
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Filing Dt:
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11/20/1998
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Title:
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PLASTIC COMPOSITIONS FOR SHEATHING A METAL OR SEMICONDUCTOR BODY
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09228610
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Filing Dt:
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01/12/1999
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Title:
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AN ADJUSTABLE DELAY CIRCUIT
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09228611
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Filing Dt:
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01/12/1999
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Title:
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DRAM CELL ARRANGEMENT AND METHOD FOR ITS PRODUCTION
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09232081
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Filing Dt:
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01/15/1999
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Title:
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TRENCH CAPACITOR WITH INSULATION COLLAR AND METHOD FOR PRODUCING THE TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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09232083
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Filing Dt:
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01/15/1999
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Title:
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MEMORY CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09243296
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Filing Dt:
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02/02/1999
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Title:
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INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09250362
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Filing Dt:
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02/12/1999
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Title:
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MEMORY CELL CONFIGURATION AND CORRESPONDING FABRICATION METHOD
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09250516
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Filing Dt:
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02/16/1999
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Title:
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CIRCUIT ARRANGEMENT WITH AT LEAST ONE CAPACITOR
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09258940
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Filing Dt:
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03/01/1999
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Title:
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INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09261100
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Filing Dt:
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03/02/1999
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Title:
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INTEGRATED CIRCUIT AND METHOD FOR TESTING IT
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09272077
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Filing Dt:
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03/18/1999
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Title:
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DRAM CELL ARRANGEMENT
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09272968
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Filing Dt:
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03/19/1999
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Title:
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MOS TRANSISTOR IN A SINGLE-TRANSISTOR MEMORY CELL HAVING A LOCALLY THICKENED GATE OXIDE, AND PRODUCTION PROCESS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09273648
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Filing Dt:
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03/23/1999
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Title:
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METHOD FOR PROGRAMMING A ROM CELL ARRANGEMENT
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09274733
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Filing Dt:
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03/23/1999
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Title:
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DRAM CELL ARRANGEMENT AND METHOD FOR ITS PRODUCTION
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09277281
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Filing Dt:
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03/26/1999
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Title:
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CONFIGURATION FOR INDENTIFYING CONTACT FAULTS DURING THE TESTING OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09285897
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Filing Dt:
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04/08/1999
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Title:
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METHOD FOR FABRICATING A STACKED CAPACITOR IN A SEMICONDUCTOR CONFIGURATION, AND STACKED CAPACITOR FABRICATED BY THIS METHOD
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09289491
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Filing Dt:
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04/09/1999
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Title:
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METHOD AND APPARATUS FOR THE TREATMENT OF OBJECTS, PREFERABLY WAFERS
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09302649
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Filing Dt:
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04/30/1999
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Title:
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CONFIGURATION FOR TESTING A PLURALITY OF MEMORY CHIPS ON A WAFER
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09302655
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Filing Dt:
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04/30/1999
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Title:
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METHOD FOR FABRICATING A CAPACITOR FOR A SEMICONDUCTOR MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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09311118
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Filing Dt:
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05/13/1999
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Title:
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OPTIMIZED-DELAY MULTIPLEXER
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09311120
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Filing Dt:
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05/13/1999
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Title:
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CIRCUIT CONFIGURATION FOR PRODUCING COMPLEMENTARY SIGNALS
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09312571
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Filing Dt:
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05/14/1999
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Title:
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MANUFACTURING METHOD FOR A CAPACITOR IN AN INTEGRATED STORAGE CIRCUIT
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09312572
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Filing Dt:
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05/14/1999
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Title:
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MANUFACTURING METHOD FOR A CAPACITOR IN AN INTEGRATED MEMORY CIRCUIT
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09313422
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Filing Dt:
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05/17/1999
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Title:
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METHOD OF HOLDING A WAFER AND TESTING THE INTEGRATED CIRCUITS ON THE WAFER
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09315328
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Filing Dt:
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05/20/1999
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Title:
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SEMICONDUCTOR MEMORY HAVING DIFFERENTIAL BIT LINES
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09315329
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Filing Dt:
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05/20/1999
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Title:
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PROCESS FOR PRODUCING METAL-CONTAINING LAYERS
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09321174
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Filing Dt:
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05/27/1999
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Title:
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FUSE-LATCH CIRCUIT
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09322717
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Filing Dt:
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05/28/1999
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Title:
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CIRCUIT CONFIGURATION FOR BURN-IN SYSTEMS FOR TESTING MODULES BY USING A BOARD
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09322718
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Filing Dt:
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05/28/1999
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Title:
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CONFIGURATION FOR CROSSTALK ATTENUATION IN WORD LINES OF DRAM CIRCUITS
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09326366
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Filing Dt:
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06/04/1999
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Title:
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BONDING PAD TEST CONFIGURATION
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09327699
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Filing Dt:
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06/08/1999
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT HAVING DUMMY STRUCTURES
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09335561
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Filing Dt:
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06/18/1999
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Title:
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DEVICE FOR THE DEPOSITION OF SUBSTANCES
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09343429
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Filing Dt:
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06/30/1999
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Title:
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DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INITIALIZING A DYNAMIC SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09343431
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Filing Dt:
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06/30/1999
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Title:
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DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INTIALIZING A DYNAMIC SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09344922
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Filing Dt:
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06/28/1999
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Title:
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INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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09346379
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Filing Dt:
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07/01/1999
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Title:
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OUTPUT DRIVER OF AN INTEGRATED SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09352992
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Filing Dt:
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07/14/1999
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Title:
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CONFIGURATION AND METHOD FOR STORING THE TEST RESULTS OBTAINED BY A BIST CIRCUIT
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09353612
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Filing Dt:
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07/14/1999
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Title:
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CONFIGURATION FOR TESTING CHIPS
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09356402
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Filing Dt:
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07/16/1999
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Title:
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METHOD OF PRODUCING A STACKED CAPACITOR
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09356811
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Filing Dt:
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07/19/1999
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Title:
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INTEGRATED CIRCUIT WITH A VOLTAGE REGULATOR
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09356813
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Filing Dt:
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07/19/1999
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Title:
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INTEGRATED CIRCUIT HAVING A SELF-TEST DEVICE
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09356955
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Filing Dt:
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07/19/1999
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Title:
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CONFIGURATION FOR TESTING INTEGRATED COMPONENTS
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09360944
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Filing Dt:
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07/26/1999
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Title:
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PROCESS FOR CLEANING CVD UNITS
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09360973
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Filing Dt:
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07/27/1999
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Title:
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COMPOSITE MEMBER COMPOSED OF AT LEAST TWO INTEGRATED CIRCUITS AND METHOD FOR THE MANUFACTURE OF A COMPOSITE MEMBER COMPOSED OF AT LEAST TWO INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09363263
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Filing Dt:
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07/29/1999
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Title:
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INTEGRATED SEMICONDUCTOR CHIP WITH MODULAR DUMMY STRUCTURES
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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09363277
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Filing Dt:
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07/28/1999
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Title:
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TRENCH CAPACITOR WITH AN INSULATION COLLAR AND METHOD FOR PRODUCING A TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09368134
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Filing Dt:
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08/04/1999
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Title:
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INTEGRATED CIRCUIT HAVING A SELF-TEST DEVICE AND METHOD FOR PRODUCING THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09372307
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Filing Dt:
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08/11/1999
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Title:
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METHOD OF TESTING LEAKAGE CURRENT AT A CONTACT-MAKING POINT IN AN INTEGRATED CIRCUIT BY DETERMINING A POTENTIAL AT THE CONTACT-MAKING POINT
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09374893
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Filing Dt:
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08/13/1999
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Title:
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PROCESS FOR PRODUCING STRUCTURED LAYERS, PROCESS FOR PRODUCING COMPONENTS OF AN INTEGRATED CIRCUIT, AND PROCESS FOR PRODUCING A MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09374894
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Filing Dt:
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08/13/1999
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Title:
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COMBINED PRECHARGING AND HOMOGENIZING CIRCUIT
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09374895
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Filing Dt:
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08/13/1999
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Title:
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INTEGRATED SEMICONDUCTOR CHIP HAVING LEADS TO ONE OR MORE EXTERNAL TERMINALS
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09384701
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Filing Dt:
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08/27/1999
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Title:
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INTEGRATED SEMICONDUCTOR MEMORY WITH CONTROL DEVICE FOR CLOCK-SYNCHRONOUS WRITING AND READING
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09390496
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Filing Dt:
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09/03/1999
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Title:
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METHOD FOR THE FABRICATION OF A DOPED SILICON LAYER
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09391717
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Filing Dt:
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09/08/1999
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Title:
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INTEGRATED SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
|
01/08/2002
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Application #:
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09391720
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Filing Dt:
|
09/08/1999
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Title:
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LAYER CONFIGURATION WITH A MATERIAL LAYER AND A DIFFUSION BARRIER WHICH BLOCKS DIFFUSING MATERIAL COMPONENTS AND PROCESS FOR PRODUCING A DIFFUSION BARRIER
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Patent #:
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Issue Dt:
|
03/12/2002
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Application #:
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09394196
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Filing Dt:
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09/10/1999
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Title:
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ELECTRONIC CIRCUIT CONFIGURATION
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Patent #:
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Issue Dt:
|
05/08/2001
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Application #:
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09395005
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Filing Dt:
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09/13/1999
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Title:
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INTEGRATED CIRCUIT WITH TWO OPERATING STATES
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09395316
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Filing Dt:
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09/13/1999
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Title:
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CAPACITOR WITH HIGH-E DIELECTRIC OR FERROELECTRIC MATERIAL BASED ON THE FIN STACK PRINCIPLE AND PRODUCTION PROCESS USING A NEGATIVE MOLD
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Patent #:
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Issue Dt:
|
01/30/2001
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Application #:
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09398695
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Filing Dt:
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09/20/1999
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Title:
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INTEGRATED CIRCUIT MEMORY HAVING A SENSE AMPLIFIER ACTIVATED BASED ON WORD LINE POTENTIALS
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Patent #:
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Issue Dt:
|
08/21/2001
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Application #:
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09401022
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Filing Dt:
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09/21/1999
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Title:
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INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
11/20/2001
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Application #:
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09401387
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Filing Dt:
|
09/22/1999
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Title:
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METHOD FOR DETERMINING THE DRIVE CAPABILITY OF A DRIVER CIRCUIT OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
01/23/2001
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Application #:
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09401388
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Filing Dt:
|
09/22/1999
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Title:
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INTEGRATED MEMORY HAVING A SELF-REPAIR FUNCTION
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Patent #:
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Issue Dt:
|
07/31/2001
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Application #:
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09401390
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Filing Dt:
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09/22/1999
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Title:
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BURN-IN TEST DEVICE
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Patent #:
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Issue Dt:
|
08/14/2001
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Application #:
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09405916
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Filing Dt:
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09/24/1999
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Title:
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MEMORY CELL CONFIGURATION AND PRODUCTION PROCESS THEREFOR
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|
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Patent #:
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Issue Dt:
|
06/12/2001
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Application #:
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09407263
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Filing Dt:
|
09/27/1999
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Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
|
04/11/2000
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Application #:
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09407384
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Filing Dt:
|
09/28/1999
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Title:
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GAPFILL OF SEMICONDUCTOR STRUCTURE USING DOPED SILICATE GLASSES
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Patent #:
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Issue Dt:
|
02/13/2001
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Application #:
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09408476
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Filing Dt:
|
09/28/1999
|
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Title:
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INTEGRATED CIRCUIT HAVING A CONTACT-MAKING POINT FOR SELECTING AN OPERATING MODE OF THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
05/13/2003
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Application #:
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09408477
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Filing Dt:
|
09/28/1999
|
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Title:
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METHOD FOR INSTALLING PROTECTIVE COMPONENTS IN INTEGRATED CIRCUITS THAT ARE CONSTRUCTED FROM STANDARD CELLS
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Patent #:
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Issue Dt:
|
07/18/2000
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Application #:
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09408479
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Filing Dt:
|
09/28/1999
|
|
Title:
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FERROELECTRIC MEMORY AND METHOD FOR PREVENTING AGING IN A MEMORY CELL
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|
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Patent #:
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Issue Dt:
|
12/12/2000
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Application #:
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09408677
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Filing Dt:
|
09/30/1999
|
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Title:
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INTEGRATED CIRCUIT WITH A CONFIGURATION ASSEMBLY
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Patent #:
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Issue Dt:
|
04/06/2004
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Application #:
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09408688
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Filing Dt:
|
09/30/1999
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Title:
|
VERTICAL FIELD EFFECT TRANSISTOR WITH INTERNAL ANNULAR GATE AND METHOD OF PRODUCTION
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Patent #:
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Issue Dt:
|
01/14/2003
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Application #:
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09428582
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Filing Dt:
|
10/28/1999
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Title:
|
METHOD AND AN APPARATUS FOR TREATING WASTEWATER FROM A CHEMICAL-MECHANICAL POLISHING PROCESS USED IN CHIP FABRICATION
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Patent #:
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Issue Dt:
|
02/06/2001
|
Application #:
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09541952
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Filing Dt:
|
04/03/2000
|
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Title:
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METHOD FOR DRAM CELL ARRANGEMENT AND METHOD FOR ITS PRODUCTION
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Patent #:
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Issue Dt:
|
04/30/2002
|
Application #:
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09617652
|
Filing Dt:
|
07/17/2000
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|
Title:
|
Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component
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Patent #:
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Issue Dt:
|
08/21/2001
|
Application #:
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09621433
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Filing Dt:
|
07/21/2000
|
|
Title:
|
Method for fabricating stacked vias
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|
Patent #:
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|
Issue Dt:
|
03/05/2002
|
Application #:
|
09632584
|
Filing Dt:
|
08/07/2000
|
|
Title:
|
Olanzapine-N-oxide compositions and methods
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|
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|
Patent #:
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Issue Dt:
|
09/02/2003
|
Application #:
|
09636521
|
Filing Dt:
|
08/10/2000
|
|
Title:
|
OPTICAL STRUCTURE AND METHOD FOR PRODUCING THE SAME
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|
|
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|
Patent #:
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|
Issue Dt:
|
11/13/2001
|
Application #:
|
09642328
|
Filing Dt:
|
08/21/2000
|
|
Title:
|
METHOD FOR FABRICATING A MEMORY CELL HAVING A MOS TRANSISTOR
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|
|
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|
Patent #:
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|
Issue Dt:
|
10/07/2003
|
Application #:
|
09655603
|
Filing Dt:
|
09/05/2000
|
|
Title:
|
MODULARLY EXPANDABLE MULT-LAYERED SEMICONDUCTOR COMPONENT
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|
|
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Patent #:
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Issue Dt:
|
04/02/2002
|
Application #:
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09668485
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Filing Dt:
|
09/25/2000
|
|
Title:
|
Memory cell configuration and method for fabricating it
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|
