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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09680736
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Filing Dt:
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10/06/2000
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Title:
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METHOD OF POSITIONING A COMPONENT MOUNTED ON A LEAD FRAME IN A TEST SOCKET
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09690298
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Filing Dt:
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10/17/2000
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Title:
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MEMORY CONFIGURATION HAVING REDUNDANT MEMORY LOCATIONS AND METHOD FOR ACCESSING REDUNDANT MEMORY LOCATIONS
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09708279
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Filing Dt:
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11/08/2000
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Title:
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SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09716336
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Filing Dt:
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11/20/2000
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Title:
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INTEGRATED CIRCUIT CONFIGURATION HAVING AT LEAST ONE TRANSISTOR AND ONE CAPACITOR, AND METHOD FOR FABRICATING IT
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09734466
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Filing Dt:
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12/11/2000
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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STORAGE CAPACITOR FOR A DRAM
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09740637
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Filing Dt:
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12/18/2000
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Publication #:
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Pub Dt:
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06/28/2001
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Title:
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Method for writing and reading a ferroelectric memory
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09751961
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Filing Dt:
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12/29/2000
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09756082
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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10/18/2001
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Title:
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DRAM MEMORY CAPACITOR HAVING THREE-LAYER DIELECTRIC, AND METHOD FOR ITS PRODUCTION
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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09756084
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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09/13/2001
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Title:
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CIRCUIT FOR DETERMINING THE TIME DIFFERENCE BETWEEN EDGES OF A FIRST DIGITAL SIGNAL AND OF A SECOND DIGITAL SIGNAL
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09756525
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09761801
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Filing Dt:
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01/16/2001
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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MEMORY CELL CONFIGURATION IN WHICH AN ELECTRICAL RESISTANCE OF A MEMORY ELEMENT REPRESENTS AN INFORMATION ITEM AND CAN BE INFLUENCED BY A MAGNETIC FIELD, AND METHOD FOR FABRICATING IT
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09767393
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Filing Dt:
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01/23/2001
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Publication #:
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Pub Dt:
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08/09/2001
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Title:
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INTEGRATED CIRCUIT HAVING A SELF-TEST DEVICE FOR CARRYING OUT A SELF-TEST OF THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09771675
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Filing Dt:
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01/29/2001
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Publication #:
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Pub Dt:
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09/13/2001
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Title:
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INTEGRATED COMPONENT, COMPOSITE ELEMENT COMPRISING AN INTEGRATED COMPONENT AND A CONDUCTOR STRUCTURE, CHIP CARD, AND METHOD OF PRODUCING THE INTEGRATED COMPONENT
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09773218
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
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10/18/2001
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Title:
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METHOD FOR FABRICATING A MEMORY CELL
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09776954
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Filing Dt:
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02/05/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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Integrated circuit with electrical connection points that can be severed by the action of enegry
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09781175
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
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08/23/2001
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Title:
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INTEGRATED MEMORY WITH INTERBLOCK REDUNDANCY
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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09787966
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Filing Dt:
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05/29/2001
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Title:
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INTEGRATED CIRCUIT COMPRISING VERTICAL TRANSISTORS, AND A METHOD FOR THE PRODUCTION THEREOF
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09793789
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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METHOD OF REPAIRING DEFECTIVE MEMORY CELLS OF AN INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09796208
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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MICROELECTRONIC MEMORY CELL STRUCTURE WITH A LAYER OF TIN HAVING N:TI
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09801210
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Filing Dt:
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03/07/2001
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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MAGNETORESISTIVE ELEMENT AND USE THEREOF AS A MEMORY ELEMENT IN A MEMORY CELL CONFIGURATION
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09803430
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Filing Dt:
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03/09/2001
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Publication #:
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Pub Dt:
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12/06/2001
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Title:
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Digital circuit
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09806617
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Filing Dt:
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03/30/2001
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Title:
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MAGNETORESISTIVE ELEMENT AND THE USE THEREOF AS STORAGE ELEMENT IN A STORAGE CELL ARRAY
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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09811881
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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SELECTIVELY DEACTIVATING A FIRST CONTROL LOOP IN A DUAL CONTROL LOOP CIRCUIT DURING DATA TRANSMISSION
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09820235
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Filing Dt:
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03/28/2001
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Publication #:
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Pub Dt:
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11/08/2001
| | | | |
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Title:
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Integrated memory having a differential sense amplifier
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09821964
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Filing Dt:
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03/30/2001
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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Magnetoresistive memory having elevated interference immunity
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09822019
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Filing Dt:
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03/30/2001
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Publication #:
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Pub Dt:
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10/18/2001
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Title:
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MAGNETORESISTIVE MEMORY WITH A LOW CURRENT DENSITY
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09822028
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Filing Dt:
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03/29/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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DECODER ELEMENT FOR GENERATING AN OUTPUT SIGNAL HAVING THREE DIFFERENT POTENTIALS AND AN OPERATING METHOD FOR THE DECODER ELEMENT
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09829871
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Filing Dt:
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04/10/2001
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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APPARATUS FOR TREATING WASTEWATER FROM A CHEMICAL-MECHANICAL POLISHING PROCESS USED IN CHIP FABRICATION
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09863925
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Filing Dt:
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05/23/2001
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Title:
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CAPACITOR WITH HIGH-EPSILON DIELECTRIC OR FERROELECTRIC MATERIAL BASED ON THE FIN STACK PRINCIPLE
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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09885553
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Filing Dt:
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06/20/2001
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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MOS TRANSISTOR IN A SINGLE-TRANSISTOR MEMORY CELL HAVING A LOCALLY THICKENED GATE OXIDE
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09976233
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Filing Dt:
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10/12/2001
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Publication #:
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Pub Dt:
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07/04/2002
| | | | |
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Title:
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METHOD OF PRODUCING AN INTEGRATED CIRCUIT CONFIGURATION
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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10005978
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Filing Dt:
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12/03/2001
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Publication #:
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Pub Dt:
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05/09/2002
| | | | |
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Title:
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METHOD FOR FABRICATING A MEMORY CELL CONFIGURATION
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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10431849
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Filing Dt:
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05/08/2003
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Title:
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MEMORY CELL ARRAY AND METHOD FOR MANFACTURING IT
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10454522
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Filing Dt:
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06/04/2003
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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METHODS OF USING ADHESION ENHANCING LAYERS AND MICROELECTRONIC INTEGRATED MODULES INCLUDING ADHESION ENHANCING LAYERS
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