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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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09036486
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Filing Dt:
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03/06/1998
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Title:
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FEEDBACK PULSE GENERATORS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09037287
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Filing Dt:
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03/09/1998
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Title:
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SELF ALIGNED BURIED PLATE
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09047581
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Filing Dt:
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03/25/1998
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Title:
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SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND BURIED WORD LINE
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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09052799
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Filing Dt:
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03/31/1998
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Title:
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DYNAMIC RANDOM ACCESS MEMORY CIRCUIT AND METHODS THEREFOR
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09056119
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Filing Dt:
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04/06/1998
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Title:
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TRENCH CAPACITOR WITH EPI BURIED LAYER
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Patent #:
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Issue Dt:
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04/04/2000
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Application #:
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09074882
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Filing Dt:
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05/08/1998
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Title:
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METHOD OF FORMING STACK CAPACITOR WITH IMPROVED PLUG CONDUCTIVITY
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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09093796
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Filing Dt:
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06/09/1998
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Title:
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SEMICONDUCTORS HAVING DEFECT DENUDED ZONES
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09093797
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Filing Dt:
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06/09/1998
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Title:
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INTEGRATED CIRCUIT WITH IMPROVED OFF CHIP DRIVERS
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09093801
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Filing Dt:
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06/09/1998
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Title:
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METHOD OF FORMING DEEP TRENCH CAPACITORS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09095793
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Filing Dt:
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06/11/1998
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Title:
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VERTICAL DEVICE FORMED ADJACENT TO A WORLDLINE SIDEWALL AND METHOD FOR SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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09097545
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Filing Dt:
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06/15/1998
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Title:
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MEMORY WITH REDUCED WIRE CONNECTIONS
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09097783
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Filing Dt:
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06/15/1998
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Title:
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TRENCH CAPACITOR WITH ISOLATION COLLAR AND CORRESPONDING MANUFACTURING METHOD
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09097872
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Filing Dt:
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06/15/1998
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Title:
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HIGH DENSITY PLASMA CVD PROCESS FOR MAKING DIELECTRIC ANTI-REFLECTIVE COATINGS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09098785
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Filing Dt:
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06/17/1998
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Title:
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PHASE SHIFT MASK HAVING MULTIPLE ALIGNMENT INDICATIONS AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09099093
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Filing Dt:
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06/17/1998
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Title:
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SEMICONDUCTOR METALIZATION SYSTEM AND METHOD BACKGROUND OF THE INVENTION
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09103871
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Filing Dt:
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06/24/1998
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Title:
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LOCK ARRANGEMENT FOR A CALABRATED DDL IN DDR SDRAM APPLICATIONS
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09105107
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Filing Dt:
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06/24/1998
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Title:
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METHOD FOR FORMING A SEMINCONDUCTOR FUSE
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09105632
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Filing Dt:
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06/26/1998
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Title:
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SYSTEM AND METHOD FOR OPTICALLY MEASURING DIELECTRIC THICKNESS IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09105633
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Filing Dt:
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06/26/1998
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Title:
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LOW LEAKAGE, LOW CAPACITANCE ISOLATION MATERIAL
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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09107191
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Filing Dt:
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06/29/1998
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Title:
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INTERLEAVED SENSE AMPLIFIER WITH A SINGLE-SIDED PRECHARGE DEVICE
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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09107672
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Filing Dt:
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06/30/1998
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Title:
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SEMICONDUCTOR MANUFACTURING METHOD
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09107861
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Filing Dt:
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06/30/1998
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Title:
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AMORPHOUSLY DEPOSITED METAL OXIDE CERAMIC FILMS
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09120629
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Filing Dt:
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07/22/1998
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Title:
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PREVENTION OF PHOTORESIST POISONING FROM DIELECTRIC ANTIREFLECTIVE COATING IN SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09120630
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Filing Dt:
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07/22/1998
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Title:
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SILICON OXYNITRIDE CAP FOR FLUORINATED SILICATE GLASS FILM IN INTERMETAL DIELECTRIC SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09127262
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Filing Dt:
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07/31/1998
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Title:
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APPARATUS AND METHOD FOR FORMING CONTROLLED DEEP TRENCH TOP ISOLATION LAYERS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09145623
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Filing Dt:
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09/02/1998
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Title:
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VERTICAL DEVICE FORMED ADJACENT TO A WORDLINE SIDEWALL AND METHOD FOR SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09146870
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Filing Dt:
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09/03/1998
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Title:
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COMBINED PREANNEAL/OXIDATION STEP USING RAPID THERMAL PROCESSING
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09153390
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Filing Dt:
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09/15/1998
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Title:
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METALLIZATION ETCHING TECHNIQUES FOR REDUCING POST-ETCH CORROSION OF METAL LINES
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09161793
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Filing Dt:
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09/28/1998
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Title:
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METHOD OF ENHANCING SEMICONDUCTOR WAFER RELEASE
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09161861
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Filing Dt:
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09/28/1998
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Title:
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STACKED CAPACITATOR MEMORY CELL AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09162867
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Filing Dt:
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09/29/1998
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Title:
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MEMORY CELL WITH A STACKED CAPACITOR
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09163670
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Filing Dt:
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09/30/1998
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Title:
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6 1/4 F2 DRAM CELL STRUCTURE WITH FOUR NODES PER BITLINE-STUD AND TWO TOPOLOGICAL WORDLINE LEVELS
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09175267
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Filing Dt:
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10/20/1998
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Title:
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METHOD FOR FABRICATING TRANSISTORS
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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09186515
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Filing Dt:
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11/05/1998
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Title:
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FUSE LAYOUT FOR IMPROVED FUSE BLOW PROCESS WINDOW
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09200338
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Filing Dt:
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11/25/1998
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Title:
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DELAY LOCK LOOP
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09204031
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Filing Dt:
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12/01/1998
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Title:
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SILICON OXYNITRIDE CAP FOR FLUORINATED SILICATE GLASS FILM IN INTERMETAL DIELECTRIC SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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02/29/2000
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Application #:
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09204402
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Filing Dt:
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12/02/1998
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Title:
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MEASUREMENT SYSTEM AND METHOD FOR MEASURING CRITICAL DIMENSIONS USING ELLIPSOMETRY
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09209198
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Filing Dt:
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12/10/1998
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Title:
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EXTENDED TRENCH FOR PREVENTING INTERACTION BETWEEN COMPONENTS OF STACKED CAPACITORS
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09213469
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Filing Dt:
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12/17/1998
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Title:
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METHODS FOR ENHANCING THE METAL REMOVAL RATE DURING THE CHEMICAL-MECHANICAL POLISHING PROCESS OF A SEMICONDUCTOR
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|
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09215607
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Filing Dt:
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12/17/1998
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Title:
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ADJUSTABLE STRENGTH DRIVER CIRCUIT AND METHOD OF ADJUSTMENT
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|
|
|
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09234341
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Filing Dt:
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01/20/1999
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|
Title:
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METHOD OF MAKING A MICROELECTRONIC STRUCTURE
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|
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|
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09253996
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Filing Dt:
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02/22/1999
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Title:
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ARRANGEMENT FOR CONTROLLING VOLTAGE GENERATORS IN MULTI VOLTAGE GENERATOR CHIPS SUCH AS DRAMS
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|
|
|
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09266038
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Filing Dt:
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03/11/1999
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Title:
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METHOD FOR NONDESTRUCTIVE MEASUREMENT OF DOPANT CONCENTRATIONS AND PROFILES IN THE DRIFT REGION OF CERTAIN SEMICONDUCTOR DEVICES
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|
|
|
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09266039
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Filing Dt:
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03/11/1999
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Title:
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METHOD FOR NONDESTRUCTIVE MEASUREMENT OF MINORITY CARRIER DIFFUSION LENGTH AND MINORITY CARRIER LIFETIME IN SEMICONDUCTOR DEVICES
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|
|
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09299364
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Filing Dt:
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04/26/1999
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Title:
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RADIATION-SENSITIVE MIXTURE AND ITS USE
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09299365
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Filing Dt:
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04/26/1999
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Title:
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FILM-FORMING POLYMERS
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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09313424
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Filing Dt:
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05/17/1999
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Title:
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SOI SEMICONDUCTOR CONFIGURATION AND METHOD OF FABRICATING THE SAME
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09393700
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Filing Dt:
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09/10/1999
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Title:
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IMPROVED PROCESS FOR DRAM CELL PRODUCTION
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|
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09408685
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Filing Dt:
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09/30/1999
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Title:
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INTEGRATED CIRCUIT HAVING ADJUSTABLE DELAY UNITS FOR CLOCK SIGNALS
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|
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|
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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09408687
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Filing Dt:
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09/30/1999
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Title:
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INTEGRATED CIRCUIT WITH ADJUSTABLE DELAY UNIT
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09429834
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Filing Dt:
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10/29/1999
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Title:
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METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT WITH LOW THRESHOLD VOLTAGE DIFFERENCES OF THE TRANISTORS THEREIN
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09431529
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Filing Dt:
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11/01/1999
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Title:
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READ/WRITE MEMORY WITH SELF-TEST DEVICE AND ASSOCIATED TEST METHOD
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09437956
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Filing Dt:
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11/10/1999
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|
Title:
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SEMICONDUCTOR CHIP CONFIGURATION AND METHOD OF CONTROLLING A SEMICONDUCTOR CHIP
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|
|
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09440721
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Filing Dt:
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11/15/1999
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Title:
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CIRCUIT CONFIGURATION WITH A TEMPERATURE-DEPENDENT SEMICONDUCTOR COMPONENT TEST AND REPAIR LOGIC CIRCUIT
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09440818
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Filing Dt:
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11/15/1999
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Title:
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FERROELECTRIC MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09443751
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Filing Dt:
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11/19/1999
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Title:
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MAGNETIC MEMORY
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09449362
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Filing Dt:
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11/24/1999
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Title:
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METHOD OF FORMING A BURIED PLATE
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|
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09449716
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Filing Dt:
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11/24/1999
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Title:
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SEMICONDUCTOR COMPONENT HAVING AT LEAST ONE CAPACITOR AND METHODS FOR FABRICATING IT
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09470310
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Filing Dt:
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12/22/1999
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Title:
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INTEGRATED CIRCUIT HAVING A DECODER
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|
|
|
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Patent #:
|
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Issue Dt:
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11/06/2001
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Application #:
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09478312
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Filing Dt:
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01/06/2000
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Title:
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STACK CAPACITOR WITH IMPROVED PLUG CUNDUCTIVITY
|
|
|
|
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09481637
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Filing Dt:
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01/12/2000
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|
Title:
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PROCESS FOR PRODUCING ULTRA-PURE WATER, AND CONFIGURATION FOR CARRYING OUT A PROCESS OF THIS NATURE
|
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|
|
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Patent #:
|
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Issue Dt:
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01/08/2002
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Application #:
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09481639
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Filing Dt:
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01/12/2000
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Title:
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CONVEYING SYSTEM
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|
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09483738
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Filing Dt:
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01/14/2000
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Title:
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Mehtod for repairing defective memory cells of an integrated semiconductor memory
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|
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Patent #:
|
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Issue Dt:
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09/27/2005
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Application #:
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09484781
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Filing Dt:
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01/18/2000
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT AND METHOD FOR FUNCTIONAL TESTING OF PAD CELLS
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|
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Patent #:
|
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Issue Dt:
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01/08/2002
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Application #:
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09492654
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Filing Dt:
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01/27/2000
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Title:
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Method for improving the quality of metal conductor tracks on semiconductor structures
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09492655
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Filing Dt:
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01/27/2000
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Title:
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METHOD FOR PRODUCING STRUCTURES ON THE SURFACE OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09492656
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Filing Dt:
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01/27/2000
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Title:
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Method for improving the readability of alignment marks
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09494774
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Filing Dt:
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01/31/2000
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Title:
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Method for fabricating an isolation trench using an auxiliary layer
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09503992
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Filing Dt:
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02/14/2000
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Title:
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Apparatus and method for forming controlled deep trench top isolation layers
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09504274
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Filing Dt:
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02/15/2000
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Title:
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EXHAUST APPARATUS
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09504275
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Filing Dt:
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02/15/2000
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Title:
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Electrical test structure on a semiconductor substrate and test method
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09505379
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Filing Dt:
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02/16/2000
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Title:
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SEMICONDUCTOR MEMORY HAVING MEMORY BANK DECODERS DISPOSED SYMMETRICALLY ON A CHIP
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09511812
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Filing Dt:
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02/24/2000
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Title:
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SEMICONDUCTOR MEMORY CONFIGURATION WITH DUMMY COMPONENTS ON CONTINUOUS DIFFUSION REGIONS
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09513587
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Filing Dt:
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02/25/2000
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Title:
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Integrated memory
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09514265
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Filing Dt:
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02/28/2000
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Title:
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METHOD FOR MOUNTING A SEMICONDUCTOR CHIP ON A CARRIER LAYER AND DEVICE FOR CARRYING OUT THE METHOD
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09514268
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Filing Dt:
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02/28/2000
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Title:
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Semiconductor memory configuration with a bit-line twist
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09519541
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Filing Dt:
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03/06/2000
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Title:
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Integrated circuit for producing two output clock signals at levels which do not overlap in time
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09523146
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Filing Dt:
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02/22/2000
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Title:
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Integrated semiconductor memory configuration with self-buffering of supply voltages
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09524240
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Filing Dt:
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03/13/2000
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Title:
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CIRCUIT CONFIGURATION FOR THE INTERFERENCE- FREE INITIALIZATION OF DELAYED LOCKED LOOP CIRCUITS WITH FAST LOCK
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09525820
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Filing Dt:
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03/15/2000
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Title:
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CONFIGURATION HAVING A FIELD-EFFECT TRANSISTOR HAVING A SHORT CHANNEL LENGTH AND AN ADJUSTABLE THRESHOLD VOLTAGE
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09603631
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Filing Dt:
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06/26/2000
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Title:
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INTEGRATED CIRCUIT WITH IMPROVED OFF CHIP DRIVERS
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09642734
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Filing Dt:
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08/17/2000
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Title:
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Test circuit for testing a digital semiconductor circuit configuration
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09771912
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Filing Dt:
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01/29/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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LEAD FRAME, CIRCUIT BOARD WITH LEAD FRAME, AND METHOD FOR PRODUCING THE LEAD FRAME
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09774743
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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MEMORY CELL WITH A STACKED CAPACITOR
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09793344
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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MEMORY SYSTEM
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09806427
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Filing Dt:
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07/03/2001
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Title:
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DRAM CELL ARRANGEMENT
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09806614
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Filing Dt:
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05/11/2001
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Title:
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DRAM CELL SYSTEM AND METHOD FOR PRODUCING SAME
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09817578
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Filing Dt:
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03/26/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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Circuit configuration for generating a reference voltage for reading a ferroelectric memory
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09821853
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Filing Dt:
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03/30/2001
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Title:
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SUBSTRATE ASSEMBLY HAVING A DEPRESSION SUITABLE FOR AN INTEGRATED CIRCUIT CONFIGURATION AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09849910
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Filing Dt:
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05/04/2001
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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FERROELECTRIC TRANSISTOR AND METHOD FOR FABRICATING IT
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09850585
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Filing Dt:
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05/07/2001
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Publication #:
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Pub Dt:
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12/27/2001
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Title:
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A METHOD FOR PREVENTING ETCHING-INDUCED DAMAGE TO A METAL OXIDE FILM BY PATTERNING THE FILM AFTER A NUCLEATION ANNEAL BUT WHILE STILL AMORPHOUS AND THEN THERMALLY ANNEALING TO CRYSTALLIZE
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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09857262
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Filing Dt:
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07/16/2001
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Title:
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FEMFET DEVICE AND METHOD FOR PRODUCING SAME
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09861431
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Filing Dt:
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05/18/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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FIELD-EFFECT-CONTROLLED TRANSISTOR AND METHOD FOR FABRICATING THE TRANSISTOR
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09867291
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Filing Dt:
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05/29/2001
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Publication #:
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Pub Dt:
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01/03/2002
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Title:
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NEW COMPLEX OF AN ELEMENT OF TRANSITION GROUP IV OR V FOR FORMING AN IMPROVED PRECURSOR COMBINATION
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09873229
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Filing Dt:
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06/04/2001
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Publication #:
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Pub Dt:
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01/31/2002
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Title:
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METHOD OF STRUCTURING A METAL-CONTAINING LAYER
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09873231
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Filing Dt:
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06/04/2001
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Publication #:
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Pub Dt:
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12/27/2001
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Title:
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INTEGRATED CIRCUIT CONFIGURATION AND METHOD FOR MANUFACTURING IT
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09883901
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Filing Dt:
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06/18/2001
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Publication #:
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Pub Dt:
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12/27/2001
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Title:
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CIRCUIT CONFIGURATION HAVING AT LEAST ONE NANOELECTRONIC COMPONENT AND METHOD FOR FABRICATING THE COMPONENT
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09888023
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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INTEGRATED MEMORY WITH REDUNDANCY
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09891114
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Filing Dt:
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06/25/2001
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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CAPACITOR ELECTRODE ARRANGEMENT WITH OXYGEN IRIDIUM BETWEEN SILICON AND OXYGEN BARRIER LAYER
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09904358
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Filing Dt:
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07/12/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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INTEGRATED MEMORY
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