Total properties:
135
Page
1
of
2
Pages:
1 2
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09546421
|
Filing Dt:
|
04/10/2000
|
|
Title:
|
Method for singling semiconductor components and semiconductor component singling device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09549275
|
Filing Dt:
|
04/14/2000
|
|
Title:
|
Semiconductor memory with a plurality of memory banks
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09550212
|
Filing Dt:
|
04/17/2000
|
|
Title:
|
CIRCUIT CONFIGURATION FOR THR BURN-IN TEST OF A SEMICONDUCTOR MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09553126
|
Filing Dt:
|
04/19/2000
|
|
Title:
|
CONFIGURATION FOR CARRYING OUT BURN-IN PROCESSING OPERATIONS OF SEMICONDUCTOR DEVICES AT WAFER LEVEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09553127
|
Filing Dt:
|
04/19/2000
|
|
Title:
|
Semiconductor memory configuration with a built-in-self-test
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09553128
|
Filing Dt:
|
04/19/2000
|
|
Title:
|
Semiconductor memory of the random access type with a bus system organized in two planes
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09560542
|
Filing Dt:
|
04/28/2000
|
|
Title:
|
BOTTOM RESIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2002
|
Application #:
|
09566067
|
Filing Dt:
|
05/05/2000
|
|
Title:
|
Circuit configuration for programming an electrically programmable element
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09566936
|
Filing Dt:
|
05/08/2000
|
|
Title:
|
Method for cob mounting of electronic chip on a circuit board
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09568941
|
Filing Dt:
|
05/11/2000
|
|
Title:
|
Circuit configuration for monitoring states of a memory device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09571486
|
Filing Dt:
|
05/15/2000
|
|
Title:
|
Circuit configuration for programming an electrically programmable element
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09574702
|
Filing Dt:
|
05/18/2000
|
|
Title:
|
METHOD OF TESTING A SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR MEMORY WITH A TEST DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2003
|
Application #:
|
09574823
|
Filing Dt:
|
05/19/2000
|
|
Title:
|
WAFER PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09575056
|
Filing Dt:
|
05/19/2000
|
|
Title:
|
INTEGRATED MEMORY HAVING A REDUNDANCY FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09577060
|
Filing Dt:
|
05/22/2000
|
|
Title:
|
SEMICONDUCTOR MODULE WITH A NUMBER OF SEMICONDUCTOR CHIPS AND A CONDUCTIVE CONNECTION BETWEEN THE SEMICONDUCTOR CHIPS BY FLEXIBLE TAPES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
09577065
|
Filing Dt:
|
05/22/2000
|
|
Title:
|
SEMICONDUCTOR MODULE HAVING INTERCONNECTED SEMICONDUCTOR CHIPS DISPOSED ONE ABOVE THE OTHER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2003
|
Application #:
|
09580034
|
Filing Dt:
|
05/26/2000
|
|
Title:
|
CIRCUIT CONFIGURATION FOR REPAIRING A SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09580982
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
Integrated memory having redundant units of memory cells, and test method for the redundant units
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09580983
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
METHOD FOR BONDING CONDUCTORS, IN PARTICULAR BEAM LEADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
09580984
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
CHIP CARRIER HAVING VENTILATION CHANNELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09580986
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
Integrated memory with a block writing function and global amplifiers requiring less space
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09583131
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
Electronic circuit having a flexible intermediate layer between electronic components and a heat sink
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09584329
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
Integrated memory having 2-transistor/2-capacitor memory cells
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2002
|
Application #:
|
09597348
|
Filing Dt:
|
06/19/2000
|
|
Title:
|
TRANSPORT DEVICE FOR ELECTRONIC COMPONENTS WITH AN ANTICONTAMINATION COATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09603742
|
Filing Dt:
|
06/26/2000
|
|
Title:
|
Integrated circuit having a command decoder
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09603749
|
Filing Dt:
|
06/26/2000
|
|
Title:
|
INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09606589
|
Filing Dt:
|
06/29/2000
|
|
Title:
|
An Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09606594
|
Filing Dt:
|
06/29/2000
|
|
Title:
|
Integrated circuit for generating a phase-shifted output clock signal from a clock signal
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09608563
|
Filing Dt:
|
06/30/2000
|
|
Title:
|
Integrated circuit with a phase locked loop
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09617649
|
Filing Dt:
|
07/17/2000
|
|
Title:
|
Synchronous integrated memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09618124
|
Filing Dt:
|
07/17/2000
|
|
Title:
|
Integrated memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09621430
|
Filing Dt:
|
07/21/2000
|
|
Title:
|
INTEGRATED SEMICONDUCTOR CIRCUIT WITH AN INCREASED OPERATING VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
09621905
|
Filing Dt:
|
07/24/2000
|
|
Title:
|
SYNCHRONOUS INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09630972
|
Filing Dt:
|
08/02/2000
|
|
Title:
|
ARRANGEMENT AND METHOD FOR TESTING A MULTIPLICITY OF SEMICONDUCTOR CHIPS AT THE WAFER LEVEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09633704
|
Filing Dt:
|
08/07/2000
|
|
Title:
|
CONTACT CONNECTION OF METAL INTERCONNECTS OF AN INTEGRATED SEMICONDUCTOR CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09642325
|
Filing Dt:
|
08/21/2000
|
|
Title:
|
Method for fabricating a microelectronic structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
09642326
|
Filing Dt:
|
08/21/2000
|
|
Title:
|
CONFIGURATION AND METHOD FOR PRODUCING TEST SIGNALS FOR TESTING A MULTIPLICITY OF SEMICONDUCTOR CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09645765
|
Filing Dt:
|
08/25/2000
|
|
Title:
|
METHOD OF FABRICATING INTEGRATED CIRCUITS HAVING TRANSISTORS AND FURTHER SEMICONDUCTOR ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09651492
|
Filing Dt:
|
08/30/2000
|
|
Title:
|
Epitaxy layer and method for its production
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09658713
|
Filing Dt:
|
09/11/2000
|
|
Title:
|
METHOD FOR PRODUCING AN ELECTRICAL CONNECTION BETWEEN THE FRONT AND REAR SIDES OF SEMICONDUCTOR CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09660453
|
Filing Dt:
|
09/12/2000
|
|
Title:
|
DRAM CELL ARRANGEMENT AND METHOD FOR FABRICATING IT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09662255
|
Filing Dt:
|
09/14/2000
|
|
Title:
|
Integrated memory with two burst operation types
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09662256
|
Filing Dt:
|
09/14/2000
|
|
Title:
|
Integrated memory having memory cells and reference cells
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09662257
|
Filing Dt:
|
09/14/2000
|
|
Title:
|
Integrated memory with at least two plate segments
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09662957
|
Filing Dt:
|
09/15/2000
|
|
Title:
|
INPUT BUFFER OF AN INTEGRATED SEMICONDUCTOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09663569
|
Filing Dt:
|
09/15/2000
|
|
Title:
|
PATTERNING OF CONTACT AREAS IN MULTILAYER METALIZATION CONFIGURATIONS OF SEMICONDUCTOR COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09663583
|
Filing Dt:
|
09/18/2000
|
|
Title:
|
Segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit lines
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09666526
|
Filing Dt:
|
09/18/2000
|
|
Title:
|
DEPOSITION OF VARIOUS BASE LAYERS FOR SELECTIVE LAYER GROWTH IN SEMICONDUCTOR PRODUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09671452
|
Filing Dt:
|
09/27/2000
|
|
Title:
|
CONFIGURATION FOR VOLTAGE BUFFERING IN A DYNAMIC MEMORY USING CMOS TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09672625
|
Filing Dt:
|
09/28/2000
|
|
Title:
|
CONFIGURATION FOR REDUCING THE NUMBER OF MEASURING PADS ON A SEMICONDUCTOR CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09677321
|
Filing Dt:
|
09/29/2000
|
|
Title:
|
TRIMMING MASK WITH SEMITRANSPARENT PHASE-SHIFTING REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09677357
|
Filing Dt:
|
10/02/2000
|
|
Title:
|
Integrated dynamic semiconductor memory having redundant units of memory cells, and a method for self-repair
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09677433
|
Filing Dt:
|
10/02/2000
|
|
Title:
|
INTEGRATED CIRCUIT CONFIGURATION WITH AT LEAST ONE CAPACITOR AND METHOD FOR PRODUCING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09685659
|
Filing Dt:
|
10/10/2000
|
|
Title:
|
CONFIGURATION AND METHOD FOR CONNECTING CONDUCTOR TRACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09692118
|
Filing Dt:
|
10/19/2000
|
|
Title:
|
Dram cell circuit
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2002
|
Application #:
|
09693769
|
Filing Dt:
|
10/20/2000
|
|
Title:
|
controlling transistor threshold potentials using substrate potentials
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09693778
|
Filing Dt:
|
10/20/2000
|
|
Title:
|
Voltage generator with superimposed reference voltage and deactivation signal
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09699982
|
Filing Dt:
|
10/30/2000
|
|
Title:
|
Integrated memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09699983
|
Filing Dt:
|
10/30/2000
|
|
Title:
|
Integrated memory having cells of the two-transistor/two-capacitor type
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
09705599
|
Filing Dt:
|
11/03/2000
|
|
Title:
|
NEEDLE-CARD ADJUSTING DEVICE FOR PLANARIZING NEEDLE SETS ON A NEEDLE CARD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09711864
|
Filing Dt:
|
11/13/2000
|
|
Title:
|
Memory device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09716871
|
Filing Dt:
|
11/20/2000
|
|
Title:
|
Method for carrying out auto refresh sequences on a DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
09716901
|
Filing Dt:
|
11/20/2000
|
|
Title:
|
STANDBY VOLTAGE CONTROLLER AND VOLTAGE DIVIDER IN A CONFIGURATION FOR SUPPLYING VOLTAGES TO AN ELECTRONIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09718937
|
Filing Dt:
|
11/22/2000
|
|
Title:
|
INTEGRATED MEMORY HAVING MEMORY CELLS AND REFERENCE CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09722118
|
Filing Dt:
|
11/27/2000
|
|
Title:
|
METHOD OF TESTING MEMORY CELLS WITH A HYSTERESIS CURVE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
09725346
|
Filing Dt:
|
11/29/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2001
| | | | |
|
Title:
|
SUBSTRATE WITH AT LEAST TWO METAL STRUCTURES DEPOSITED THEREON, AND METHOD FOR FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09726960
|
Filing Dt:
|
11/30/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2001
| | | | |
|
Title:
|
METHOD FOR FABRICATING A FIELD-EFFECT TRANSISTOR HAVING AN ANTI-PUNCH-THROUGH IMPLANTATION REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
09729062
|
Filing Dt:
|
12/04/2000
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2001
| | | | |
|
Title:
|
LITHOGRAPHY METHOD AND LITHOGRAPHY MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09729066
|
Filing Dt:
|
12/04/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2001
| | | | |
|
Title:
|
Method for producing a metal layer with a given thickness
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09732136
|
Filing Dt:
|
12/07/2000
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2001
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT HAVING A PARTICULAR FUNCTIONALITY REQUIRED BY A USER OF THE CIRCUIT AND HAVING FIRST STRUCTURE TO PRODUCE THE PARTICULAR FUNCTIONALITY AND SECOND STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
09734467
|
Filing Dt:
|
12/11/2000
|
|
Publication #:
|
|
Pub Dt:
|
01/24/2002
| | | | |
|
Title:
|
METHODS FOR PRODUCING A STRUCTURED METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09735338
|
Filing Dt:
|
12/12/2000
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2001
| | | | |
|
Title:
|
INTEGRATED DYNAMIC SEMICONDUCTOR MEMORY WITH TIME CONTROLLED READ ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09737056
|
Filing Dt:
|
12/14/2000
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2001
| | | | |
|
Title:
|
METHOD OF PRODUCING A SEMICONDUCTOR DEVICE COMPRISING A CLEANING PROCESS FOR REMOVING SILICON-CONTAINING MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09737057
|
Filing Dt:
|
12/14/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2001
| | | | |
|
Title:
|
CONFIGURATION FOR TRIMMING REFERENCE VOLTAGES IN SEMICONDUCTOR CHIPS, IN PARTICULAR SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09737060
|
Filing Dt:
|
12/14/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2001
| | | | |
|
Title:
|
BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09739543
|
Filing Dt:
|
12/15/2000
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
|
Title:
|
Semiconductor memory of the dynamic random access type (DRAM) and method for actuating a memory cell
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
09740633
|
Filing Dt:
|
12/18/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2001
| | | | |
|
Title:
|
CONFIGURATION FOR MEASUREMENT OF INTERNAL VOLTAGES OF AN INTEGRATED SEMICONDUCTOR APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09741308
|
Filing Dt:
|
12/18/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2001
| | | | |
|
Title:
|
DIELECTRIC FILLING OF ELECTRICAL WIRING PLANES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09962703
|
Filing Dt:
|
09/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
|
Title:
|
INTEGRATED MEMORY HAVING MEMORY CELLS AND REFERENCE CELLS, AND CORRESPONDING OPERATING METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09963005
|
Filing Dt:
|
09/25/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/01/2002
| | | | |
|
Title:
|
PLANT FOR PRODUCING SEMICONDUCTOR PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09963006
|
Filing Dt:
|
09/25/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/18/2002
| | | | |
|
Title:
|
OPERATING METHOD FOR AN INTEGRATED MEMORY HAVING WRITEABLE MEMORY CELLS AND CORRESPONDING INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
09963956
|
Filing Dt:
|
09/26/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
INSTALLATION FOR PROCESSING WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
09963957
|
Filing Dt:
|
09/26/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/11/2002
| | | | |
|
Title:
|
PLANT FOR PRODUCING SEMICONDUCTOR PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09968287
|
Filing Dt:
|
10/01/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/18/2002
| | | | |
|
Title:
|
DEVICE FOR EVALUATING CELL RESISTANCES IN A MAGNETORESISTIVE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09968304
|
Filing Dt:
|
10/01/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
|
Title:
|
MEMORY CELL CONFIGURATION WITH CAPACITOR ON OPPOSITE SURFACE OF SUBSTRATE AND METHOD FOR FABRICATION THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
09968575
|
Filing Dt:
|
10/01/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
|
Title:
|
DEVICE FOR EVALUATING CELL RESISTANCES IN A MAGNETORESISTIVE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
09968576
|
Filing Dt:
|
10/01/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2002
| | | | |
|
Title:
|
METHOD FOR PROCESSING WAFER BY APPLYING LAYER TO PROTECT THE BACKSIDE DURING A TEMPERING STEP AND REMOVING CONTAMINATED PORTIONS OF THE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
09980386
|
Filing Dt:
|
03/19/2002
|
|
Title:
|
SEMICONDUCTOR STORAGE COMPONENT WITH STORAGE CELLS, LOGIC AREAS AND FILLING STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2003
|
Application #:
|
09980811
|
Filing Dt:
|
03/11/2002
|
|
Title:
|
SOI DRAM WITHOUT FLOATING BODY EFFECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09992977
|
Filing Dt:
|
11/19/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2002
| | | | |
|
Title:
|
METHOD FOR DEPOSITING A TWO-LAYER DIFFUSION BARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
09996279
|
Filing Dt:
|
11/28/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2002
| | | | |
|
Title:
|
DOUBLE GATE MOSFET TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09996280
|
Filing Dt:
|
11/28/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
CHARGE PUMP WITH CHARGE EQUALIZATION FOR IMPROVED EFFICIENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10009979
|
Filing Dt:
|
03/27/2002
|
|
Title:
|
COMPUTER-ASSISTED METHOD FOR THE PARALLEL CALCULATION OF THE OPERATING POINT OF ELECTRIC CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
10011133
|
Filing Dt:
|
11/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/18/2002
| | | | |
|
Title:
|
CAPACITOR FOR SEMICONDUCTOR CONFIGURATION AND METHOD FOR FABRICATING A DIELECTRIC LAYER THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
10013234
|
Filing Dt:
|
12/10/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2002
| | | | |
|
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10013256
|
Filing Dt:
|
12/10/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/01/2002
| | | | |
|
Title:
|
CONFIGURATION OF FUSES IN SEMICONDUCTOR STRUCTURES WITH CU METALLIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10013298
|
Filing Dt:
|
12/10/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2002
| | | | |
|
Title:
|
FUSE FOR A SEMICONDUCTOR CONFIGURATION AND METHOD FOR ITS PRODUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10022226
|
Filing Dt:
|
12/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/11/2002
| | | | |
|
Title:
|
ELECTRONIC COMPONENT WITH FLEXIBLE BONDING PADS AND METHOD OF PRODUCING SUCH A COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10022605
|
Filing Dt:
|
12/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2002
| | | | |
|
Title:
|
MULTICHIP MODULE FOR LOC MOUNTING AND METHOD FOR PRODUCING THE MULTICHIP MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
10022606
|
Filing Dt:
|
12/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/18/2002
| | | | |
|
Title:
|
ELECTRONIC CONFIGURATION WITH FLEXIBLE BONDING PADS
|
|
