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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09225665
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Filing Dt:
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01/05/1999
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Publication #:
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Pub Dt:
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01/03/2002
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Title:
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SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09228178
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Filing Dt:
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01/11/1999
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Publication #:
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Pub Dt:
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03/14/2002
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Title:
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SYSTEM AND METHOD FOR DETERMINING YIELD IMPACT FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09238543
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Filing Dt:
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01/28/1999
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Title:
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LIGHT ABSORPTION LAYER FOR LASER BLOWN FUSES
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09252372
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Filing Dt:
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02/18/1999
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Title:
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USE OF DUMMY POLY SPACERS AND DIVOT FILL TECHNIQUES FOR DT-ALIGNED PROCESSING AFTER STI FORMATION FOR ADVANCED DEEP TRENCH CAPACITOR DRAMS
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09256930
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Filing Dt:
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02/24/1999
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Title:
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SYSTEM AND METHOD FOR AUTOMATED DEFECT INSPECTION OF PHOTOMASKS
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09266473
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Filing Dt:
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03/11/1999
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Title:
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EXTRUSION ENHANCED MASK FOR IMPROVING WINDOW
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09271684
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Filing Dt:
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03/18/1999
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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CMP UNIFORMITY
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09273842
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Filing Dt:
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03/22/1999
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Title:
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SKEW POINTER GENERATION
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09276027
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Filing Dt:
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03/25/1999
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Title:
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SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09277669
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Filing Dt:
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03/26/1999
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Title:
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STACKED CAPACITOR MEMORY CELL AND METHOD OF MANUFACUTRE
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09277673
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Filing Dt:
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03/26/1999
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Title:
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IN-SITU METHOD FOR PREPARING AND HIGHLIGHTING OF DEFECTS FOR FAILURE ANALYSIS
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09280615
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Filing Dt:
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03/29/1999
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Title:
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METHOD FOR REDUCING CORNER ROUNDING IN MASK FABRICATION UTILIZING ELLIPTICAL ENERGY BEAM
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09281020
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Filing Dt:
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03/30/1999
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Title:
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PULSE WIDTH DETECTION
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09282745
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Filing Dt:
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03/31/1999
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Title:
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METHOD OF IMPROVING THE ETCH RESISTANCE OF CHEMICALLY AMPLIFIED PHOTORESISTS BY INTRODUCING SILICON AFTER PATTERNING
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09290319
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Filing Dt:
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04/12/1999
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Title:
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IMPROVED TOP LAYER IMAGING LITHOGRAPHY FOR SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09299979
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Filing Dt:
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04/27/1999
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Title:
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YIELD PREDICTION AND STATISTICAL PROCESS CONTROL USING PREDICTED DEFECT RELATED YIELD LOSS
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09302757
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Filing Dt:
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04/30/1999
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Title:
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STATIC RANDOM ACCESS MEMORY (SRAM)
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09302768
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Filing Dt:
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04/30/1999
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Title:
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DOUBLE GATED TRANSISTOR
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09312974
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Filing Dt:
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05/17/1999
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Title:
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ON CHIP PROGRAMMABLE DATA PATTERN GENERATOR FOR SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09313016
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Filing Dt:
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05/17/1999
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Title:
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ON CHIP DATA COMPARATOR WITH VARIABLE DATA AND COMPARE RESULT COMPRESSION
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09314358
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Filing Dt:
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05/19/1999
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Title:
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DIFFERENTIAL TRENCH OPEN PROCESS
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09323363
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Filing Dt:
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06/01/1999
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Title:
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SENSING OF MEMORY CELL VIA A PLATELINE
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09324926
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Filing Dt:
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06/03/1999
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Title:
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LOW TEMPERATURE SACRIFICIAL OXIDE FORMATION
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09324927
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Filing Dt:
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06/03/1999
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Title:
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LOW TEMPERATURE SELF-ALIGNED COLLAR FORMATION
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09326889
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Filing Dt:
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06/07/1999
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Title:
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LAYOUT AND WIRING SCHEME FOR MEMORY CELLS WITH VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09327711
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Filing Dt:
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06/08/1999
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Title:
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LOW TEMPERFATURE OXIDATION OF CONDUCTIVE LAYERS FOR SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09328763
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Filing Dt:
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06/09/1999
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Title:
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METHOD FOR EXPANDING TRENCHES BY AN ANISOTROPIC WET ETCH
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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09337168
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Filing Dt:
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06/21/1999
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Title:
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DEVICE PERFORMANCE BY EMPLOYING AN IMPROVED METHOD FOR FORMING HALO IMPLANTS
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09339519
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Filing Dt:
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06/24/1999
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Title:
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SEMICONDUCTOR MANUFACTURING METHODS
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Patent #:
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|
Issue Dt:
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03/12/2002
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Application #:
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09374537
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Filing Dt:
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08/16/1999
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Title:
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METHOD FOR FABRICATING 4F2 MEMORY CELLS WITH IMPROVED GATE CONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09374538
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Filing Dt:
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08/16/1999
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Title:
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METHOD FOR FABRICATION OF ENLARGED STACKED CAPACITORS USING ISOTROPIC ETCHING
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09383666
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Filing Dt:
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08/26/1999
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Title:
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SIDEWALL OXIDE PROCESS FOR IMPROVED SHALLOW JUNCTION FORMATION IN SUPPORT REGION
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09395952
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Filing Dt:
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09/14/1999
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Title:
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PROCESS FOR IMPROVING THE THICKNESS UNIFORMITY OF A THIN LAYER IN SEMICONCUCTOR WAFER FABRICATION
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09406890
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Filing Dt:
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09/28/1999
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Title:
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REDUCING IMPACT OF COUPLING NOISE IN MULTI-LEVEL BIELINE ARCHITECTURE
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09406892
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Filing Dt:
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09/28/1999
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Title:
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REDUCED IMPACT FROM COUPLING NOISE IN DIAGONAL BITLINE ARCHITECTURES
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09408246
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Filing Dt:
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09/29/1999
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Title:
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SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09411551
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Filing Dt:
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10/04/1999
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Title:
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LOCALLY FOLDED SPLIT LEVEL BITLINE WIRING
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09432063
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Filing Dt:
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11/02/1999
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Title:
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SPACER PROCESS TO ELIMINATE CORNER TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09432064
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Filing Dt:
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11/02/1999
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Title:
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EFFICIENT REDUNDANCY CALCULATION SYSTEM AND METHOD FOR VARIOUS TYPES OF MEMORY DEVICES
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09442982
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Filing Dt:
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11/18/1999
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Title:
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MEMORY CELL
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09455855
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Filing Dt:
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12/07/1999
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Title:
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ADVANCED BIT FAIL MAP COMPRESSION WITH FAIL SIGNATURE ANALYSIS
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09460318
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Filing Dt:
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12/14/1999
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Title:
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SELF-ALIGNED LDD FORMATION WITH ONE-STEP IMPLANTATION FOR TRANSISTOR FORMATION
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09476449
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Filing Dt:
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12/30/1999
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Title:
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AUTOMATED CREATION OF SPECIFIC TEST PROGRAMS FROM COMPLEX TEST PROGRAMS
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09476450
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Filing Dt:
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12/30/1999
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Title:
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USAGE OF REDUNDANCY DATA FOR DISPLAYING FAILURE BIT MAPS FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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01/01/2002
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Application #:
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09476726
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Filing Dt:
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12/30/1999
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Title:
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METHOD FOR MAKING AN ANTI-FUSE
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09525093
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Filing Dt:
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03/14/2000
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Title:
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MEMORY CELL FOR PLATELINE SENSING
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09638309
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Filing Dt:
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08/14/2000
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Title:
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PROCESS FOR IMPROVING THE THICKNESS UNIFORMITY OF A THIN OXIDE LAYER IN SEMICONDUCTOR WAFER FABRICATION
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09639986
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Filing Dt:
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08/16/2000
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Title:
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CMP UNIFORMITY
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09670742
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Filing Dt:
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09/27/2000
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Title:
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DOUBLE GATED TRANSISTOR
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09687883
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Filing Dt:
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10/13/2000
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Title:
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PULSE WIDTH DETECTION
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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09733665
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Filing Dt:
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12/08/2000
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Publication #:
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Pub Dt:
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05/30/2002
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Title:
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SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09733666
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Filing Dt:
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12/08/2000
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09742133
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Filing Dt:
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12/20/2000
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Publication #:
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Pub Dt:
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06/21/2001
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Title:
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Method for operating a current sense amplifier
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09745541
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Filing Dt:
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12/21/2000
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Publication #:
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Pub Dt:
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06/28/2001
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Title:
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DICING CONFIGURATION FOR SEPARATING A SEMICONDUCTOR COMPONENT FROM A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09745567
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Filing Dt:
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12/21/2000
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Publication #:
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Pub Dt:
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06/28/2001
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Title:
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CONFIGURATION FOR TESTING CHIPS USING A PRINTED CIRCUIT BOARD
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09750399
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Filing Dt:
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12/28/2000
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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CIRCUIT CONFIGURATION FOR AN INTEGRATED SEMICONDUCTOR MEMORY WITH COLUMN ACCESS
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09750531
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Filing Dt:
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12/28/2000
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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METHOD FOR FABRICATING A PATTERNED METAL-OXIDE-CONTAINING LAYER
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09751958
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Filing Dt:
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12/29/2000
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Publication #:
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Pub Dt:
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07/05/2001
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Title:
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Integrated semiconductor memory with a memory unit for storing addresses of defective memory cells
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09752920
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Filing Dt:
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01/02/2001
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Publication #:
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Pub Dt:
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07/05/2001
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Title:
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CIRCUIT CONFIGURATION FOR REGULATING THE POWER CONSUMPTION OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09753589
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Filing Dt:
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01/03/2001
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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METHOD FOR PRODUCING TRENCHES FOR DRAM CELL CONFIGURATIONS
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09758997
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Filing Dt:
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01/11/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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METHOD OF PRODUCING ALIGNMENT MARKS
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09758998
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Filing Dt:
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01/11/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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PULSE GENERATOR FOR GENERATING AN OUTPUT IN RESPONSE TO A DELAY TIME
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09761804
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Filing Dt:
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01/16/2001
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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CIRCUIT CONFIGURATION FOR MEASURING THE CAPACITANCE OF STRUCTURES IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09761815
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Filing Dt:
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01/16/2001
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Publication #:
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Pub Dt:
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10/11/2001
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Title:
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INTEGRATED CIRCUIT WITH A DIFFERENTIAL AMPLIFIER
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09766321
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Filing Dt:
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01/19/2001
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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CIRCUIT CONFIGURATION HAVING A VARIABLE NUMBER OF DATA OUTPUTS AND DEVICE FOR READING OUT DATA FROM THE CIRCUIT CONFIGURATION WITH THE VARIABLE NUMBER OF DATA OUTPUTS
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09766465
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Filing Dt:
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01/19/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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Method and apparatus for alternate operation of a random access memory in single-memory operating mode and in combined multi-memory operating mode
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09767380
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Filing Dt:
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01/22/2001
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Publication #:
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Pub Dt:
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10/04/2001
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Title:
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SEMICONDUCTOR MEMORY CONFIGURATION WITH A REFRESH LOGIC CIRCUIT, AND METHOD OF REFRESHING A MEMORY CONTENT OF THE SEMICONDUCTOR MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09768391
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Filing Dt:
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01/24/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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REACTOR FOR MANUFACTURING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09768393
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Filing Dt:
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01/24/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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METHOD AND DEVICE FOR TESTING ELECTRONIC COMPONENTS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09771391
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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ELECTRICAL CIRCUIT AND METHOD FOR TESTING A CIRCUIT COMPONENT OF THE ELECTRICAL CIRCUIT
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09771451
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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METHOD OF TESTING A MEMORY CELL HAVING A FLOATING GATE
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09773220
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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Circuit configuration for generating an output clock signal with optimized signal generation time
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09773221
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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Memory component with short access time
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09773222
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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Method and circuit configuration for read-write mode control of a synchronous memory
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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09776947
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Filing Dt:
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02/05/2001
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Publication #:
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Pub Dt:
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10/04/2001
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Title:
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METHOD FOR TESTING THE REFRESH DEVICE OF AN INFORMATION MEMORY
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09776950
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Filing Dt:
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02/05/2001
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Publication #:
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Pub Dt:
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08/23/2001
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Title:
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Integrated semiconductor memory
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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09776951
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Filing Dt:
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02/05/2001
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Publication #:
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Pub Dt:
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10/18/2001
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Title:
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METHOD AND DEVICE FOR ADAPTING/TUNING SIGNAL TRANSIT TIMES ON LINE SYSTEMS OR NETWORKS BETWEEN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09780305
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Filing Dt:
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02/09/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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INTEGRATED SEMICONDUCTOR MEMORY HAVING MEMORY CELLS WITH A FERROELECTRIC MEMORY PROPERTY
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09780324
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Filing Dt:
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02/09/2001
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Publication #:
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Pub Dt:
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10/04/2001
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Title:
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CIRCUIT CONFIGURATION FOR ADJUSTING SIGNAL DELAY TIMES
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09780326
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Filing Dt:
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02/09/2001
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Publication #:
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Pub Dt:
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09/13/2001
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Title:
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Integrated semiconductor memory with redundant units for memory cells
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09781208
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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CONFIGURATION FOR GENERATING SIGNAL IMPULSES OF DEFINED LENGTHS IN A MODULE WITH A BIST-FUNCTION
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09781675
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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METHOD OF MANUFACTURE OF A CAPACITOR WITH A DIELECTRIC ON THE BASIS OF STRONTIUM-BISMUTH-TANTALUM
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09781813
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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FUSIBLE LINK CONFIGURATION IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09784768
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Filing Dt:
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02/15/2001
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Publication #:
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Pub Dt:
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10/11/2001
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Title:
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FUSE CONFIGURATION FOR A SEMICONDUCTOR APPARATUS
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09789784
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Filing Dt:
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02/20/2001
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Publication #:
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Pub Dt:
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10/04/2001
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Title:
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DECODING APPARATUS
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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09789991
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Filing Dt:
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02/20/2001
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Publication #:
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Pub Dt:
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09/27/2001
| | | | |
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Title:
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METHOD AND APPARATUS FOR TESTING AN SDRAM MEMORY USED AS THE MAIN MEMORY IN A PERSONAL COMPUTER
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09792796
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Filing Dt:
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02/23/2001
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Publication #:
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Pub Dt:
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10/18/2001
| | | | |
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Title:
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INTEGRATED MEMORY WITH PLATE LINE SEGMENTS
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Patent #:
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Issue Dt:
|
05/07/2002
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Application #:
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09793343
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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09/06/2001
| | | | |
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Title:
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REDUNDANCY MULTIPLEXER FOR A SEMICONDUCTOR MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
|
07/06/2004
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Application #:
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09793345
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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12/27/2001
| | | | |
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Title:
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METHOD FOR FILLING DEPRESSIONS IN A SURFACE OF A SEMICONDUCTOR STRUCTURE, AND A SEMICONDUCTOR STRUCTURE FILLED IN THIS WAY
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|
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Patent #:
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Issue Dt:
|
02/08/2005
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Application #:
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09793350
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Filing Dt:
|
02/26/2001
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|
Publication #:
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Pub Dt:
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09/20/2001
| | | | |
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Title:
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METHOD OF MANUFACTURING A FERROELECTRIC CAPACITOR CONFIGURATION
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Patent #:
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Issue Dt:
|
11/13/2001
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Application #:
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09793351
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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09/13/2001
| | | | |
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Title:
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Method for fabricating a semiconductor component
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Patent #:
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|
Issue Dt:
|
02/04/2003
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Application #:
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09793353
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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09/20/2001
| | | | |
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Title:
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TEST STRUCTURE IN AN INTEGRATED SEMICONDUCTOR
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|
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Patent #:
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Issue Dt:
|
11/23/2004
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Application #:
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09796207
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
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10/18/2001
| | | | |
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Title:
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READ/WRITE AMPLIFIER HAVING VERTICAL TRANSISTORS FOR A DRAM MEMORY
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09796209
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
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08/30/2001
| | | | |
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Title:
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METHOD FOR REGENERATING SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
|
09/17/2002
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Application #:
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09799940
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Filing Dt:
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03/06/2001
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Publication #:
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Pub Dt:
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02/28/2002
| | | | |
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Title:
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READ AMPLIFIER SUBCIRCUIT FOR A DRAM MEMORY
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Patent #:
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Issue Dt:
|
09/03/2002
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Application #:
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09801715
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Filing Dt:
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03/09/2001
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Publication #:
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Pub Dt:
|
11/01/2001
| | | | |
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Title:
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INTEGRATED DRAM MEMORY CELL AND DRAM MEMORY
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|
|
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Patent #:
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|
Issue Dt:
|
09/02/2003
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Application #:
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09801963
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Filing Dt:
|
03/08/2001
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Publication #:
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Pub Dt:
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10/04/2001
| | | | |
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Title:
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METHOD FOR DETERMINING THE TEMPERATURE OF A SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP WITH TEMPERATURE MEASURING CONFIGURATION
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|
|
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Patent #:
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Issue Dt:
|
06/03/2003
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Application #:
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09805295
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Filing Dt:
|
03/13/2001
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|
Publication #:
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Pub Dt:
|
09/13/2001
| | | | |
|
Title:
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REDUNDANT MULTIPLEXER FOR A SEMICONDUCTOR MEMORY CONFIGURATION
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|
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Patent #:
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|
Issue Dt:
|
12/16/2003
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Application #:
|
09809860
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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10/18/2001
| | | | |
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Title:
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APPARATUS FOR APPLYING A SEMICONDUCTOR CHIP TO A CARRIER ELEMENT WITH A COMPENSATING LAYER
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|
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Patent #:
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Issue Dt:
|
09/03/2002
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Application #:
|
09816924
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Filing Dt:
|
03/23/2001
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|
Publication #:
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Pub Dt:
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10/25/2001
| | | | |
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Title:
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METHOD FOR CARRYING OUT A BURN-IN PROCESS FOR ELECTRICALLY STRESSING A SEMICONDUCTOR MEMORY
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|
