|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13350981
|
Filing Dt:
|
01/16/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13351012
|
Filing Dt:
|
01/16/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
TRENCH-GENERATED TRANSISTOR STRUCTURES, DEVICE STRUCTURES, AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13351041
|
Filing Dt:
|
01/16/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13351294
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13351370
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
METHOD FOR FABRICATING AIR GAP INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13351398
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
13351402
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13352131
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
PREVENTION OF DATA LOSS DUE TO ADJACENT TRACK INTERFERENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13352713
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
ANALYZING A PATTERNING PROCESS USING A MODEL OF YIELD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13352737
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
GRAPHENE DEVICES AND SEMICONDUCTOR FIELD EFFECT TRANSISTORS IN 3D HYBRID INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13352851
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13353035
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
NEAR-NEIGHBOR TRIMMING OF DUMMY FILL SHAPES WITH BUILT-IN OPTICAL PROXIMITY CORRECTIONS FOR SEMICONDUCTOR APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13353118
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13353162
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
SILICON PHOTONICS WAFER USING STANDARD SILICON-ON-INSULATOR PROCESSES THROUGH SUBSTRATE REMOVAL OR TRANSFER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13353383
|
Filing Dt:
|
01/19/2012
|
Title:
|
SELECTABLE DYNAMIC/STATIC LATCH WITH EMBEDDED LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13353708
|
Filing Dt:
|
01/19/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13353814
|
Filing Dt:
|
01/19/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
PER-RANK CHANNEL MARKING IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13353879
|
Filing Dt:
|
01/19/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
DYNAMIC GRADUATED MEMORY DEVICE PROTECTION IN REDUNDANT ARRAY OF INDEPENDENT MEMORY (RAIM) SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13353925
|
Filing Dt:
|
01/19/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13354363
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
13354371
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
METHOD OF FABRICATING DAMASCENE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13354705
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13354715
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13354717
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
ENERGY EFFICIENT AIR FLOW CONTROL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13355004
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
FUNCTIONAL TESTING OF A PROCESSOR DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13355065
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13355099
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13355691
|
Filing Dt:
|
01/23/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
EPITAXIAL REPLACEMENT OF A RAISED SOURCE/DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13355833
|
Filing Dt:
|
01/23/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13356013
|
Filing Dt:
|
01/23/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13356090
|
Filing Dt:
|
01/23/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHOD TO FORM SILICIDE CONTACT IN TRENCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13356681
|
Filing Dt:
|
01/24/2012
|
Title:
|
ANALYTIC EXPERIMENTAL ESTIMATOR FOR IMPACT OF VOLTAGE-OVERSHOOT OF VOLTAGE WAVEFORM ON DIELECTRIC FAILURE/BREAKDOWN
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13356778
|
Filing Dt:
|
01/24/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
NEGATIVE COEFFICIENT THERMAL EXPANSION ENGINEERED PARTICLES FOR COMPOSITE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13357656
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
N-TYPE CARRIER ENHANCEMENT IN SEMICONDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13357728
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ARRAY OF ALPHA PARTICLE SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13357757
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13358105
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND METHOD OF DESIGNING SEMICONDUCTOR STRUCTURE TO AVOID HIGH VOLTAGE INITIATED LATCH-UP IN LOW VOLTAGE SECTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13358172
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHOD OF MANUFACTURING SWITCHING FILTERS AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13358180
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13358963
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
3D OPTOELECTRONIC PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13359032
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
METHOD OF FORMING MIM CAPACITOR STRUCTURE IN FEOL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13359100
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
3D OPTOELECTRONIC PACKAGING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13359110
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13359177
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13359454
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13359634
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13359818
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
METHODS FOR READING A FEATURE PATTERN FROM A PACKAGED DIE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13359849
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13359858
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Mosfet Structures Having Compressively Strained Silicon Channel
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13359970
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13360055
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13360083
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360203
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360248
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360270
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360277
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13360811
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
BDD-BASED FUNCTIONAL COVERAGE ANALYSIS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13360823
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SILICON CARBON FILM STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13360877
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
TRANSMISSION ELECTRON MICROSCOPY SAMPLE ETCHING FIXTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13361004
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATES USING BANDGAP MATERIAL BETWEEN III-V CHANNEL MATERIAL AND INSULATOR LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13361050
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
FIN-TYPE FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13361051
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13361057
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13362019
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH CHANNEL REGION EDGE AND CENTER PORTIONS HAVING DIFFERENT BAND STRUCTURES FOR SUPPRESSED CORNER LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13362043
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
METHOD OF PROGRAMMING ELECTRICAL ANTIFUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13362228
|
Filing Dt:
|
01/31/2012
|
Title:
|
UNIFORM SOLDER REFLOW FIXTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13362366
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SUPERCONDUCTING QUANTUM CIRCUIT HAVING A RESONANT CAVITY THERMALIZED WITH METAL COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
13362754
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
PROBABLISTIC SUBSURFACE MODELING FOR IMPROVED DRILL CONTROL AND REAL-TIME CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13362862
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
LOW TEMPERATURE MELT-PROCESSING OF ORGANIC-INORGANIC HYBRID
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13363549
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
THERMALLY INSULATED PHASE MATERIAL CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13363603
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13363651
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Multi-Gate Field Effect Transistor with a Tapered Gate Profile
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13363944
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
RECESSED GATE CHANNEL WITH LOW VT CORNER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13363995
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13364002
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
3D INTEGRATED CIRCUITS STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13364036
|
Filing Dt:
|
02/01/2012
|
Title:
|
BULK FINFET AND SOI FINFET HYBRID TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13364153
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13364171
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
GRID-LINE-FREE CONTACT FOR A PHOTOVOLTAIC CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13364273
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
LOCAL BOTTOM GATES FOR GRAPHENE AND CARBON NANOTUBE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13364311
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13364346
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
IMPLEMENTING MULTIPLE DIFFERENT TYPES OF DIES FOR MEMORY STACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
13364494
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
TUNNEL JUNCTION VIA
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
13364564
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
METHOD AND STRUCTURE FOR GATE HEIGHT SCALING WITH HIGH-K/METAL GATE TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13364569
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
DESIGN STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13364607
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
MULTI-WAFER 3D CAM CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13364663
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13364753
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13364759
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
METHOD AND STRUCTURE FOR ULTRA-HIGH DENSITY, HIGH DATA RATE FERROELECTRIC STORAGE DISK TECHNOLOGY USING STABILIZATION BY A SURFACE CONDUCTING LAYER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13364850
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13364976
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13365030
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT CONTACT STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13365370
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
VALIDATING INTERCONNECTIONS BETWEEN LOGIC BLOCKS IN A CIRCUIT DESCRIPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13365408
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
HIGH DENSITY DATA STORAGE MEDIUM, METHOD AND DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13365505
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13365577
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
NANOFLUIDIC FIELD EFFECT TRANSISTOR BASED ON SURFACE CHARGE MODULATED NANOCHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
13365764
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13365920
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
HYBRID METROLOGY FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13365961
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
ESTIMATING POWER CONSUMPTION OF AN ELECTRONIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13365989
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
GATE CONFIGURATION DETERMINATION AND SELECTION FROM STANDARD CELL LIBRARY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13366804
|
Filing Dt:
|
02/06/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
WORD-LINE LEVEL SHIFT CIRCUIT
|
|