|
|
Patent #:
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|
Issue Dt:
|
10/14/2014
|
Application #:
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13411068
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Filing Dt:
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03/02/2012
|
Publication #:
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|
Pub Dt:
|
09/05/2013
| | | | |
Title:
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DEFECT DETECTION ON CHARACTERISTICALLY CAPACITIVE CIRCUIT NODES
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|
Patent #:
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|
Issue Dt:
|
06/25/2013
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Application #:
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13411610
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Filing Dt:
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03/04/2012
|
Publication #:
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|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
RESISTOR WITH IMPROVED SWITCHABLE RESISTANCE AND NON-VOLATILE MEMORY DEVICE
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|
Patent #:
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|
Issue Dt:
|
06/04/2013
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Application #:
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13412725
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Filing Dt:
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03/06/2012
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Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
METHOD FOR COMPENSATING FOR VARIATIONS IN STRUCTURES OF AN INTEGRATED CIRCUIT
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13413192
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Filing Dt:
|
03/06/2012
|
Publication #:
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|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
APPARATUS AND METHOD FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE
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|
Patent #:
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|
Issue Dt:
|
07/09/2013
|
Application #:
|
13413288
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Filing Dt:
|
03/06/2012
|
Title:
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DECOMPOSING LAYOUT FOR TRIPLE PATTERNING LITHOGRAPHY
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|
Patent #:
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|
Issue Dt:
|
06/25/2013
|
Application #:
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13413759
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Filing Dt:
|
03/07/2012
|
Publication #:
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|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
PHYSICAL DESIGN SYSTEM AND METHOD
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|
|
Patent #:
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|
Issue Dt:
|
10/16/2012
|
Application #:
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13413825
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Filing Dt:
|
03/07/2012
|
Publication #:
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|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
MULTI-OUTPUT PLL OUTPUT SHIFT
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|
|
Patent #:
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|
Issue Dt:
|
03/18/2014
|
Application #:
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13414133
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Filing Dt:
|
03/07/2012
|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM
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|
Patent #:
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|
Issue Dt:
|
09/16/2014
|
Application #:
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13414742
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Filing Dt:
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03/08/2012
|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
Fuse and Integrated Conductor
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13414743
|
Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
FLEXIBLE FILM CARRIER TO INCREASE INTERCONNECT DENSITY OF MODULES AND METHODS THEREOF
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|
Patent #:
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|
Issue Dt:
|
01/14/2014
|
Application #:
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13414877
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Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
STRUCTURES AND METHODS FOR DETECTING SOLDER WETTING OF PEDESTAL SIDEWALLS
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|
Patent #:
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|
Issue Dt:
|
04/01/2014
|
Application #:
|
13414954
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Filing Dt:
|
03/08/2012
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
ASYMMETRIC COMPLEMENTARY DIPOLE ILLUMINATOR
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|
Patent #:
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|
Issue Dt:
|
09/03/2013
|
Application #:
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13414976
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Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTURES THEREOF
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|
Patent #:
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|
Issue Dt:
|
06/17/2014
|
Application #:
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13415012
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Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
DETERMINING CELL-STATE IN PHASE-CHANGE MEMORY
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13415061
|
Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
PROGRAMMING OF PHASE-CHANGE MEMORY CELLS
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|
Patent #:
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|
Issue Dt:
|
05/27/2014
|
Application #:
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13415106
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Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
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ASYMMETRIC COMPLEMENTARY DIPOLE ILLUMINATOR
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13415127
|
Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
CELL-STATE MEASUREMENT IN RESISTIVE MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
07/08/2014
|
Application #:
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13415159
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Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
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|
|
Patent #:
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|
Issue Dt:
|
07/01/2014
|
Application #:
|
13415372
|
Filing Dt:
|
03/08/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
METAL DENSITY AWARE SIGNAL ROUTING
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|
|
Patent #:
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|
Issue Dt:
|
12/23/2014
|
Application #:
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13415532
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Filing Dt:
|
03/08/2012
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
Title:
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METAL DENSITY AWARE SIGNAL ROUTING
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|
|
Patent #:
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|
Issue Dt:
|
10/01/2013
|
Application #:
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13415902
|
Filing Dt:
|
03/09/2012
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
SELF-ALIGNED POLYMER PASSIVATION/ALUMINUM PAD
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|
|
Patent #:
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|
Issue Dt:
|
06/25/2013
|
Application #:
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13415924
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Filing Dt:
|
03/09/2012
|
Publication #:
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|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
METHOD AND SYSTEM FOR SCALABLE REDUCTION IN REGISTERS WITH SAT-BASED RESUBSTITUTION
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|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
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13415946
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Filing Dt:
|
03/09/2012
|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
HYBRID IO CELL FOR WIREBOND AND C4 APPLICATIONS
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|
Patent #:
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|
Issue Dt:
|
05/13/2014
|
Application #:
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13416015
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Filing Dt:
|
03/09/2012
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
OPTIMIZING TIMING CRITICAL PATHS BY MODULATING SYSTEMIC PROCESS VARIATION
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13416324
|
Filing Dt:
|
03/09/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
COMPLIANT VAPOR CHAMBER CHIP PACKAGING
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|
|
Patent #:
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|
Issue Dt:
|
05/13/2014
|
Application #:
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13416354
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Filing Dt:
|
03/09/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
EFFICIENCY IN ANTIREFLECTIVE COATING LAYERS FOR SOLAR CELLS
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|
|
Patent #:
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|
Issue Dt:
|
08/13/2013
|
Application #:
|
13416588
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Filing Dt:
|
03/09/2012
|
Title:
|
PERFORMANCE DRIVEN LAYOUT OPTIMIZATION USING MORPHING OF A BASIS SET OF REPRESENTATIVE LAYOUTS
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13417023
|
Filing Dt:
|
03/09/2012
|
Publication #:
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|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
VIA STUB ELIMINATION
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|
|
Patent #:
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|
Issue Dt:
|
03/12/2013
|
Application #:
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13417829
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Filing Dt:
|
03/12/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
NANOMESH SRAM CELL
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|
|
Patent #:
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|
Issue Dt:
|
05/06/2014
|
Application #:
|
13417879
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Filing Dt:
|
03/12/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
Continuously Referencing Signals Over Multiple Layers in Laminate Packages
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|
Patent #:
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|
Issue Dt:
|
01/14/2014
|
Application #:
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13417900
|
Filing Dt:
|
03/12/2012
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE
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|
Patent #:
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|
Issue Dt:
|
06/10/2014
|
Application #:
|
13418261
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Filing Dt:
|
03/12/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A COPPER PLUG
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|
Patent #:
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|
Issue Dt:
|
10/29/2013
|
Application #:
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13418421
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Filing Dt:
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03/13/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
MULTIPLE EXPOSURE PHOTOLITHOGRAPHY METHODS
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|
Patent #:
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|
Issue Dt:
|
09/16/2014
|
Application #:
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13418423
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Filing Dt:
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03/13/2012
|
Publication #:
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|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
ENCODING A DATA WORD FOR WRITING THE ENCODED DATA WORD IN A MULTI-LEVEL SOLID STATE MEMORY
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13418438
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Filing Dt:
|
03/13/2012
|
Publication #:
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|
Pub Dt:
|
09/19/2013
| | | | |
Title:
|
GALLIUM NITRIDE SUPERJUNCTION DEVICES
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|
Patent #:
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|
Issue Dt:
|
01/13/2015
|
Application #:
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13418454
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Filing Dt:
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03/13/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES
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|
Patent #:
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|
Issue Dt:
|
06/23/2015
|
Application #:
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13418476
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Filing Dt:
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03/13/2012
|
Publication #:
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|
Pub Dt:
|
09/19/2013
| | | | |
Title:
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BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME
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|
Patent #:
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|
Issue Dt:
|
10/22/2013
|
Application #:
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13418659
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Filing Dt:
|
03/13/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
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METHOD OF MANUFACTURING AN INTERCONNECT STRUCTURE AND DESIGN STRUCTURE THEREOF
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|
Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
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13418716
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Filing Dt:
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03/13/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
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HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION
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Patent #:
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|
Issue Dt:
|
06/11/2013
|
Application #:
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13418818
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Filing Dt:
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03/13/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
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STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME
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|
|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13418862
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Filing Dt:
|
03/13/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
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SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13418921
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Filing Dt:
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03/13/2012
|
Publication #:
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|
Pub Dt:
|
09/19/2013
| | | | |
Title:
|
MONOLITHIC HIGH VOLTAGE MULTIPLIER HAVING HIGH VOLTAGE SEMICONDUCTOR DIODES AND HIGH-K CAPACITORS
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Patent #:
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|
Issue Dt:
|
04/09/2013
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Application #:
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13419522
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Filing Dt:
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03/14/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13419537
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Filing Dt:
|
03/14/2012
|
Publication #:
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|
Pub Dt:
|
08/22/2013
| | | | |
Title:
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AUTOMATED, THREE DIMENSIONAL MAPPABLE ENVIRONMENTAL SAMPLING SYSTEM AND METHODS OF USE
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13419624
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Filing Dt:
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03/14/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES
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Patent #:
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|
Issue Dt:
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03/17/2015
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Application #:
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13419877
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Filing Dt:
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03/14/2012
|
Publication #:
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|
Pub Dt:
|
09/19/2013
| | | | |
Title:
|
PROGRAMMABLE FUSE STRUCTURE AND METHODS OF FORMING
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|
Patent #:
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|
Issue Dt:
|
05/20/2014
|
Application #:
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13419927
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Filing Dt:
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03/14/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION
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|
Patent #:
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|
Issue Dt:
|
03/25/2014
|
Application #:
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13420637
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Filing Dt:
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03/15/2012
|
Publication #:
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|
Pub Dt:
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09/19/2013
| | | | |
Title:
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FINE TUNING HIGHLY RESISTIVE SUBSTRATE RESISTIVITY AND STRUCTURES THEREOF
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Patent #:
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|
Issue Dt:
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01/14/2014
|
Application #:
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13420724
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Filing Dt:
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03/15/2012
|
Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
ELECTRICALLY PROGRAMMABLE FUSE USING ANISOMETRIC CONTACTS AND FABRICATION METHOD
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|
Patent #:
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|
Issue Dt:
|
11/22/2016
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Application #:
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13420728
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Filing Dt:
|
03/15/2012
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Publication #:
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Pub Dt:
|
07/12/2012
| | | | |
Title:
|
METHOD OF FORMING AN INTERCONNECT STRUCTURE
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Patent #:
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|
Issue Dt:
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01/14/2014
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Application #:
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13420730
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Filing Dt:
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03/15/2012
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Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
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ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME
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Patent #:
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|
Issue Dt:
|
12/03/2013
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Application #:
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13420763
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Filing Dt:
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03/15/2012
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Publication #:
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|
Pub Dt:
|
07/05/2012
| | | | |
Title:
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FIELD EFFECT TRANSISTOR (FET) AND METHOD OF FORMING THE FET WITHOUT DAMAGING THE WAFER SURFACE
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13421276
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Filing Dt:
|
03/15/2012
|
Publication #:
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Pub Dt:
|
09/19/2013
| | | | |
Title:
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USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS
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Patent #:
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|
Issue Dt:
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07/16/2013
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Application #:
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13421400
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Filing Dt:
|
03/15/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
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METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE
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Patent #:
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|
Issue Dt:
|
03/18/2014
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Application #:
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13422297
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Filing Dt:
|
03/16/2012
|
Publication #:
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|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS
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|
|
Patent #:
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|
Issue Dt:
|
12/10/2013
|
Application #:
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13422390
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Filing Dt:
|
03/16/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
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SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13422566
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Filing Dt:
|
03/16/2012
|
Publication #:
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|
Pub Dt:
|
08/02/2012
| | | | |
Title:
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UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS
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Patent #:
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|
Issue Dt:
|
08/13/2013
|
Application #:
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13422637
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Filing Dt:
|
03/16/2012
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
ORDERING OF STATISTICAL CORRELATED QUANTITIES
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13423624
|
Filing Dt:
|
03/19/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits
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|
|
Patent #:
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|
Issue Dt:
|
08/13/2013
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Application #:
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13423659
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Filing Dt:
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03/19/2012
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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Structure and Apparatus for Cooling Integrated Circuits Using Copper Microchannels
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Patent #:
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Issue Dt:
|
12/10/2013
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Application #:
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13423716
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Filing Dt:
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03/19/2012
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Publication #:
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Pub Dt:
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10/04/2012
| | | | |
Title:
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STRESSED SOURCE/DRAIN CMOS AND METHOD FOR FORMING SAME
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Patent #:
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Issue Dt:
|
01/14/2014
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Application #:
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13423772
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Filing Dt:
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03/19/2012
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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APPARATUS AND METHODS FOR PACKAGING INTEGRATED CIRCUIT CHIPS WITH ANTENNAS FORMED FROM PACKAGE LEAD WIRES
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Patent #:
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Issue Dt:
|
02/18/2014
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Application #:
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13423838
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Filing Dt:
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03/19/2012
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Publication #:
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Pub Dt:
|
08/16/2012
| | | | |
Title:
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ORGANIC GRADED SPIN ON BARC COMPOSITIONS FOR HIGH NA LITHOGRAPHY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13424319
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Filing Dt:
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03/19/2012
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Publication #:
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Pub Dt:
|
09/19/2013
| | | | |
Title:
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CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD
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Patent #:
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|
Issue Dt:
|
03/04/2014
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Application #:
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13424447
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Filing Dt:
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03/20/2012
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Publication #:
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Pub Dt:
|
09/26/2013
| | | | |
Title:
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Structure and method to improve etsoi mosfets with back gate
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|
Patent #:
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|
Issue Dt:
|
11/25/2014
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Application #:
|
13424613
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Filing Dt:
|
03/20/2012
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Publication #:
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Pub Dt:
|
07/12/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING
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|
Patent #:
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|
Issue Dt:
|
11/26/2013
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Application #:
|
13424787
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Filing Dt:
|
03/20/2012
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Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
Title:
|
SELECTIVELY RAISED SOURCE/DRAIN TRANSISTOR
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|
Patent #:
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|
Issue Dt:
|
07/23/2013
|
Application #:
|
13424816
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Filing Dt:
|
03/20/2012
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Title:
|
LITHOGRAPHIC ERROR REDUCTION BY PATTERN MATCHING
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|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
|
13425470
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Filing Dt:
|
03/21/2012
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Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
Title:
|
VACUUM TRAP
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|
Patent #:
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|
Issue Dt:
|
09/10/2013
|
Application #:
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13425654
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Filing Dt:
|
03/21/2012
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Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
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REPLACEMENT SPACER FOR TUNNEL FETS
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|
Patent #:
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|
Issue Dt:
|
10/15/2013
|
Application #:
|
13425681
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Filing Dt:
|
03/21/2012
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Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
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BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
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|
Patent #:
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|
Issue Dt:
|
11/05/2013
|
Application #:
|
13426776
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Filing Dt:
|
03/22/2012
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
Title:
|
INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY
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|
Patent #:
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|
Issue Dt:
|
09/30/2014
|
Application #:
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13426845
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Filing Dt:
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03/22/2012
|
Publication #:
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|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
METHOD FOR FORMING A SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION
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|
Patent #:
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Issue Dt:
|
07/29/2014
|
Application #:
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13426892
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Filing Dt:
|
03/22/2012
|
Publication #:
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|
Pub Dt:
|
03/28/2013
| | | | |
Title:
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REDUCING IMPEDANCE DISCONTINUITY IN PACKAGES
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Patent #:
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Issue Dt:
|
02/18/2014
|
Application #:
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13426966
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Filing Dt:
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03/22/2012
|
Publication #:
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|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SELF ALIGNED IMPACT-IONIZATION MOS (I-MOS) DEVICE AND METHODS OF MANUFACTURE
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|
Patent #:
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Issue Dt:
|
05/13/2014
|
Application #:
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13427162
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Filing Dt:
|
03/22/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
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PROGRAMMABLE SEMICONDUCTOR DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
08/23/2016
|
Application #:
|
13427216
|
Filing Dt:
|
03/22/2012
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
|
07/01/2014
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Application #:
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13427237
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Filing Dt:
|
03/22/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
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REPLACEMENT GATE CMOS
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13427257
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Filing Dt:
|
03/22/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
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METHOD FOR FORMING A FIELD EFFECT DEVICE INCLUDING AN ANNULAR GATE ELECTRODE
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|
Patent #:
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Issue Dt:
|
12/17/2013
|
Application #:
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13427486
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Filing Dt:
|
03/22/2012
|
Publication #:
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Pub Dt:
|
07/12/2012
| | | | |
Title:
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METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN
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|
Patent #:
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|
Issue Dt:
|
09/17/2013
|
Application #:
|
13427516
|
Filing Dt:
|
03/22/2012
|
Publication #:
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|
Pub Dt:
|
07/19/2012
| | | | |
Title:
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METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13427940
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Filing Dt:
|
03/23/2012
|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
Title:
|
ELECTROMIGRATION-RESISTANT LEAD-FREE SOLDER INTERCONNECT STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
10/08/2013
|
Application #:
|
13427963
|
Filing Dt:
|
03/23/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
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STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL
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|
Patent #:
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|
Issue Dt:
|
11/19/2013
|
Application #:
|
13428004
|
Filing Dt:
|
03/23/2012
|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
Title:
|
CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE
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|
|
Patent #:
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|
Issue Dt:
|
03/17/2015
|
Application #:
|
13428184
|
Filing Dt:
|
03/23/2012
|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
Title:
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Techniques to Form Uniform and Stable Silicide
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|
|
Patent #:
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|
Issue Dt:
|
10/08/2013
|
Application #:
|
13428205
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Filing Dt:
|
03/23/2012
|
Publication #:
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|
Pub Dt:
|
07/19/2012
| | | | |
Title:
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DATA CONSISTENCY IN LONG-RUNNING PROCESSES
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|
Patent #:
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Issue Dt:
|
09/17/2013
|
Application #:
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13428277
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Filing Dt:
|
03/23/2012
|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
Title:
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FLEXIBLE FIBER TO WAFER INTERFACE
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13428571
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Filing Dt:
|
03/23/2012
|
Publication #:
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|
Pub Dt:
|
09/26/2013
| | | | |
Title:
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ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS
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|
Patent #:
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|
Issue Dt:
|
04/29/2014
|
Application #:
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13429466
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Filing Dt:
|
03/26/2012
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
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CIRCUIT DESIGN APPROXIMATION
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13429930
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Filing Dt:
|
03/26/2012
|
Publication #:
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|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE
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|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13429981
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Filing Dt:
|
03/26/2012
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Publication #:
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Pub Dt:
|
10/04/2012
| | | | |
Title:
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THREAD SERIALIZATION AND DISABLEMENT TOOL
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|
|
Patent #:
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|
Issue Dt:
|
05/06/2014
|
Application #:
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13430018
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Filing Dt:
|
03/26/2012
|
Publication #:
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|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
06/16/2015
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Application #:
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13430028
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Filing Dt:
|
03/26/2012
|
Publication #:
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|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
COMBINED MATRIX-VECTOR AND MATRIX TRANSPOSE VECTOR MULTIPLY FOR A BLOCK-SPARSE MATRIX
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|
Patent #:
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Issue Dt:
|
08/05/2014
|
Application #:
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13430041
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Filing Dt:
|
03/26/2012
|
Publication #:
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|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13430049
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Filing Dt:
|
03/26/2012
|
Publication #:
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|
Pub Dt:
|
07/19/2012
| | | | |
Title:
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ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL
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|
Patent #:
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|
Issue Dt:
|
06/17/2014
|
Application #:
|
13430067
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Filing Dt:
|
03/26/2012
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
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ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL
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|
Patent #:
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|
Issue Dt:
|
07/16/2013
|
Application #:
|
13430177
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Filing Dt:
|
03/26/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL
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|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13430179
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Filing Dt:
|
03/26/2012
|
Publication #:
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|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13430755
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
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Replacement Gate With Reduced Gate Leakage Current
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13430864
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
Network Based Energy Preference Service for Managing Electric Vehicle Charging Preferences
|
|