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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 113 of 148
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Patent #:	8423847	Issue Dt:	04/16/2013	Application #:	13469604	Filing Dt:	05/11/2012
Publication #:	US20120221910	Pub Dt:	08/30/2012
Title:	MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)

Patent #:	8901619	Issue Dt:	12/02/2014	Application #:	13470393	Filing Dt:	05/14/2012
Publication #:	US20120223386	Pub Dt:	09/06/2012
Title:	Asymmetric FinFET devices

Patent #:	9059321	Issue Dt:	06/16/2015	Application #:	13470620	Filing Dt:	05/14/2012
Publication #:	US20130302949	Pub Dt:	11/14/2013
Title:	BURIED-CHANNEL FIELD-EFFECT TRANSISTORS

Patent #:	9291665	Issue Dt:	03/22/2016	Application #:	13470645	Filing Dt:	05/14/2012
Publication #:	US20130300451	Pub Dt:	11/14/2013
Title:	EVALUATING TRANSISTORS WITH E-BEAM INSPECTION

Patent #:	8586455	Issue Dt:	11/19/2013	Application #:	13471487	Filing Dt:	05/15/2012
Publication #:	US20130309837	Pub Dt:	11/21/2013
Title:	PREVENTING SHORTING OF ADJACENT DEVICES

Patent #:	8601418	Issue Dt:	12/03/2013	Application #:	13471536	Filing Dt:	05/15/2012
Publication #:	US20130311962	Pub Dt:	11/21/2013
Title:	INSTRUCTION-BY-INSTRUCTION CHECKING ON ACCELERATION PLATFORMS

Patent #:	8756554	Issue Dt:	06/17/2014	Application #:	13471623	Filing Dt:	05/15/2012
Publication #:	US20130067425	Pub Dt:	03/14/2013
Title:	IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN

Patent #:	8635575	Issue Dt:	01/21/2014	Application #:	13471627	Filing Dt:	05/15/2012
Publication #:	US20120227025	Pub Dt:	09/06/2012
Title:	SYSTEM AND METHOD TO IMPROVE CHIP YIELD, RELIABILITY AND PERFORMANCE

Patent #:	8987084	Issue Dt:	03/24/2015	Application #:	13471711	Filing Dt:	05/15/2012
Publication #:	US20120225527	Pub Dt:	09/06/2012
Title:	HIGH DENSITY LOW POWER NANOWIRE PHASE CHANGE MATERIAL MEMORY DEVICE

Patent #:	8679968	Issue Dt:	03/25/2014	Application #:	13471846	Filing Dt:	05/15/2012
Publication #:	US20130307087	Pub Dt:	11/21/2013
Title:	METHOD FOR FORMING A SELF-ALIGNED CONTACT OPENING BY A LATERAL ETCH

Patent #:	8629511	Issue Dt:	01/14/2014	Application #:	13471852	Filing Dt:	05/15/2012
Publication #:	US20130307086	Pub Dt:	11/21/2013
Title:	MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES

Patent #:	8703553	Issue Dt:	04/22/2014	Application #:	13471955	Filing Dt:	05/15/2012
Publication #:	US20130309832	Pub Dt:	11/21/2013
Title:	MOS CAPACITORS WITH A FINFET PROCESS

Patent #:	8525293	Issue Dt:	09/03/2013	Application #:	13472044	Filing Dt:	05/15/2012
Publication #:	US20120319233	Pub Dt:	12/20/2012
Title:	BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION

Patent #:	8658444	Issue Dt:	02/25/2014	Application #:	13472584	Filing Dt:	05/16/2012
Publication #:	US20130309791	Pub Dt:	11/21/2013
Title:	SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR

Patent #:	8816436	Issue Dt:	08/26/2014	Application #:	13472605	Filing Dt:	05/16/2012
Publication #:	US20130307076	Pub Dt:	11/21/2013
Title:	METHOD AND STRUCTURE FOR FORMING FIN RESISTORS

Patent #:	8923666	Issue Dt:	12/30/2014	Application #:	13472674	Filing Dt:	05/16/2012
Publication #:	US20130306928	Pub Dt:	11/21/2013
Title:	ELECTRICALLY CONTROLLED OPTICAL FUSE AND METHOD OF FABRICATION

Patent #:	8530974	Issue Dt:	09/10/2013	Application #:	13472680	Filing Dt:	05/16/2012
Publication #:	US20130062704	Pub Dt:	03/14/2013
Title:	CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES

Patent #:	8956938	Issue Dt:	02/17/2015	Application #:	13472747	Filing Dt:	05/16/2012
Publication #:	US20130307074	Pub Dt:	11/21/2013
Title:	Epitaxial Semiconductor Resistor With Semiconductor Structures On Same Substrate

Patent #:	8464199	Issue Dt:	06/11/2013	Application #:	13472814	Filing Dt:	05/16/2012
Title:	CIRCUIT DESIGN USING DESIGN VARIABLE FUNCTION SLOPE SENSITIVITY

Patent #:	NONE	Issue Dt:		Application #:	13473789	Filing Dt:	05/17/2012
Publication #:	US20120228775	Pub Dt:	09/13/2012
Title:	AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING

Patent #:	8652941	Issue Dt:	02/18/2014	Application #:	13474090	Filing Dt:	05/17/2012
Publication #:	US20130149841	Pub Dt:	06/13/2013
Title:	WAFER DICING EMPLOYING EDGE REGION UNDERFILL REMOVAL

Patent #:	8450205	Issue Dt:	05/28/2013	Application #:	13474244	Filing Dt:	05/17/2012
Publication #:	US20120225549	Pub Dt:	09/06/2012
Title:	REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE

Patent #:	9293593	Issue Dt:	03/22/2016	Application #:	13474257	Filing Dt:	05/17/2012
Publication #:	US20120228639	Pub Dt:	09/13/2012
Title:	SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE

Patent #:	8645455	Issue Dt:	02/04/2014	Application #:	13474304	Filing Dt:	05/17/2012
Publication #:	US20120232864	Pub Dt:	09/13/2012
Title:	ANALYZING ANTICIPATED VALUE AND EFFORT IN USING CLOUD COMPUTING TO PROCESS A SPECIFIED WORKLOAD

Patent #:	8415248	Issue Dt:	04/09/2013	Application #:	13474349	Filing Dt:	05/17/2012
Publication #:	US20120231622	Pub Dt:	09/13/2012
Title:	SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME

Patent #:	8563446	Issue Dt:	10/22/2013	Application #:	13474790	Filing Dt:	05/18/2012
Publication #:	US20120228736	Pub Dt:	09/13/2012
Title:	TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE

Patent #:	8610276	Issue Dt:	12/17/2013	Application #:	13474916	Filing Dt:	05/18/2012
Publication #:	US20120228770	Pub Dt:	09/13/2012
Title:	METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE

Patent #:	NONE	Issue Dt:		Application #:	13474944	Filing Dt:	05/18/2012
Publication #:	US20130307153	Pub Dt:	11/21/2013
Title:	INTERCONNECT WITH TITANIUM-OXIDE DIFFUSION BARRIER

Patent #:	8928096	Issue Dt:	01/06/2015	Application #:	13474949	Filing Dt:	05/18/2012
Publication #:	US20130299906	Pub Dt:	11/14/2013
Title:	BURIED-CHANNEL FIELD-EFFECT TRANSISTORS

Patent #:	8557657	Issue Dt:	10/15/2013	Application #:	13475485	Filing Dt:	05/18/2012
Title:	RETROGRADE SUBSTRATE FOR DEEP TRENCH CAPACITORS

Patent #:	8642454	Issue Dt:	02/04/2014	Application #:	13475503	Filing Dt:	05/18/2012
Publication #:	US20120295421	Pub Dt:	11/22/2012
Title:	LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH

Patent #:	8485812	Issue Dt:	07/16/2013	Application #:	13475967	Filing Dt:	05/19/2012
Publication #:	US20120276234	Pub Dt:	11/01/2012
Title:	SPIN-MOUNTED FABRICATION OF INJECTION MOLDED MICRO-OPTICS

Patent #:	9214435	Issue Dt:	12/15/2015	Application #:	13476056	Filing Dt:	05/21/2012
Publication #:	US20130307160	Pub Dt:	11/21/2013
Title:	VIA STRUCTURE FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION

Patent #:	NONE	Issue Dt:		Application #:	13476382	Filing Dt:	05/21/2012
Publication #:	US20120292706	Pub Dt:	11/22/2012
Title:	SCHEME TO ENABLE ROBUST INTEGRATION OF BAND EDGE DEVICES AND ALTERNATIVE CHANNELS

Patent #:	8581320	Issue Dt:	11/12/2013	Application #:	13476567	Filing Dt:	05/21/2012
Publication #:	US20130307043	Pub Dt:	11/21/2013
Title:	MOS CAPACITORS WITH A FINFET PROCESS

Patent #:	9064628	Issue Dt:	06/23/2015	Application #:	13477978	Filing Dt:	05/22/2012
Publication #:	US20130314192	Pub Dt:	11/28/2013
Title:	INDUCTOR WITH STACKED CONDUCTORS

Patent #:	9048108	Issue Dt:	06/02/2015	Application #:	13478080	Filing Dt:	05/22/2012
Publication #:	US20130313651	Pub Dt:	11/28/2013
Title:	INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES

Patent #:	8448119	Issue Dt:	05/21/2013	Application #:	13478127	Filing Dt:	05/23/2012
Title:	METHOD AND SYSTEM FOR DESIGN AND MODELING OF VERTICAL INTERCONNECTS FOR 3DI APPLICATIONS

Patent #:	9041116	Issue Dt:	05/26/2015	Application #:	13478154	Filing Dt:	05/23/2012
Publication #:	US20130313643	Pub Dt:	11/28/2013
Title:	STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETS)

Patent #:	8793630	Issue Dt:	07/29/2014	Application #:	13478272	Filing Dt:	05/23/2012
Publication #:	US20120304136	Pub Dt:	11/29/2012
Title:	Clock Tree Planning for an ASIC

Patent #:	8658486	Issue Dt:	02/25/2014	Application #:	13478411	Filing Dt:	05/23/2012
Publication #:	US20130313647	Pub Dt:	11/28/2013
Title:	FORMING FACET-LESS EPITAXY WITH A CUT MASK

Patent #:	NONE	Issue Dt:		Application #:	13478749	Filing Dt:	05/23/2012
Publication #:	US20130316538	Pub Dt:	11/28/2013
Title:	SURFACE MORPHOLOGY GENERATION AND TRANSFER BY SPALLING

Patent #:	8737121	Issue Dt:	05/27/2014	Application #:	13478932	Filing Dt:	05/23/2012
Publication #:	US20130314983	Pub Dt:	11/28/2013
Title:	DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY

Patent #:	NONE	Issue Dt:		Application #:	13478976	Filing Dt:	05/23/2012
Publication #:	US20130316513	Pub Dt:	11/28/2013
Title:	FIN ISOLATION FOR MULTIGATE TRANSISTORS

Patent #:	8649239	Issue Dt:	02/11/2014	Application #:	13479448	Filing Dt:	05/24/2012
Publication #:	US20130315022	Pub Dt:	11/28/2013
Title:	MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIGNAL BUFFERING FOR IMPROVED PERFORMANCE

Patent #:	NONE	Issue Dt:		Application #:	13479871	Filing Dt:	05/24/2012
Publication #:	US20130313683	Pub Dt:	11/28/2013
Title:	SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES

Patent #:	9070686	Issue Dt:	06/30/2015	Application #:	13479946	Filing Dt:	05/24/2012
Publication #:	US20120306017	Pub Dt:	12/06/2012
Title:	WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS

Patent #:	8450184	Issue Dt:	05/28/2013	Application #:	13480329	Filing Dt:	05/24/2012
Publication #:	US20120282782	Pub Dt:	11/08/2012
Title:	THIN SUBSTRATE FABRICATION USING STRESS-INDUCED SPALLING

Patent #:	8519761	Issue Dt:	08/27/2013	Application #:	13480573	Filing Dt:	05/25/2012
Title:	CLOSED-LOOP SLEW-RATE CONTROL FOR PHASE INTERPOLATOR OPTIMIZATION

Patent #:	8673791	Issue Dt:	03/18/2014	Application #:	13480831	Filing Dt:	05/25/2012
Publication #:	US20130316543	Pub Dt:	11/28/2013
Title:	METHOD AND APPARATUS FOR SUBSTRATE-MASK ALIGNMENT

Patent #:	8486797	Issue Dt:	07/16/2013	Application #:	13481048	Filing Dt:	05/25/2012
Title:	BIPOLAR JUNCTION TRANSISTOR WITH EPITAXIAL CONTACTS

Patent #:	8709957	Issue Dt:	04/29/2014	Application #:	13481062	Filing Dt:	05/25/2012
Publication #:	US20130316542	Pub Dt:	11/28/2013
Title:	SPALLING UTILIZING STRESSOR LAYER PORTIONS

Patent #:	9384835	Issue Dt:	07/05/2016	Application #:	13482166	Filing Dt:	05/29/2012
Publication #:	US20130326111	Pub Dt:	12/05/2013
Title:	CONTENT ADDRESSABLE MEMORY EARLY-PREDICT LATE-CORRECT SINGLE ENDED SENSING

Patent #:	8816333	Issue Dt:	08/26/2014	Application #:	13482262	Filing Dt:	05/29/2012
Publication #:	US20120235119	Pub Dt:	09/20/2012
Title:	METHOD TO IMPROVE NUCLEATION OF MATERIALS ON GRAPHENE AND CARBON NANOTUBES

Patent #:	9054109	Issue Dt:	06/09/2015	Application #:	13482352	Filing Dt:	05/29/2012
Publication #:	US20130320544	Pub Dt:	12/05/2013
Title:	CORROSION/ETCHING PROTECTION IN INTEGRATION CIRCUIT FABRICATIONS

Patent #:	8987130	Issue Dt:	03/24/2015	Application #:	13482414	Filing Dt:	05/29/2012
Publication #:	US20130320529	Pub Dt:	12/05/2013
Title:	REACTIVE BONDING OF A FLIP CHIP PACKAGE

Patent #:	9057915	Issue Dt:	06/16/2015	Application #:	13482438	Filing Dt:	05/29/2012
Publication #:	US20130321753	Pub Dt:	12/05/2013
Title:	LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME

Patent #:	8713485	Issue Dt:	04/29/2014	Application #:	13482624	Filing Dt:	05/29/2012
Publication #:	US20130326445	Pub Dt:	12/05/2013
Title:	Categorization of Design Rule Errors

Patent #:	9831122	Issue Dt:	11/28/2017	Application #:	13482864	Filing Dt:	05/29/2012
Publication #:	US20130320536	Pub Dt:	12/05/2013
Title:	INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE

Patent #:	9024355	Issue Dt:	05/05/2015	Application #:	13483200	Filing Dt:	05/30/2012
Publication #:	US20130320399	Pub Dt:	12/05/2013
Title:	EMBEDDED PLANAR SOURCE/DRAIN STRESSORS FOR A FINFET INCLUDING A PLURALITY OF FINS

Patent #:	9059245	Issue Dt:	06/16/2015	Application #:	13483781	Filing Dt:	05/30/2012
Publication #:	US20130320483	Pub Dt:	12/05/2013
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES

Patent #:	8589855	Issue Dt:	11/19/2013	Application #:	13484111	Filing Dt:	05/30/2012
Publication #:	US20130326441	Pub Dt:	12/05/2013
Title:	MACHINE-LEARNING BASED DATAPATH EXTRACTION

Patent #:	8543960	Issue Dt:	09/24/2013	Application #:	13484451	Filing Dt:	05/31/2012
Title:	POWER AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT BY VOLTAGE MODIFICATION ACROSS VARIOUS RANGES OF TEMPERATURES

Patent #:	NONE	Issue Dt:		Application #:	13484657	Filing Dt:	05/31/2012
Publication #:	US20130320422	Pub Dt:	12/05/2013
Title:	FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM

Patent #:	9385131	Issue Dt:	07/05/2016	Application #:	13484739	Filing Dt:	05/31/2012
Publication #:	US20130320423	Pub Dt:	12/05/2013
Title:	WRAP-AROUND FIN FOR CONTACTING A CAPACITOR STRAP OF A DRAM

Patent #:	8473879	Issue Dt:	06/25/2013	Application #:	13484868	Filing Dt:	05/31/2012
Publication #:	US20120293197	Pub Dt:	11/22/2012
Title:	ON-CHIP LEAKAGE CURRENT MODELING AND MEASUREMENT CIRCUIT

Patent #:	8811060	Issue Dt:	08/19/2014	Application #:	13485748	Filing Dt:	05/31/2012
Publication #:	US20130322153	Pub Dt:	12/05/2013
Title:	NON-VOLATILE MEMORY CROSSPOINT REPAIR

Patent #:	9524363	Issue Dt:	12/20/2016	Application #:	13485828	Filing Dt:	05/31/2012
Publication #:	US20130326455	Pub Dt:	12/05/2013
Title:	ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION

Patent #:	8849440	Issue Dt:	09/30/2014	Application #:	13485862	Filing Dt:	05/31/2012
Publication #:	US20130325156	Pub Dt:	12/05/2013
Title:	MANUFACTURING CONTROL BASED ON A FINAL DESIGN STRUCTURE INCORPORATING BOTH LAYOUT AND CLIENT-SPECIFIC MANUFACTURING INFORMATION

Patent #:	8640075	Issue Dt:	01/28/2014	Application #:	13486177	Filing Dt:	06/01/2012
Publication #:	US20130326450	Pub Dt:	12/05/2013
Title:	EARLY DESIGN CYCLE OPTIMZATION

Patent #:	8752283	Issue Dt:	06/17/2014	Application #:	13486573	Filing Dt:	06/01/2012
Publication #:	US20130283591	Pub Dt:	10/31/2013
Title:	Assembly of Electronic and Optical Devices

Patent #:	8917762	Issue Dt:	12/23/2014	Application #:	13486644	Filing Dt:	06/01/2012
Publication #:	US20130322512	Pub Dt:	12/05/2013
Title:	RECEIVER WITH FOUR-SLICE DECISION FEEDBACK EQUALIZER

Patent #:	8635577	Issue Dt:	01/21/2014	Application #:	13486645	Filing Dt:	06/01/2012
Publication #:	US20130326458	Pub Dt:	12/05/2013
Title:	TIMING REFINEMENT RE-ROUTING

Patent #:	NONE	Issue Dt:		Application #:	13487062	Filing Dt:	06/01/2012
Publication #:	US20130326451	Pub Dt:	12/05/2013
Title:	Structured Latch and Local-Clock-Buffer Planning

Patent #:	8569152	Issue Dt:	10/29/2013	Application #:	13487413	Filing Dt:	06/04/2012
Title:	CUT-VERY-LAST DUAL-EPI FLOW

Patent #:	8817533	Issue Dt:	08/26/2014	Application #:	13487427	Filing Dt:	06/04/2012
Publication #:	US20120243291	Pub Dt:	09/27/2012
Title:	CROSSPOINT ARRAY AND METHOD OF USE WITH A CROSSPOINT ARRAY HAVING CROSSBAR ELEMENTS HAVING A SOLID ELECTROLYTE MATERIAL USED AS A RECTIFIER WITH A SYMMETRIC OR SUBSTANTIALLY SYMMETRIC RESISTIVE MEMORY

Patent #:	8604519	Issue Dt:	12/10/2013	Application #:	13487473	Filing Dt:	06/04/2012
Publication #:	US20120248535	Pub Dt:	10/04/2012
Title:	SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET) AND INTEGRATED CIRCUIT (IC) CHIP

Patent #:	8642415	Issue Dt:	02/04/2014	Application #:	13487511	Filing Dt:	06/04/2012
Publication #:	US20130295730	Pub Dt:	11/07/2013
Title:	SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES

Patent #:	8962480	Issue Dt:	02/24/2015	Application #:	13487904	Filing Dt:	06/04/2012
Publication #:	US20120238069	Pub Dt:	09/20/2012
Title:	ESD NETWORK CIRCUIT WITH A THROUGH WAFER VIA STRUCTURE AND A METHOD OF MANUFACTURE

Patent #:	8677305	Issue Dt:	03/18/2014	Application #:	13488065	Filing Dt:	06/04/2012
Publication #:	US20130326456	Pub Dt:	12/05/2013
Title:	DESIGNING A ROBUST POWER EFFICIENT CLOCK DISTRIBUTION NETWORK

Patent #:	8969104	Issue Dt:	03/03/2015	Application #:	13488532	Filing Dt:	06/05/2012
Publication #:	US20130320340	Pub Dt:	12/05/2013
Title:	CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS

Patent #:	NONE	Issue Dt:		Application #:	13488581	Filing Dt:	06/05/2012
Publication #:	US20130320411	Pub Dt:	12/05/2013
Title:	BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION

Patent #:	9048245	Issue Dt:	06/02/2015	Application #:	13488678	Filing Dt:	06/05/2012
Publication #:	US20130320069	Pub Dt:	12/05/2013
Title:	METHOD FOR SHAPING A LAMINATE SUBSTRATE

Patent #:	9129942	Issue Dt:	09/08/2015	Application #:	13488685	Filing Dt:	06/05/2012
Publication #:	US20130320578	Pub Dt:	12/05/2013
Title:	METHOD FOR SHAPING A LAMINATE SUBSTRATE

Patent #:	9059240	Issue Dt:	06/16/2015	Application #:	13488693	Filing Dt:	06/05/2012
Publication #:	US20130323345	Pub Dt:	12/05/2013
Title:	FIXTURE FOR SHAPING A LAMINATE SUBSTRATE

Patent #:	8921975	Issue Dt:	12/30/2014	Application #:	13488870	Filing Dt:	06/05/2012
Publication #:	US20130320488	Pub Dt:	12/05/2013
Title:	SYSTEM AND METHOD FOR FORMING ALUMINUM FUSE FOR COMPATIBILITY WITH COPPER BEOL INTERCONNECT SCHEME

Patent #:	8642787	Issue Dt:	02/04/2014	Application #:	13488940	Filing Dt:	06/05/2012
Publication #:	US20120245218	Pub Dt:	09/27/2012
Title:	SURFACE MODIFIED NANOPARTICLES, METHODS OF THEIR PREPARATION, AND USES THEREOF FOR GENE AND DRUG DELIVERY

Patent #:	8779551	Issue Dt:	07/15/2014	Application #:	13489537	Filing Dt:	06/06/2012
Publication #:	US20130328124	Pub Dt:	12/12/2013
Title:	GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL

Patent #:	8637365	Issue Dt:	01/28/2014	Application #:	13489572	Filing Dt:	06/06/2012
Publication #:	US20130328157	Pub Dt:	12/12/2013
Title:	SPACER ISOLATION IN DEEP TRENCH

Patent #:	8765578	Issue Dt:	07/01/2014	Application #:	13489861	Filing Dt:	06/06/2012
Publication #:	US20130328174	Pub Dt:	12/12/2013
Title:	EDGE PROTECTION OF BONDED WAFERS DURING WAFER THINNING

Patent #:	NONE	Issue Dt:		Application #:	13489940	Filing Dt:	06/06/2012
Publication #:	US20130328167	Pub Dt:	12/12/2013
Title:	SELF-ALIGNED METAL-INSULATOR-METAL (MIM) CAPACITOR

Patent #:	8946866	Issue Dt:	02/03/2015	Application #:	13490239	Filing Dt:	06/06/2012
Publication #:	US20120241913	Pub Dt:	09/27/2012
Title:	MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT

Patent #:	NONE	Issue Dt:		Application #:	13490488	Filing Dt:	06/07/2012
Publication #:	US20130327652	Pub Dt:	12/12/2013
Title:	PLATING BATHS AND METHODS FOR ELECTROPLATING SELENIUM AND SELENIUM ALLOYS

Patent #:	8803321	Issue Dt:	08/12/2014	Application #:	13490542	Filing Dt:	06/07/2012
Publication #:	US20130328208	Pub Dt:	12/12/2013
Title:	DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME

Patent #:	8652340	Issue Dt:	02/18/2014	Application #:	13490618	Filing Dt:	06/07/2012
Publication #:	US20130299448	Pub Dt:	11/14/2013
Title:	FABRICATE SELF-FORMED NANOMETER PORE ARRAY AT WAFER SCALE FOR DNA SEQUENCING

Patent #:	9099461	Issue Dt:	08/04/2015	Application #:	13490740	Filing Dt:	06/07/2012
Publication #:	US20130330843	Pub Dt:	12/12/2013
Title:	METHOD OF MANUFACTURING SCALED EQUIVALENT OXIDE THICKNESS GATE STACKS IN SEMICONDUCTOR DEVICES AND RELATED DESIGN STRUCTURE

Patent #:	8916933	Issue Dt:	12/23/2014	Application #:	13491036	Filing Dt:	06/07/2012
Publication #:	US20120241765	Pub Dt:	09/27/2012
Title:	SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE

Patent #:	9254533	Issue Dt:	02/09/2016	Application #:	13491093	Filing Dt:	06/07/2012
Publication #:	US20120241116	Pub Dt:	09/27/2012
Title:	REMOVING MATERIAL FROM DEFECTIVE OPENING IN GLASS MOLD

Patent #:	9354266	Issue Dt:	05/31/2016	Application #:	13491210	Filing Dt:	06/07/2012
Publication #:	US20130332096	Pub Dt:	12/12/2013
Title:	UNIVERSAL JITTER METER AND PHASE NOISE MEASUREMENT

100

Patent #:	8679909	Issue Dt:	03/25/2014	Application #:	13491857	Filing Dt:	06/08/2012
Publication #:	US20130328111	Pub Dt:	12/12/2013
Title:	RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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