|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13537140
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Filing Dt:
|
06/29/2012
|
Publication #:
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|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
High-k Seal for Protection of Replacement Gates
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|
|
Patent #:
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|
Issue Dt:
|
04/07/2015
|
Application #:
|
13537177
|
Filing Dt:
|
06/29/2012
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
DEVELOPABLE BOTTOM ANTIREFLECTIVE COATING COMPOSITION AND PATTERN FORMING METHOD USING THEREOF
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|
Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
|
13537334
|
Filing Dt:
|
06/29/2012
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC
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|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13537879
|
Filing Dt:
|
06/29/2012
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
Title:
|
INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS
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|
|
Patent #:
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|
Issue Dt:
|
04/16/2013
|
Application #:
|
13538025
|
Filing Dt:
|
06/29/2012
|
Title:
|
CHEMICAL DETECTION WITH MOSFET SENSOR
|
|
|
Patent #:
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|
Issue Dt:
|
10/22/2013
|
Application #:
|
13538276
|
Filing Dt:
|
06/29/2012
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
HIGH-RESOLUTION PHASE INTERPOLATORS
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|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13538593
|
Filing Dt:
|
06/29/2012
|
Publication #:
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|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
ROUTING OF LOCAL CLOCK INTERCONNECTS
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|
|
Patent #:
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|
Issue Dt:
|
10/15/2013
|
Application #:
|
13538621
|
Filing Dt:
|
06/29/2012
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
HIGH-RESOLUTION PHASE INTERPOLATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13539428
|
Filing Dt:
|
06/30/2012
|
Title:
|
LOCAL OBJECTIVE OPTIMIZATION IN GLOBAL PLACEMENT OF AN INTEGRATED CIRCUIT DESIGN
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|
|
Patent #:
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|
Issue Dt:
|
07/01/2014
|
Application #:
|
13539440
|
Filing Dt:
|
06/30/2012
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN INTERMEDIATE PLACEMENT OF AN INTEGRATED CIRCUIT DESIGN
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|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13539480
|
Filing Dt:
|
07/01/2012
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD
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|
|
Patent #:
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|
Issue Dt:
|
07/22/2014
|
Application #:
|
13539544
|
Filing Dt:
|
07/02/2012
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
PINNING MAGNETIC DOMAIN WALLS IN A MAGNETIC DOMAIN SHIFT REGISTER MEMORY DEVICE
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13539550
|
Filing Dt:
|
07/02/2012
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13539700
|
Filing Dt:
|
07/02/2012
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SIGE
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|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13540931
|
Filing Dt:
|
07/03/2012
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
AIR GAP-CONTAINING INTERCONNECT STRUCTURE HAVING PHOTO-PATTERNABLE LOW K MATERIAL
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|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13541022
|
Filing Dt:
|
07/03/2012
|
Publication #:
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|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
Nanowire Tunnel Field Effect Transistors
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|
|
Patent #:
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|
Issue Dt:
|
08/20/2013
|
Application #:
|
13541857
|
Filing Dt:
|
07/05/2012
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
PATTERNED DOPING OF SEMICONDUCTOR SUBSTRATES USING PHOTOSENSITIVE MONOLAYERS
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|
|
Patent #:
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|
Issue Dt:
|
01/27/2015
|
Application #:
|
13541979
|
Filing Dt:
|
07/05/2012
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
Title:
|
INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
01/28/2014
|
Application #:
|
13542003
|
Filing Dt:
|
07/05/2012
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
Title:
|
FIELD-EFFECT-TRANSISTOR WITH SELF-ALIGNED DIFFUSION CONTACT
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|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13543061
|
Filing Dt:
|
07/06/2012
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
Title:
|
DOMAIN WALL MOTION IN PERPENDICULARLY MAGNETIZED WIRES HAVING MAGNETIC MULTILAYERS WITH ENGINEERED INTERFACES
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|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13543090
|
Filing Dt:
|
07/06/2012
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
Title:
|
DOMAIN WALL MOTION IN PERPENDICULARLY MAGNETIZED WIRES HAVING ARTIFICIAL ANTIFERROMAGNETICALLY COUPLED MULTILAYERS WITH ENGINEERED INTERFACES
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|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13543459
|
Filing Dt:
|
07/06/2012
|
Title:
|
FLEXIBLE III-V SOLAR CELL STRUCTURE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13543966
|
Filing Dt:
|
07/09/2012
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
Title:
|
DEEP TRENCH HEAT SINK
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|
|
Patent #:
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|
Issue Dt:
|
10/14/2014
|
Application #:
|
13544093
|
Filing Dt:
|
07/09/2012
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
Title:
|
STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR
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|
|
Patent #:
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|
Issue Dt:
|
03/25/2014
|
Application #:
|
13544134
|
Filing Dt:
|
07/09/2012
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
INTEGRATED DESIGN ENVIRONMENT FOR NANOPHOTONICS
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|
|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
|
13544415
|
Filing Dt:
|
07/09/2012
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
HIGH EFFICIENCY SOLAR CELLS FABRICATED BY INEXPENSIVE PECVD
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|
|
Patent #:
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|
Issue Dt:
|
02/24/2015
|
Application #:
|
13545224
|
Filing Dt:
|
07/10/2012
|
Publication #:
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|
Pub Dt:
|
01/16/2014
| | | | |
Title:
|
FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES
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|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13545456
|
Filing Dt:
|
07/10/2012
|
Publication #:
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|
Pub Dt:
|
12/05/2013
| | | | |
Title:
|
CUT-VERY-LAST DUAL-EPI FLOW
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|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13546150
|
Filing Dt:
|
07/11/2012
|
Title:
|
INVERSION MODE VARACTOR
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|
|
Patent #:
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|
Issue Dt:
|
03/01/2016
|
Application #:
|
13546151
|
Filing Dt:
|
07/11/2012
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
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PRECAST THERMAL INTERFACE ADHESIVE FOR EASY AND REPEATED, SEPARATION AND REMATING
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|
|
Patent #:
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|
Issue Dt:
|
03/24/2015
|
Application #:
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13546509
|
Filing Dt:
|
07/11/2012
|
Publication #:
|
|
Pub Dt:
|
01/16/2014
| | | | |
Title:
|
SELF-PROTECTED METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13546562
|
Filing Dt:
|
07/11/2012
|
Publication #:
|
|
Pub Dt:
|
01/16/2014
| | | | |
Title:
|
SYSTEMS AND METHODS FOR FIXING PIN MISMATCH IN LAYOUT MIGRATION
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|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13546684
|
Filing Dt:
|
07/11/2012
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13547142
|
Filing Dt:
|
07/12/2012
|
Publication #:
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|
Pub Dt:
|
01/16/2014
| | | | |
Title:
|
Replacement Contacts for All-Around Contacts
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|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
13547218
|
Filing Dt:
|
07/12/2012
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
DIFFERENTIALLY RECESSED CONTACTS FOR MULTI-GATE TRANSISTOR OF SRAM CELL
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|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13547485
|
Filing Dt:
|
07/12/2012
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
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USING DIRECT MEMORY ACCESS TO INITIALIZE A PROGRAMMABLE LOGIC DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13547490
|
Filing Dt:
|
07/12/2012
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
USING DIRECT MEMORY ACCESS TO INITIALIZE A PROGRAMMABLE LOGIC DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13547792
|
Filing Dt:
|
07/12/2012
|
Publication #:
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|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
CONTROL OF THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACK AND STRUCTURES FOR CMOS DEVICES
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13548186
|
Filing Dt:
|
07/12/2012
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
Title:
|
THREE DIMENSIONAL FLIP CHIP SYSTEM AND METHOD
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13548554
|
Filing Dt:
|
07/13/2012
|
Publication #:
|
|
Pub Dt:
|
12/26/2013
| | | | |
Title:
|
NANOWIRE FET AND FINFET
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|
|
Patent #:
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|
Issue Dt:
|
06/25/2013
|
Application #:
|
13548916
|
Filing Dt:
|
07/13/2012
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
SLACK-BASED TIMING BUDGET APPORTIONMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13549428
|
Filing Dt:
|
07/14/2012
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
Knowledge-Based Models for Data Centers
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13549440
|
Filing Dt:
|
07/14/2012
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13550091
|
Filing Dt:
|
07/16/2012
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13550092
|
Filing Dt:
|
07/16/2012
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
Analog-Digital Converter
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13550762
|
Filing Dt:
|
07/17/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
SELF-RECONFIGURABLE ADDRESS DECODER FOR ASSOCIATIVE INDEX EXTENDED CACHES
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|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13550813
|
Filing Dt:
|
07/17/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING SENSOR STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
08/19/2014
|
Application #:
|
13550861
|
Filing Dt:
|
07/17/2012
|
Publication #:
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|
Pub Dt:
|
01/23/2014
| | | | |
Title:
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Replacement Gate Fin First Wire Last Gate All Around Devices
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|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13550919
|
Filing Dt:
|
07/17/2012
|
Publication #:
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|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13550957
|
Filing Dt:
|
07/17/2012
|
Publication #:
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|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
SCHEDULING FOR PARALLEL PROCESSING OF REGIONALLY-CONSTRAINED PLACEMENT PROBLEM
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|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
13550967
|
Filing Dt:
|
07/17/2012
|
Title:
|
CHEMICAL DETECTION WITH MOSFET SENSOR
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|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13551054
|
Filing Dt:
|
07/17/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING NFET EXTENSION LAST IMPLANTS
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|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13551164
|
Filing Dt:
|
07/17/2012
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE WITH SHAPED CONDUCTION CHANNEL
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|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13551574
|
Filing Dt:
|
10/01/2012
|
Title:
|
MULTI-BIT RESISTANCE MEASUREMENT
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|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13551597
|
Filing Dt:
|
07/17/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING
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|
|
Patent #:
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|
Issue Dt:
|
12/31/2013
|
Application #:
|
13551659
|
Filing Dt:
|
07/18/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
POST-GATE ISOLATION AREA FORMATION FOR FIN FIELD EFFECT TRANSISTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13551714
|
Filing Dt:
|
07/18/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC
|
|
|
Patent #:
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|
Issue Dt:
|
01/27/2015
|
Application #:
|
13551728
|
Filing Dt:
|
07/18/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
WRITING SCHEME FOR PHASE CHANGE MATERIAL-CONTENT ADDRESSABLE MEMORY
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|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13551766
|
Filing Dt:
|
07/18/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
DRAM WITH DUAL LEVEL WORD LINES
|
|
|
Patent #:
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|
Issue Dt:
|
03/18/2014
|
Application #:
|
13551776
|
Filing Dt:
|
07/18/2012
|
Publication #:
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|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
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|
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Patent #:
|
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Issue Dt:
|
07/08/2014
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Application #:
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13551785
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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01/24/2013
| | | | |
Title:
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TUNNEL FIELD-EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
|
08/11/2015
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Application #:
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13551929
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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01/23/2014
| | | | |
Title:
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DATA CENTER COOLING METHOD
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Patent #:
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Issue Dt:
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02/11/2014
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Application #:
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13551962
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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01/23/2014
| | | | |
Title:
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USE OF GRAPHENE TO LIMIT COPPER SURFACE OXIDATION, DIFFUSION AND ELECTROMIGRATION IN INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
|
09/23/2014
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Application #:
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13551971
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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01/23/2014
| | | | |
Title:
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LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION
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Patent #:
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Issue Dt:
|
01/06/2015
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Application #:
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13552033
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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11/15/2012
| | | | |
Title:
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SPIN-TORQUE BASED MEMORY DEVICE WITH READ AND WRITE CURRENT PATHS MODULATED WITH A NON-LINEAR SHUNT RESISTOR
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Patent #:
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Issue Dt:
|
06/25/2013
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Application #:
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13552091
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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11/08/2012
| | | | |
Title:
|
POWER DELIVERY IN A HETEROGENEOUS 3-D STACKED APPARATUS
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Patent #:
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Issue Dt:
|
09/23/2014
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Application #:
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13552106
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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01/23/2014
| | | | |
Title:
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METHOD OF FORMING VERTICAL ELECTRONIC FUSE INTERCONNECT STRUCTURES INCLUDING A CONDUCTIVE CAP
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Patent #:
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Issue Dt:
|
09/03/2013
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Application #:
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13552205
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
|
11/08/2012
| | | | |
Title:
|
MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER
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Patent #:
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Issue Dt:
|
01/28/2014
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Application #:
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13552293
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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01/23/2014
| | | | |
Title:
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LOW COST ANTI-FUSE STRUCTURE
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Patent #:
|
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Issue Dt:
|
10/29/2013
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Application #:
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13552296
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
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11/08/2012
| | | | |
Title:
|
DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS
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Patent #:
|
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Issue Dt:
|
12/03/2013
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Application #:
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13552634
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Filing Dt:
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07/18/2012
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Publication #:
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Pub Dt:
|
11/08/2012
| | | | |
Title:
|
VERIFYING A PROCESSOR DESIGN USING A PROCESSOR SIMULATION MODEL
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|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13552695
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Filing Dt:
|
07/19/2012
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Publication #:
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Pub Dt:
|
11/08/2012
| | | | |
Title:
|
UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE
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Patent #:
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|
Issue Dt:
|
01/27/2015
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Application #:
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13552727
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Filing Dt:
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07/19/2012
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Publication #:
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|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
Sensor for Biomolecules
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|
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Patent #:
|
|
Issue Dt:
|
06/24/2014
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Application #:
|
13552788
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Filing Dt:
|
07/19/2012
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Publication #:
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|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
CONTROL OF SILVER IN C4 METALLURGY WITH PLATING PROCESS
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|
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Patent #:
|
|
Issue Dt:
|
06/03/2014
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Application #:
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13552792
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Filing Dt:
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07/19/2012
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Publication #:
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Pub Dt:
|
01/23/2014
| | | | |
Title:
|
SOLDER VOLUME COMPENSATION WITH C4 PROCESS
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|
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Patent #:
|
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Issue Dt:
|
12/31/2013
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Application #:
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13552919
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Filing Dt:
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07/19/2012
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Publication #:
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Pub Dt:
|
01/23/2014
| | | | |
Title:
|
GENERATING AND SELECTING BIT-STACK CANDIDATES FROM A GRAPH USING DYNAMIC PROGRAMMING
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Patent #:
|
|
Issue Dt:
|
01/07/2014
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Application #:
|
13553264
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Filing Dt:
|
07/19/2012
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Publication #:
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|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
HOMOGENEOUS POROUS LOW DIELECTRIC CONSTANT MATERIALS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13553559
|
Filing Dt:
|
07/19/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
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Application #:
|
13553882
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Filing Dt:
|
07/20/2012
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Publication #:
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|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
REDISTRIBUTION LAYER (RDL) WITH VARIABLE OFFSET BUMPS
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|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
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Application #:
|
13553887
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Filing Dt:
|
07/20/2012
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Publication #:
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Pub Dt:
|
01/17/2013
| | | | |
Title:
|
SELF ORIENTING MICRO PLATES OF THERMALLY CONDUCTING MATERIAL AS COMPONENT IN THERMAL PASTE OR ADHESIVE
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|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
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Application #:
|
13553941
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Filing Dt:
|
07/20/2012
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Publication #:
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Pub Dt:
|
01/23/2014
| | | | |
Title:
|
OPTIMIZATION METALLIZATION FOR PREVENTION OF DIELECTRIC CRACKING UNDER CONTROLLED COLLAPSE CHIP CONNECTIONS
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|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
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Application #:
|
13553947
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Filing Dt:
|
07/20/2012
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Publication #:
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|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING TRANSISTOR STRUCTURE ON DEPLETED SILICON-ON-INSULATOR, RELATED METHOD AND DESIGN STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
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Application #:
|
13553986
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Filing Dt:
|
07/20/2012
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Publication #:
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Pub Dt:
|
01/23/2014
| | | | |
Title:
|
METHOD AND STRUCTURE FOR MULTI-CORE CHIP PRODUCT TEST AND SELECTIVE VOLTAGE BINNING DISPOSITION
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Patent #:
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Issue Dt:
|
08/27/2013
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Application #:
|
13554057
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Filing Dt:
|
07/20/2012
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Publication #:
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|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
NANOWIRE CIRCUITS IN MATCHED DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
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Application #:
|
13554065
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Filing Dt:
|
07/20/2012
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Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
A P-FET WITH A STRAINED NANOWIRE CHANNEL AND EMBEDDED SIGE SOURCE AND DRAIN STRESSORS
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|
Patent #:
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|
Issue Dt:
|
06/03/2014
|
Application #:
|
13554294
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Filing Dt:
|
07/20/2012
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Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION
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|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13554305
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Filing Dt:
|
07/20/2012
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Publication #:
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|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
Self-Aligned Contacts for Field Effect Transistor Devices
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|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
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Application #:
|
13554382
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Filing Dt:
|
07/20/2012
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Publication #:
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Pub Dt:
|
12/26/2013
| | | | |
Title:
|
PROBE-ON-SUBSTRATE
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|
Patent #:
|
|
Issue Dt:
|
09/01/2015
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Application #:
|
13554886
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Filing Dt:
|
07/20/2012
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Publication #:
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Pub Dt:
|
12/26/2013
| | | | |
Title:
|
PHOTORECEPTOR WITH IMPROVED BLOCKING LAYER
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Patent #:
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|
Issue Dt:
|
10/28/2014
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Application #:
|
13555240
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Filing Dt:
|
07/23/2012
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Publication #:
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|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
METHOD OF MULTIPLE PATTERNING TO FORM SEMICONDUCTOR DEVICES
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|
Patent #:
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Issue Dt:
|
07/14/2015
|
Application #:
|
13555242
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Filing Dt:
|
07/23/2012
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Publication #:
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|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13555251
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Filing Dt:
|
07/23/2012
|
Publication #:
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Pub Dt:
|
01/02/2014
| | | | |
Title:
|
Crossed slit structure for nanopores
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Patent #:
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|
Issue Dt:
|
04/28/2015
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Application #:
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13555252
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Filing Dt:
|
07/23/2012
|
Publication #:
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|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS
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Patent #:
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Issue Dt:
|
11/26/2013
|
Application #:
|
13555261
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Filing Dt:
|
07/23/2012
|
Title:
|
METHOD OF LARGE-AREA CIRCUIT LAYOUT RECOGNITION
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|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13555271
|
Filing Dt:
|
07/23/2012
|
Publication #:
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Pub Dt:
|
12/26/2013
| | | | |
Title:
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RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME
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|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
|
13555362
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Filing Dt:
|
07/23/2012
|
Publication #:
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|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
PINNING MAGNETIC DOMAIN WALLS IN A MAGNETIC DOMAIN SHIFT REGISTER MEMORY DEVICE
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|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13555368
|
Filing Dt:
|
07/23/2012
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13555383
|
Filing Dt:
|
07/23/2012
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
SUPER LATTICE/QUANTUM WELL NANOWIRES
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|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13555451
|
Filing Dt:
|
07/23/2012
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
OPTIMIZED SEMICONDUCTOR PACKAGING IN A THREE-DIMENSIONAL STACK
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|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13556237
|
Filing Dt:
|
07/24/2012
|
Publication #:
|
|
Pub Dt:
|
01/30/2014
| | | | |
Title:
|
PHASE ROTATOR BASED ON VOLTAGE REFERENCING
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|