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Patent #:
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|
Issue Dt:
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06/16/2015
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Application #:
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13598787
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Filing Dt:
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08/30/2012
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Publication #:
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Pub Dt:
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03/06/2014
| | | | |
Title:
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SRAM LOCAL EVALUATION LOGIC FOR COLUMN SELECTION
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Patent #:
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|
Issue Dt:
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11/19/2013
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Application #:
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13598992
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Filing Dt:
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08/30/2012
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Publication #:
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|
Pub Dt:
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12/20/2012
| | | | |
Title:
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SELF-ALIGNED DUAL DEPTH ISOLATION AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13599256
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Filing Dt:
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08/30/2012
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Publication #:
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Pub Dt:
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03/06/2014
| | | | |
Title:
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DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13599295
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Filing Dt:
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08/30/2012
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Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
|
PREVENTION OF THRU-SUBSTRATE VIA PISTONING USING HIGHLY DOPED COPPER ALLOY SEED LAYER
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13599694
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Filing Dt:
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08/30/2012
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Publication #:
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|
Pub Dt:
|
12/20/2012
| | | | |
Title:
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PNEUMATIC METHOD AND APPARATUS FOR NANO IMPRINT LITHOGRAPHY HAVING A CONFORMING MASK
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Patent #:
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Issue Dt:
|
09/09/2014
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Application #:
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13600204
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Filing Dt:
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08/30/2012
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Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
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DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13600314
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Filing Dt:
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08/31/2012
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Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
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FINFET WITH REDUCED PARASITIC CAPACITANCE
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|
Patent #:
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|
Issue Dt:
|
07/15/2014
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Application #:
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13600319
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Filing Dt:
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08/31/2012
|
Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
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SOLUTIONS FOR RETARGETING INTEGRATED CIRCUIT LAYOUTS BASED ON DIFFRACTION PATTERN ANALYSIS
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|
Patent #:
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Issue Dt:
|
11/18/2014
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Application #:
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13600324
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Filing Dt:
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08/31/2012
|
Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
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SUSPENDED NANOWIRE STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
11/10/2015
|
Application #:
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13600598
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Filing Dt:
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08/31/2012
|
Publication #:
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Pub Dt:
|
12/20/2012
| | | | |
Title:
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PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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08/20/2013
|
Application #:
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13600625
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Filing Dt:
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08/31/2012
|
Title:
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SILICON GERMANIUM CHANNEL WITH SILICON BUFFER REGIONS FOR FIN FIELD EFFECT TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
|
08/05/2014
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Application #:
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13601240
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Filing Dt:
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08/31/2012
|
Publication #:
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|
Pub Dt:
|
06/26/2014
| | | | |
Title:
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CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13601958
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Filing Dt:
|
08/31/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
METAL-GRAPHITE FOAM COMPOSITE AND A COOLING APPARATUS FOR USING THE SAME
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|
Patent #:
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|
Issue Dt:
|
06/17/2014
|
Application #:
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13602117
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Filing Dt:
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09/01/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE
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|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
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13602118
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Filing Dt:
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09/01/2012
|
Publication #:
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|
Pub Dt:
|
01/03/2013
| | | | |
Title:
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STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
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|
Patent #:
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|
Issue Dt:
|
06/25/2013
|
Application #:
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13602119
|
Filing Dt:
|
09/01/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
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METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS
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|
Patent #:
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|
Issue Dt:
|
12/31/2013
|
Application #:
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13602123
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Filing Dt:
|
09/01/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
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MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE
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|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
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13602126
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Filing Dt:
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09/01/2012
|
Publication #:
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|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
INTERCONNECT STRUCTURES CONTAINING A PHOTO-PATTERNABLE
LOW-K DIELECTRIC WITH A CURVED SIDEWALL SURFACE
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|
Patent #:
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|
Issue Dt:
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06/10/2014
|
Application #:
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13602164
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Filing Dt:
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09/02/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
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IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13602388
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Filing Dt:
|
09/04/2012
|
Publication #:
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|
Pub Dt:
|
03/14/2013
| | | | |
Title:
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MANUFACTURING A FILLING OF A GAP REGION
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|
Patent #:
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|
Issue Dt:
|
08/30/2016
|
Application #:
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13602496
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Filing Dt:
|
09/04/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
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INTERCONNECT STRUCTURE INCLUDING A MODIFIED PHOTORESIST AS A PERMANENT INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13602644
|
Filing Dt:
|
09/04/2012
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
RAISED SOURCE/DRAIN FIELD EFFECT TRANSISTOR
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|
|
Patent #:
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|
Issue Dt:
|
09/02/2014
|
Application #:
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13602777
|
Filing Dt:
|
09/04/2012
|
Publication #:
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|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS
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|
Patent #:
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|
Issue Dt:
|
07/23/2013
|
Application #:
|
13602957
|
Filing Dt:
|
09/04/2012
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
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HOMOGENEOUS POROUS LOW DIELECTRIC CONSTANT MATERIALS
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|
|
Patent #:
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|
Issue Dt:
|
12/22/2015
|
Application #:
|
13603008
|
Filing Dt:
|
09/04/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13603017
|
Filing Dt:
|
09/04/2012
|
Publication #:
|
|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING
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|
Patent #:
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|
Issue Dt:
|
08/12/2014
|
Application #:
|
13603051
|
Filing Dt:
|
09/04/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS
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|
Patent #:
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|
Issue Dt:
|
06/04/2013
|
Application #:
|
13603086
|
Filing Dt:
|
09/04/2012
|
Publication #:
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|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
SOLID STATE KLYSTRON
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|
|
Patent #:
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|
Issue Dt:
|
12/24/2013
|
Application #:
|
13603110
|
Filing Dt:
|
09/04/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
SOLID STATE KLYSTRON
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|
|
Patent #:
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|
Issue Dt:
|
09/24/2013
|
Application #:
|
13603567
|
Filing Dt:
|
09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13603661
|
Filing Dt:
|
09/05/2012
|
Publication #:
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|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
Semiconductor Devices with Raised Source and Drain Regions
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|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13603739
|
Filing Dt:
|
09/05/2012
|
Publication #:
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|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT
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|
Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
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13603869
|
Filing Dt:
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09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
TONE INVERSION OF SELF-ASSEMBLED SELF-ALIGNED STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13603872
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Filing Dt:
|
09/05/2012
|
Title:
|
RAISED ISOLATION STRUCTURE SELF-ALIGNED TO FIN STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13603879
|
Filing Dt:
|
09/05/2012
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
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ADDING SCALABILITY AND FAULT TOLERANCE TO GENERIC FINITE STATE MACHINE FRAMEWORKS FOR USE IN AUTOMATED INCIDENT MANAGEMENT OF CLOUD COMPUTING INFRASTRUCTURES
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|
Patent #:
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|
Issue Dt:
|
10/14/2014
|
Application #:
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13603892
|
Filing Dt:
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09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
INTEGRATED CROSS-TESTER ANALYSIS AND REAL-TIME ADAPTIVE TEST
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|
Patent #:
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|
Issue Dt:
|
07/09/2013
|
Application #:
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13603927
|
Filing Dt:
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09/05/2012
|
Publication #:
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|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE
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|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
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13603944
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Filing Dt:
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09/05/2012
|
Publication #:
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|
Pub Dt:
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01/03/2013
| | | | |
Title:
|
METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13604004
|
Filing Dt:
|
09/05/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC
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|
|
Patent #:
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|
Issue Dt:
|
08/05/2014
|
Application #:
|
13604036
|
Filing Dt:
|
09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
11/18/2014
|
Application #:
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13604090
|
Filing Dt:
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09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES
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|
Patent #:
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|
Issue Dt:
|
12/10/2013
|
Application #:
|
13604230
|
Filing Dt:
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09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
METHOD TO EVALUATE EFFECTIVENESS OF SUBSTRATE CLEANNESS AND QUANTITY OF PIN HOLES IN AN ANTIREFLECTIVE COATING OF A SOLAR CELL
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13604236
|
Filing Dt:
|
09/05/2012
|
Publication #:
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|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTION WITH IRON DUSTING LAYER BETWEEN FREE LAYER AND TUNNEL BARRIER
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|
Patent #:
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|
Issue Dt:
|
09/17/2013
|
Application #:
|
13604340
|
Filing Dt:
|
09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS
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|
Patent #:
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|
Issue Dt:
|
10/15/2013
|
Application #:
|
13604341
|
Filing Dt:
|
09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
SILICON CARRIER OPTOELECTRONIC PACKAGING
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|
Patent #:
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|
Issue Dt:
|
05/26/2015
|
Application #:
|
13604363
|
Filing Dt:
|
09/05/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
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|
Patent #:
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|
Issue Dt:
|
09/23/2014
|
Application #:
|
13604658
|
Filing Dt:
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09/06/2012
|
Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
|
BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER
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|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
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13604660
|
Filing Dt:
|
09/06/2012
|
Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
|
OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
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|
Patent #:
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|
Issue Dt:
|
01/07/2014
|
Application #:
|
13604666
|
Filing Dt:
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09/06/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
MULTI-ANODE SYSTEM FOR UNIFORM PLATING OF ALLOYS
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|
Patent #:
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|
Issue Dt:
|
07/09/2013
|
Application #:
|
13604671
|
Filing Dt:
|
09/06/2012
|
Publication #:
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|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES TO ACHIEVE A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE, A METHOD OF FORMING THE TRANSISTOR AND A PROGRAM STORAGE DEVICE FOR DESIGNING THE TRANSISTOR
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|
Patent #:
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|
Issue Dt:
|
09/06/2016
|
Application #:
|
13604739
|
Filing Dt:
|
09/06/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
Deposition On A Nanowire Using Atomic Layer Deposition
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|
|
Patent #:
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|
Issue Dt:
|
07/21/2015
|
Application #:
|
13604800
|
Filing Dt:
|
09/06/2012
|
Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
|
SRAM LOCAL EVALUATION AND WRITE LOGIC FOR COLUMN SELECTION
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|
|
Patent #:
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|
Issue Dt:
|
11/05/2013
|
Application #:
|
13604814
|
Filing Dt:
|
09/06/2012
|
Title:
|
CIRCUIT DESIGN WITH GROWABLE CAPACITOR ARRAYS
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|
Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
|
13604820
|
Filing Dt:
|
09/06/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
METHODS FOR CONTROLLING WAFER CURVATURE
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|
Patent #:
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|
Issue Dt:
|
12/23/2014
|
Application #:
|
13604878
|
Filing Dt:
|
09/06/2012
|
Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
|
WIRE BOND SPLASH CONTAINMENT
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13604959
|
Filing Dt:
|
09/06/2012
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
LARGE-GRAIN, LOW-RESISTIVITY TUNGSTEN ON A CONDUCTIVE COMPOUND
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|
Patent #:
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|
Issue Dt:
|
12/31/2013
|
Application #:
|
13604963
|
Filing Dt:
|
09/06/2012
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATES USING BANDGAP MATERIAL BETWEEN III-V CHANNEL MATERIAL AND INSULATOR LAYER
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|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13604986
|
Filing Dt:
|
09/06/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
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COMPREHENSIVE ANALYSIS OF QUEUE TIMES IN MICROELECTRONIC MANUFACTURING
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Patent #:
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Issue Dt:
|
01/27/2015
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Application #:
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13604995
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Filing Dt:
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09/06/2012
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Publication #:
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Pub Dt:
|
03/07/2013
| | | | |
Title:
|
AMPLIFIERS USING GATED DIODES
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13605085
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Filing Dt:
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09/06/2012
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Publication #:
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Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets
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Patent #:
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|
Issue Dt:
|
06/03/2014
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Application #:
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13605136
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Filing Dt:
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09/06/2012
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Publication #:
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Pub Dt:
|
12/27/2012
| | | | |
Title:
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FORMATION OF DIVIDERS BETWEEN GATE ENDS OF FIELD EFFECT TRANSISTOR DEVICES
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Patent #:
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Issue Dt:
|
06/03/2014
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Application #:
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13605144
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Filing Dt:
|
09/06/2012
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Publication #:
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|
Pub Dt:
|
01/24/2013
| | | | |
Title:
|
BORDERLESS CONTACTS IN SEMICONDUCTOR DEVICES
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13605168
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Filing Dt:
|
09/06/2012
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Publication #:
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|
Pub Dt:
|
03/06/2014
| | | | |
Title:
|
PRODUCT RELIABILITY ESTIMATION
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|
Patent #:
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|
Issue Dt:
|
10/15/2013
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Application #:
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13605253
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Filing Dt:
|
09/06/2012
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Publication #:
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|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT
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Patent #:
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|
Issue Dt:
|
11/26/2013
|
Application #:
|
13605363
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Filing Dt:
|
09/06/2012
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Publication #:
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|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
MULTI-SPINDLE CHEMICAL MECHANICAL PLANARIZATION TOOL
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Patent #:
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Issue Dt:
|
10/07/2014
|
Application #:
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13606055
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Filing Dt:
|
09/07/2012
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Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13606071
|
Filing Dt:
|
09/07/2012
|
Publication #:
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|
Pub Dt:
|
03/13/2014
| | | | |
Title:
|
PARTICLE DETECTION AND CLEANING SYSTEM
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|
Patent #:
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|
Issue Dt:
|
11/26/2013
|
Application #:
|
13606326
|
Filing Dt:
|
09/07/2012
|
Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
|
ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE
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|
Patent #:
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|
Issue Dt:
|
10/15/2013
|
Application #:
|
13606365
|
Filing Dt:
|
09/07/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
Nanowire Field Effect Transistors
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|
Patent #:
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|
Issue Dt:
|
10/22/2013
|
Application #:
|
13606382
|
Filing Dt:
|
09/07/2012
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE WITH RAISED ACTIVE REGIONS
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|
Patent #:
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|
Issue Dt:
|
06/02/2015
|
Application #:
|
13606448
|
Filing Dt:
|
09/07/2012
|
Publication #:
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|
Pub Dt:
|
03/13/2014
| | | | |
Title:
|
DEEP TRENCH CAPACITOR
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13606778
|
Filing Dt:
|
09/07/2012
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
MODULAR ARRAY OF FIXED-COUPLING QUANTUM SYSTEMS FOR QUANTUM INFORMATION PROCESSING
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|
Patent #:
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|
Issue Dt:
|
12/08/2015
|
Application #:
|
13606788
|
Filing Dt:
|
09/07/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION
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|
Patent #:
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|
Issue Dt:
|
01/14/2014
|
Application #:
|
13606816
|
Filing Dt:
|
09/07/2012
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS
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|
|
Patent #:
|
|
Issue Dt:
|
03/15/2016
|
Application #:
|
13606873
|
Filing Dt:
|
09/07/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
FINFET FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING
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|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13606893
|
Filing Dt:
|
09/07/2012
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
SOI FINFET WITH RECESSED MERGED FINS AND LINER FOR ENHANCED STRESS COUPLING
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|
Patent #:
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|
Issue Dt:
|
01/06/2015
|
Application #:
|
13606904
|
Filing Dt:
|
09/07/2012
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
SELF-SEALED FLUIDIC CHANNELS FOR A NANOPORE ARRAY
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|
Patent #:
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|
Issue Dt:
|
05/26/2015
|
Application #:
|
13606916
|
Filing Dt:
|
09/07/2012
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
FORMATION OF METAL NANOSPHERES AND MICROSPHERES
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|
Patent #:
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|
Issue Dt:
|
03/18/2014
|
Application #:
|
13606940
|
Filing Dt:
|
09/07/2012
|
Publication #:
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|
Pub Dt:
|
03/13/2014
| | | | |
Title:
|
CLOCK FEATHERED SLEW RATE CONTROL SYSTEM
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|
Patent #:
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|
Issue Dt:
|
01/06/2015
|
Application #:
|
13607020
|
Filing Dt:
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09/07/2012
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STACK OF INTEGRATED CIRCUITS
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|
Patent #:
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|
Issue Dt:
|
06/18/2013
|
Application #:
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13607089
|
Filing Dt:
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09/07/2012
|
Publication #:
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|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING
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|
Patent #:
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Issue Dt:
|
12/03/2013
|
Application #:
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13607589
|
Filing Dt:
|
09/07/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
CONTROLLING THRESHOLD VOLTAGE IN CARBON BASED FIELD EFFECT TRANSISTORS
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|
Patent #:
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Issue Dt:
|
10/15/2013
|
Application #:
|
13607672
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Filing Dt:
|
09/08/2012
|
Title:
|
GERMANIUM LATERAL BIPOLAR JUNCTION TRANSISTOR
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|
Patent #:
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Issue Dt:
|
07/01/2014
|
Application #:
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13607674
|
Filing Dt:
|
09/08/2012
|
Publication #:
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Pub Dt:
|
01/03/2013
| | | | |
Title:
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TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS
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|
Patent #:
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Issue Dt:
|
04/22/2014
|
Application #:
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13607677
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Filing Dt:
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09/08/2012
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS
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Patent #:
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Issue Dt:
|
11/05/2013
|
Application #:
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13607678
|
Filing Dt:
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09/08/2012
|
Publication #:
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|
Pub Dt:
|
10/17/2013
| | | | |
Title:
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METHODOLOGIES FOR AUTOMATIC 3-D DEVICE STRUCTURE SYNTHESIS FROM CIRCUIT LAYOUTS FOR DEVICE SIMULATION
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Patent #:
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Issue Dt:
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04/01/2014
|
Application #:
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13607680
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Filing Dt:
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09/08/2012
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Publication #:
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Pub Dt:
|
12/27/2012
| | | | |
Title:
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SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT
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Patent #:
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Issue Dt:
|
10/31/2017
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Application #:
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13607741
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Filing Dt:
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09/09/2012
|
Publication #:
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Pub Dt:
|
12/27/2012
| | | | |
Title:
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HIGH k GATE STACK ON III-V COMPOUND SEMICONDUCTORS
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13607743
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Filing Dt:
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09/09/2012
|
Publication #:
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|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS
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Patent #:
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Issue Dt:
|
12/16/2014
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Application #:
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13607744
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Filing Dt:
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09/09/2012
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Publication #:
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Pub Dt:
|
12/27/2012
| | | | |
Title:
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CAPPING COATING FOR 3D INTEGRATION APPLICATIONS
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13607856
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
|
03/13/2014
| | | | |
Title:
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SELF-ALIGNED CONTACTS
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Patent #:
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Issue Dt:
|
06/24/2014
|
Application #:
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13607869
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
|
12/27/2012
| | | | |
Title:
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BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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13607875
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Filing Dt:
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09/10/2012
|
Publication #:
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Pub Dt:
|
06/27/2013
| | | | |
Title:
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THIN HETEREOSTRUCTURE CHANNEL DEVICE
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Patent #:
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Issue Dt:
|
12/31/2013
|
Application #:
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13607877
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Filing Dt:
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09/10/2012
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Title:
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FIN BIPOLAR TRANSISTORS HAVING SELF-ALIGNED COLLECTOR AND EMITTER REGIONS
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Patent #:
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Issue Dt:
|
11/26/2013
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Application #:
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13608032
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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01/03/2013
| | | | |
Title:
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METHOD AND SYSTEM FOR EVALUATING A MACHINE TOOL OPERATING CHARACTERISTICS
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Patent #:
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Issue Dt:
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05/27/2014
|
Application #:
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13608183
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Filing Dt:
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09/10/2012
|
Publication #:
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Pub Dt:
|
03/13/2014
| | | | |
Title:
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ELECTRONIC ANTI-FUSE
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|
Patent #:
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Issue Dt:
|
08/12/2014
|
Application #:
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13608211
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Filing Dt:
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09/10/2012
|
Publication #:
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Pub Dt:
|
03/13/2014
| | | | |
Title:
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Semiconductor plural gate lengths
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|
Patent #:
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Issue Dt:
|
04/22/2014
|
Application #:
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13608277
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Filing Dt:
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09/10/2012
|
Publication #:
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Pub Dt:
|
03/13/2014
| | | | |
Title:
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HYBRID PHASE-LOCKED LOOP ARCHITECTURES
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|
Patent #:
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Issue Dt:
|
05/13/2014
|
Application #:
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13608281
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Filing Dt:
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09/10/2012
|
Publication #:
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Pub Dt:
|
12/27/2012
| | | | |
Title:
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MULTI-MODE MULTIPLEXING USING STAGED COUPLING AND QUASI-PHASE-MATCHING
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|
Patent #:
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Issue Dt:
|
07/23/2013
|
Application #:
|
13608314
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Filing Dt:
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09/10/2012
|
Publication #:
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|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND STRUCTURE INCLUDING MULTIPLE ORDER RADIO FREQUENCY HARMONIC SUPRESSING REGION
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|