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10/23/2014
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03/19/2015
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10/30/2014
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02/05/2015
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10/30/2014
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01/22/2015
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10/30/2014
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01/21/2016
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11/06/2014
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01/27/2015
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01/29/2015
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Pub Dt:
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03/05/2015
| | | | |
Title:
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REDUCING OVERHEAD IN LOADING CONSTANTS
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Patent #:
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Issue Dt:
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02/10/2015
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Application #:
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14446634
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Filing Dt:
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07/30/2014
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Publication #:
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Pub Dt:
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11/20/2014
| | | | |
Title:
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METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
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Patent #:
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Issue Dt:
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08/09/2016
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Application #:
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14446710
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Filing Dt:
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07/30/2014
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Publication #:
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Pub Dt:
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02/05/2015
| | | | |
Title:
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IDENTIFYING CONTENT FROM AN ENCRYPTED COMMUNICATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14447111
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Filing Dt:
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07/30/2014
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Publication #:
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Pub Dt:
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03/19/2015
| | | | |
Title:
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Virtual Storage Devices Formed by Selected Partitions of a Physical Storage Device
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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14447710
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Filing Dt:
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07/31/2014
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Publication #:
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Pub Dt:
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11/20/2014
| | | | |
Title:
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STRUCTURE AND METHOD FOR MAKING CRACK STOP FOR 3D INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/23/2017
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Application #:
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14448790
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Filing Dt:
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07/31/2014
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Publication #:
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Pub Dt:
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02/05/2015
| | | | |
Title:
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TECHNIQUES FOR INCREASING INSTRUCTION ISSUE RATE AND REDUCING LATENCY IN AN OUT-OF-ORDER PROCESSOR
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Patent #:
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Issue Dt:
|
06/30/2015
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Application #:
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14449177
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Filing Dt:
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08/01/2014
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Publication #:
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Pub Dt:
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03/12/2015
| | | | |
Title:
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ELECTROMECHANICAL SWITCHING DEVICE WITH 2D LAYERED MATERIAL SURFACES
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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14449180
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Filing Dt:
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08/01/2014
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Publication #:
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Pub Dt:
|
11/20/2014
| | | | |
Title:
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LOW VOLTAGE METAL GATE ANTIFUSE WITH DEPLETION MODE MOSFET
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Patent #:
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Issue Dt:
|
07/26/2016
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Application #:
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14449185
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Filing Dt:
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08/01/2014
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Publication #:
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Pub Dt:
|
02/04/2016
| | | | |
Title:
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HANDLER WAFER REMOVAL BY USE OF SACRIFICIAL INERT LAYER
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Patent #:
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Issue Dt:
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02/23/2016
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Application #:
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14449314
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Filing Dt:
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08/01/2014
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Publication #:
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Pub Dt:
|
11/20/2014
| | | | |
Title:
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DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME
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Patent #:
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Issue Dt:
|
08/11/2015
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Application #:
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14449557
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Filing Dt:
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08/01/2014
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Publication #:
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Pub Dt:
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11/20/2014
| | | | |
Title:
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PIXEL SENSOR CELL WITH HOLD NODE FOR LEAKAGE CANCELLATION AND METHODS OF MANUFACTURE AND DESIGN STRUCTURE
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Patent #:
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Issue Dt:
|
08/09/2016
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Application #:
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14449592
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Filing Dt:
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08/01/2014
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Publication #:
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Pub Dt:
|
11/20/2014
| | | | |
Title:
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VISUALIZATION INTERFACE OF CONTINUOUS WAVEFORM MULTI-SPEAKER IDENTIFICATION
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Patent #:
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Issue Dt:
|
02/21/2017
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Application #:
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14449666
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Filing Dt:
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08/01/2014
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Publication #:
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|
Pub Dt:
|
02/04/2016
| | | | |
Title:
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TRACKING A RELATIVE ARRIVAL ORDER OF EVENTS BEING STORED IN MULTIPLE QUEUES USING A COUNTER USING MOST SIGNIFICANT BIT VALUES
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
14450721
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Filing Dt:
|
08/04/2014
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Publication #:
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|
Pub Dt:
|
02/12/2015
| | | | |
Title:
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TECHNIQUES FOR VALIDATING DISTRIBUTED DENIAL OF SERVICE ATTACKS BASED ON SOCIAL MEDIA CONTENT
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Patent #:
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Issue Dt:
|
11/17/2015
|
Application #:
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14451493
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Filing Dt:
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08/05/2014
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Publication #:
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|
Pub Dt:
|
11/19/2015
| | | | |
Title:
|
TRANSISTOR STRUCTURE HAVING AN ELECTRICAL CONTACT STRUCTURE WITH MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER
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Patent #:
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Issue Dt:
|
02/14/2017
|
Application #:
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14451716
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Filing Dt:
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08/05/2014
|
Publication #:
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|
Pub Dt:
|
02/11/2016
| | | | |
Title:
|
SELF-ALIGNED EMITTER-BASE BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE AND BASE-COLLECTOR CAPACITANCE
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Patent #:
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Issue Dt:
|
03/22/2016
|
Application #:
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14451778
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Filing Dt:
|
08/05/2014
|
Publication #:
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|
Pub Dt:
|
03/05/2015
| | | | |
Title:
|
REMOTE DATA STORAGE
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|
|
Patent #:
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|
Issue Dt:
|
07/21/2015
|
Application #:
|
14451836
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Filing Dt:
|
08/05/2014
|
Publication #:
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|
Pub Dt:
|
11/20/2014
| | | | |
Title:
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FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES
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|
Patent #:
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Issue Dt:
|
01/05/2016
|
Application #:
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14452741
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Filing Dt:
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08/06/2014
|
Title:
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NANOCHANNEL ELECTRODE DEVICES
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|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
14452758
|
Filing Dt:
|
08/06/2014
|
Publication #:
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|
Pub Dt:
|
11/20/2014
| | | | |
Title:
|
FINFET WITH VERTICAL SILICIDE STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
09/05/2017
|
Application #:
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14452762
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Filing Dt:
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08/06/2014
|
Publication #:
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|
Pub Dt:
|
02/11/2016
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE EMPLOYING A DEEP TRENCH CAPACITOR
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|
Patent #:
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|
Issue Dt:
|
11/17/2015
|
Application #:
|
14453227
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Filing Dt:
|
08/06/2014
|
Publication #:
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|
Pub Dt:
|
03/05/2015
| | | | |
Title:
|
ALIGNING A FIRST ELEMENT COUPLED TO AN ACTUATOR WITH A SECOND ELEMENT OF A MAIN SYSTEM
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
14453700
|
Filing Dt:
|
08/07/2014
|
Publication #:
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|
Pub Dt:
|
04/02/2015
| | | | |
Title:
|
Reading Speed of Updated File by Tape Drive File System
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|
Patent #:
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|
Issue Dt:
|
10/04/2016
|
Application #:
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14453779
|
Filing Dt:
|
08/07/2014
|
Publication #:
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|
Pub Dt:
|
11/27/2014
| | | | |
Title:
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READ ONLY MEMORY (ROM) WITH REDUNDANCY
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
14453882
|
Filing Dt:
|
08/07/2014
|
Publication #:
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|
Pub Dt:
|
02/11/2016
| | | | |
Title:
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ACIDIFIED CONDUCTIVE WATER FOR DEVELOPER RESIDUE REMOVAL
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|
Patent #:
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|
Issue Dt:
|
08/30/2016
|
Application #:
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14454765
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Filing Dt:
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08/08/2014
|
Publication #:
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|
Pub Dt:
|
11/27/2014
| | | | |
Title:
|
GRAPHENE-METAL E-FUSE
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|
Patent #:
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|
Issue Dt:
|
04/19/2016
|
Application #:
|
14455816
|
Filing Dt:
|
08/08/2014
|
Publication #:
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|
Pub Dt:
|
11/27/2014
| | | | |
Title:
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COMBINED SOFT DETECTION/SOFT DECODING IN TAPE DRIVE STORAGE CHANNELS
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|
Patent #:
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|
Issue Dt:
|
02/24/2015
|
Application #:
|
14456199
|
Filing Dt:
|
08/11/2014
|
Publication #:
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|
Pub Dt:
|
11/27/2014
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
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Patent #:
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Issue Dt:
|
07/21/2015
|
Application #:
|
14457273
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Filing Dt:
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08/12/2014
|
Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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FINFET WITH ENHANCED EMBEDDED STRESSOR
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Patent #:
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Issue Dt:
|
06/16/2015
|
Application #:
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14457537
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Filing Dt:
|
08/12/2014
|
Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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THREAD SERIALIZATION AND DISABLEMENT TOOL
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|
Patent #:
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Issue Dt:
|
11/21/2017
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Application #:
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14457545
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Filing Dt:
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08/12/2014
|
Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME
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|
Patent #:
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Issue Dt:
|
03/17/2015
|
Application #:
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14458428
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Filing Dt:
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08/13/2014
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Publication #:
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|
Pub Dt:
|
03/05/2015
| | | | |
Title:
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PASSGATE STRENGTH CALIBRATION TECHNIQUES FOR VOLTAGE REGULATORS
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
14458459
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Filing Dt:
|
08/13/2014
|
Publication #:
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|
Pub Dt:
|
11/27/2014
| | | | |
Title:
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SILICON-ON-INSULATOR (SOI) BODY-CONTACT PASS GATE STRUCTURE
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Patent #:
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Issue Dt:
|
04/12/2016
|
Application #:
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14459407
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Filing Dt:
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08/14/2014
|
Publication #:
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|
Pub Dt:
|
02/18/2016
| | | | |
Title:
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BLOCK PATTERNING PROCESS FOR POST FIN
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|
Patent #:
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|
Issue Dt:
|
06/30/2015
|
Application #:
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14460921
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Filing Dt:
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08/15/2014
|
Publication #:
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|
Pub Dt:
|
12/04/2014
| | | | |
Title:
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BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER
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|
Patent #:
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Issue Dt:
|
09/22/2015
|
Application #:
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14461737
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Filing Dt:
|
08/18/2014
|
Publication #:
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|
Pub Dt:
|
12/04/2014
| | | | |
Title:
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LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY
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Patent #:
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|
Issue Dt:
|
03/29/2016
|
Application #:
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14462112
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Filing Dt:
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08/18/2014
|
Publication #:
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|
Pub Dt:
|
03/05/2015
| | | | |
Title:
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Automatically Generating Route Directions Based On Signpost Data
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|
Patent #:
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|
Issue Dt:
|
05/24/2016
|
Application #:
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14463025
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Filing Dt:
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08/19/2014
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Publication #:
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|
Pub Dt:
|
12/04/2014
| | | | |
Title:
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HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS
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|
Patent #:
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Issue Dt:
|
07/26/2016
|
Application #:
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14464090
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Filing Dt:
|
08/20/2014
|
Publication #:
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|
Pub Dt:
|
11/19/2015
| | | | |
Title:
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Stacked Memory Device Control
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|
Patent #:
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|
Issue Dt:
|
03/17/2015
|
Application #:
|
14464282
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Filing Dt:
|
08/20/2014
|
Publication #:
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|
Pub Dt:
|
12/04/2014
| | | | |
Title:
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EFUSE AND METHOD OF FABRICATION
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|
Patent #:
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|
Issue Dt:
|
03/14/2017
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Application #:
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14465248
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Filing Dt:
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08/21/2014
|
Publication #:
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Pub Dt:
|
02/26/2015
| | | | |
Title:
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TECHNIQUES FOR UPDATING MEMORY OF A CHASSIS MANAGEMENT MODULE
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|
Patent #:
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|
Issue Dt:
|
06/09/2015
|
Application #:
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14465255
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Filing Dt:
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08/21/2014
|
Publication #:
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|
Pub Dt:
|
01/29/2015
| | | | |
Title:
|
RANDOM LOCAL METAL CAP LAYER FORMATION FOR IMPROVED INTEGRATED CIRCUIT RELIABILITY
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|