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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09769640
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Filing Dt:
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01/25/2001
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Publication #:
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|
Pub Dt:
|
07/25/2002
| | | | |
Title:
|
STI PULL-DOWN TO CONTROL SIGE FACET GROWTH
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Patent #:
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Issue Dt:
|
10/15/2002
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Application #:
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09769667
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
|
07/25/2002
| | | | |
Title:
|
ESD ROBUST SILICON GERMANIUM TRANSISTOR WITH EMITTER NP-BLOCK MASK EXTRINSIC BASE BALLASTING RESISTOR WITH DOPED FACET REGION
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09770788
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
|
T-RAM ARRAY HAVING A PLANAR CELL STRUCTURE AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
|
04/22/2003
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Application #:
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09770913
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
|
07/26/2001
| | | | |
Title:
|
HIGH PERFORMANCE CHIP PACKAGING AND METHOD
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Patent #:
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Issue Dt:
|
12/02/2003
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Application #:
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09770915
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
|
07/26/2001
| | | | |
Title:
|
METHOD OF PACKAGING A HIGH PERFORMANCE CHIP
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09771149
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
|
10/10/2002
| | | | |
Title:
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NORBORNENE FLUOROACRYLATE COPOLYMERS AND PROCESS FOR USE THEREOF
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Patent #:
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Issue Dt:
|
05/04/2004
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Application #:
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09771261
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
|
10/10/2002
| | | | |
Title:
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LITHOGRAPHIC PHOTORESIST COMPOSITION AND PROCESS FOR ITS USE
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Patent #:
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Issue Dt:
|
04/15/2003
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Application #:
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09771262
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
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SUBSTITUTED NORBORNENE FLUOROACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
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Patent #:
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Issue Dt:
|
09/17/2002
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Application #:
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09771778
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Filing Dt:
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01/29/2001
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Publication #:
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Pub Dt:
|
07/05/2001
| | | | |
Title:
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SEMICONDUCTOR DEVICES HAVING BACKSIDE PROBING CAPABILITY
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09772205
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Filing Dt:
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01/29/2001
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Publication #:
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Pub Dt:
|
10/10/2002
| | | | |
Title:
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METHOD OF FORMING RECESSED THIN FILM LANDING PAD STRUCTURE
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
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09772345
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Filing Dt:
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01/30/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
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METHOD FOR DELINEATION OF EDRAM SUPPORT DEVICE NOTCHED GATE
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09772459
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Filing Dt:
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01/30/2001
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Publication #:
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Pub Dt:
|
09/13/2001
| | | | |
Title:
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METHOD FOR CONSTRUCTING AN ENCAPSULATED MEMS BAND-PASS FILTER FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
11/04/2003
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Application #:
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09772630
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Filing Dt:
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01/30/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
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DUAL WORK FUNCTION SEMICONDUCTOR STRUCTURE WITH BORDERLESS CONTACT AND METHOD OF FABRICATING THE SAME
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Patent #:
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Issue Dt:
|
01/21/2003
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Application #:
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09773323
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
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METHOD FOR WRITING AND/OR ERASING HIGH DENSITY DATA ON A MEDIA
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Patent #:
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Issue Dt:
|
10/22/2002
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Application #:
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09773488
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Filing Dt:
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02/02/2001
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Publication #:
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Pub Dt:
|
10/04/2001
| | | | |
Title:
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COMPOSITION FOR INCREASING ACTIVITY OF A NO-CLEAN FLUX
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Patent #:
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Issue Dt:
|
05/08/2007
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Application #:
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09773798
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Filing Dt:
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02/01/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
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PASSIVATION FOR IMPROVED BIPOLAR YIELD
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09774126
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Filing Dt:
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01/30/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
|
INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09774152
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Filing Dt:
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01/30/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
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FLIP CHIP PACKAGE WITH IMPROVED CAP DESIGN AND PROCESS FOR MAKING THEREOF
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Patent #:
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Issue Dt:
|
05/18/2004
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Application #:
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09774489
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
|
09/26/2002
| | | | |
Title:
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HEAD-MOUNTED DISPLAY CONTENT TRANSFORMER
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Patent #:
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Issue Dt:
|
07/19/2005
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Application #:
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09774943
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
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ASSEMBLY FOR WRITING AND / OR ERASING HIGH DENSITY DATA ON A MEDIA
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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09775374
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Filing Dt:
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02/01/2001
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Publication #:
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Pub Dt:
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08/01/2002
| | | | |
Title:
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SYSTEM AND METHOD FOR REMOTE OPTICAL DIGITAL NETWORKING OF COMPUTING DEVICES
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09777004
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Filing Dt:
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02/07/2001
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Publication #:
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Pub Dt:
|
08/08/2002
| | | | |
Title:
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HIGH SPEED DRAM LOCAL BIT LINE SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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09777506
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Filing Dt:
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02/05/2001
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Publication #:
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Pub Dt:
|
08/08/2002
| | | | |
Title:
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METHOD FOR ASSIGNING ENCRYPTION KEYS
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Patent #:
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Issue Dt:
|
11/12/2002
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Application #:
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09777539
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Filing Dt:
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02/06/2001
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Publication #:
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Pub Dt:
|
06/28/2001
| | | | |
Title:
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MULTI-WAFER POLISHING TOOL
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
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09777548
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Filing Dt:
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02/06/2001
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Publication #:
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Pub Dt:
|
08/08/2002
| | | | |
Title:
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SUPPORT AND ALIGNMENT DEVICE FOR ENABLING CHEMICAL MECHANICAL POLISHING RINSE AND FILM MEASUREMENTS
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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09777976
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Filing Dt:
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02/06/2001
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Publication #:
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Pub Dt:
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06/21/2001
| | | | |
Title:
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WAVE SOLDER APPLICATION FOR BALL GRID ARRAY MODULES
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09778335
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Filing Dt:
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02/07/2001
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Publication #:
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Pub Dt:
|
08/08/2002
| | | | |
Title:
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DAMASCENE DOUBLE-GATE MOSFET STRUCTURE AND ITS FABRICATION METHOD
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09779043
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Filing Dt:
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02/08/2001
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Publication #:
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Pub Dt:
|
08/16/2001
| | | | |
Title:
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METHOD FOR ATTENUATING THERMAL SENSATION WHEN HANDLING OBJECTS AT NON-BODY TEMPERATURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09779044
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Filing Dt:
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02/08/2001
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Publication #:
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Pub Dt:
|
10/11/2001
| | | | |
Title:
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Method for attenuating thermal sensation when handling objects at non-body temperature
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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09780558
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Filing Dt:
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02/09/2001
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
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METHOD AND SYSTEM FOR FAULT-TOLERANT STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09781014
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Filing Dt:
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02/10/2001
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
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HIGH Q INDUCTOR WITH FARADAY SHIELD AND DIELECTRIC WELL BURIED IN SUBSTRATE
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09781121
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Filing Dt:
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02/09/2001
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
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COMMON BALL-LIMITING METALLURGY FOR I/O SITES
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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09781369
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
|
08/21/2003
| | | | |
Title:
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WIRING OPTIMIZATIONS FOR POWER
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09781637
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
|
06/28/2001
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A THERMOSET-CONTAINING DIELECTRIC MATERIAL AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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09781730
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
|
11/15/2001
| | | | |
Title:
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SMICONDUCTOR DEVICE HAVING A THERMOSET- CONTAINING DIELECTRIC MATERIAL AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09782828
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Filing Dt:
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02/13/2001
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Publication #:
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Pub Dt:
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06/28/2001
| | | | |
Title:
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CIRCUIT TRACE PROBE AND METHOD
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09785432
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Filing Dt:
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02/16/2001
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Publication #:
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Pub Dt:
|
08/22/2002
| | | | |
Title:
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CONDUCTIVE COUPLING OF ELECTRICAL STRUCTURES TO A SEMICONDUCTOR DEVICE LOCATED UNDER A BURIED OXIDE LAYER
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09785609
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Filing Dt:
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02/16/2001
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Publication #:
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Pub Dt:
|
08/22/2002
| | | | |
Title:
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RADIATION SENSITIVE SILICON-CONTAINING NEGATIVE RESISTS AND USE THEREOF
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|
Patent #:
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Issue Dt:
|
12/30/2003
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Application #:
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09788081
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Filing Dt:
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02/16/2001
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Publication #:
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Pub Dt:
|
01/30/2003
| | | | |
Title:
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DRILL STACK FORMATION
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Patent #:
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Issue Dt:
|
09/30/2003
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Application #:
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09788631
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Filing Dt:
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02/16/2001
|
Publication #:
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Pub Dt:
|
06/28/2001
| | | | |
Title:
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METHOD OF DESIGNING AND STRUCTURE FOR VISUAL AND ELECTRICAL TEST OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09788635
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Filing Dt:
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02/21/2001
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Publication #:
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Pub Dt:
|
10/10/2002
| | | | |
Title:
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GUI FOR REPRESENTING ENTITY MATCHES UTILIZING GRAPHICAL TRANSITIONS PERFORMED DIRECTLY ON THE MATCHING OBJECT
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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09788925
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Filing Dt:
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02/20/2001
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Publication #:
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Pub Dt:
|
08/22/2002
| | | | |
Title:
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METHOD FOR INSERTION OF TEST POINTS INTO INTEGRATED CIRCUIT LOGIC DESIGNS
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09788979
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Filing Dt:
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02/20/2001
|
Publication #:
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Pub Dt:
|
08/22/2002
| | | | |
Title:
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DOUBLE SOI DEVICE WITH RECESS ETCH AND EPITAXY
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Patent #:
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Issue Dt:
|
02/03/2004
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Application #:
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09789156
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Filing Dt:
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02/20/2001
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Publication #:
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Pub Dt:
|
10/25/2001
| | | | |
Title:
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MANUFACTURING METHODS FOR PRINTED CIRCUIT BOARDS
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Patent #:
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|
Issue Dt:
|
09/24/2002
|
Application #:
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09789422
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Filing Dt:
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02/21/2001
|
Publication #:
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Pub Dt:
|
10/31/2002
| | | | |
Title:
|
METHOD OF FABRICATING LOW-DIELECTRIC CONSTANT INTERLEVEL DIELECTRIC FILMS FOR BEOL INTERCONNECTS WITH ENHANCED ADHESION AND LOW-DEFECT DENSITY
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Patent #:
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|
Issue Dt:
|
09/20/2005
|
Application #:
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09789451
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Filing Dt:
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02/20/2001
|
Publication #:
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Pub Dt:
|
08/22/2002
| | | | |
Title:
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METHOD FOR ASSIGNING ENCRYPTION KEYS
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|
Patent #:
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|
Issue Dt:
|
06/22/2004
|
Application #:
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09791003
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Filing Dt:
|
02/22/2001
|
Publication #:
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Pub Dt:
|
08/22/2002
| | | | |
Title:
|
SYSTEM AND METHOD TO PREDETERMINE A BITMAP OF A SELF-TESTED EMBEDDED ARRAY
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Patent #:
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|
Issue Dt:
|
09/03/2002
|
Application #:
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09791024
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Filing Dt:
|
02/21/2001
|
Publication #:
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|
Pub Dt:
|
08/22/2002
| | | | |
Title:
|
SELF-ALIGNED SILICIDE PROCESS FOR REDUCTION OF SI CONSUMPTION IN SHALLOW JUNCTION AND THIN SOI ELECTRONIC DEVICES
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Patent #:
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Issue Dt:
|
08/06/2002
|
Application #:
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09791273
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Filing Dt:
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02/22/2001
|
Publication #:
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Pub Dt:
|
07/19/2001
| | | | |
Title:
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DENSELY PATTERNED SILICON-ON-INSULATOR (SOI) REGION ON A WAFER
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Patent #:
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Issue Dt:
|
11/25/2003
|
Application #:
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09793646
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Filing Dt:
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02/26/2001
|
Publication #:
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Pub Dt:
|
08/29/2002
| | | | |
Title:
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ATTENUATED EMBEDDED PHASE SHIFT PHOTOMASK BLANKS
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Patent #:
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Issue Dt:
|
08/26/2003
|
Application #:
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09794466
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Filing Dt:
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02/26/2001
|
Publication #:
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|
Pub Dt:
|
11/07/2002
| | | | |
Title:
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FLUORINE-CONTAINING STYRENE ACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
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Patent #:
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Issue Dt:
|
01/13/2004
|
Application #:
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09795429
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Filing Dt:
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02/28/2001
|
Publication #:
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Pub Dt:
|
08/29/2002
| | | | |
Title:
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HYBRID LOW-K INTERCONNECT STRUCTURE COMPRISED OF 2 SPIN-ON DIELECTRIC MATERIALS
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Patent #:
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Issue Dt:
|
03/23/2004
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Application #:
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09795430
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Filing Dt:
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02/28/2001
|
Publication #:
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Pub Dt:
|
08/29/2002
| | | | |
Title:
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INTERCONNECT STRUCTURE WITH PRECISE CONDUCTOR RESISTANCE AND METHOD TO FORM SAME
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Patent #:
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Issue Dt:
|
08/05/2003
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Application #:
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09795431
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Filing Dt:
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02/28/2001
|
Publication #:
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|
Pub Dt:
|
08/29/2002
| | | | |
Title:
|
LOW-K INTERCONNECT STRUCTURE COMPRISED OF A MULTILAYER OF SPIN-ON POROUS DIELECTRICS
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Patent #:
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Issue Dt:
|
03/11/2003
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Application #:
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09795610
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Filing Dt:
|
02/27/2001
|
Publication #:
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Pub Dt:
|
08/29/2002
| | | | |
Title:
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INTRINSIC DUAL GATE OXIDE MOSFET USING A DAMASCENE GATE PROCESS
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Patent #:
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Issue Dt:
|
09/17/2002
|
Application #:
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09796389
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Filing Dt:
|
02/28/2001
|
Publication #:
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Pub Dt:
|
08/02/2001
| | | | |
Title:
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USE OF BLIND VIAS FOR SOLDERED INTERCONNECTIONS BETWEEN SUBSTRATES AND PRINTED WIRING BOARDS
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Patent #:
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Issue Dt:
|
09/09/2003
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Application #:
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09796445
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Filing Dt:
|
03/02/2001
|
Publication #:
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Pub Dt:
|
09/05/2002
| | | | |
Title:
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FORMING A PATTERN OF A NEGATIVE PHOTORESIST
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Patent #:
|
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Issue Dt:
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01/28/2003
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Application #:
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09797078
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Filing Dt:
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03/01/2001
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Publication #:
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Pub Dt:
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09/05/2002
| | | | |
Title:
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COUPLED-CAP FLIP CHIP BGA PACKAGE WITH IMPROVED CAP DESIGN FOR REDUCED INTERFACIAL STRESSES
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09799701
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Filing Dt:
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03/07/2001
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Publication #:
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Pub Dt:
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06/20/2002
| | | | |
Title:
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NANO-DEVICES USING BLOCK-COPOLYMERS
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09801473
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Filing Dt:
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03/08/2001
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Publication #:
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Pub Dt:
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11/01/2001
| | | | |
Title:
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PROCESS FOR MAKING PLANARIZED SILICON FIN DEVICE
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09802471
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Filing Dt:
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03/09/2001
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Publication #:
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Pub Dt:
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01/30/2003
| | | | |
Title:
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PACKAGED RADIATION SENSITIVE COATED WORKPIECE PROCESS FOR MAKING AND METHOD OF STORING SAME
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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09804210
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Filing Dt:
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03/12/2001
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Publication #:
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Pub Dt:
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09/12/2002
| | | | |
Title:
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TIME-MULTIPLEXING DATA BETWEEN ASYNCHRONOUS CLOCK DOMAINS WITHIN CYCLE SIMULATION AND EMULATION ENVIRONMENTS
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Patent #:
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Issue Dt:
|
05/14/2002
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Application #:
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09804529
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Filing Dt:
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03/12/2001
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Title:
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PRINTED CIRCUIT BOARD TO MODULE MOUNTING AND INTERCONNECTING STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09804535
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Filing Dt:
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03/12/2001
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Title:
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STRUCTURE AND METHOD FOR FORMING THE SAME OF A PRINTED WIRING BOARD HAVING BUILT-IN INSPECTION AIDS
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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09805027
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Filing Dt:
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03/12/2001
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Publication #:
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Pub Dt:
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09/12/2002
| | | | |
Title:
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COPPER TO ALUMINUM INTERLAYER INTERCONNECT USING STUD AND VIA LINER
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Patent #:
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Issue Dt:
|
08/13/2002
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Application #:
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09805420
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Filing Dt:
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03/13/2001
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Title:
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CLOCKED MEMORY DEVICE THAT INCLUDES A PROGRAMMING MECHANISM FOR SETTING WRITE RECOVERY TIME AS A FUNCTION OF THE INPUT CLOCK
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Patent #:
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|
Issue Dt:
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12/10/2002
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Application #:
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09808381
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
Title:
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INTEGRATED COIL INDUCTORS FOR IC DEVICES
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|
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Patent #:
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Issue Dt:
|
02/03/2004
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Application #:
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09808724
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
Title:
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DEFECT-FREE DIELECTRIC COATINGS AND PREPARATION THEREOF USING POLYMERIC NITROGENOUS POROGENS
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Patent #:
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Issue Dt:
|
12/30/2003
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Application #:
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09808726
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
Title:
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NITROGEN-CONTAINING POLYMERS AS POROGENS IN THE PREPARATION OF HIGHLY POROUS, LOW DIELECTRIC CONSTANT MATERIALS
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Patent #:
|
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Issue Dt:
|
11/23/2004
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Application #:
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09809766
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Filing Dt:
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03/15/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
Title:
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SPATIAL PHASE LOCKING WITH SHAPED ELECTRON BEAM LITHOGRAPHY
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Patent #:
|
|
Issue Dt:
|
08/20/2002
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Application #:
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09809888
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Filing Dt:
|
03/16/2001
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Title:
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METHOD AND STRUCTURE FOR CREATING HIGH DENSITY BURIED CONTACT FOR USE WITH SOI PROCESSES FOR HIGH PERFORMANCE LOGIC
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|
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Patent #:
|
|
Issue Dt:
|
07/08/2003
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Application #:
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09810075
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Filing Dt:
|
03/15/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
Title:
|
APPARATUS AND METHOD FOR DETERMINING BUFFERED STEINER TREES FOR COMPLEX CIRCUITS
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|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
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Application #:
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09810133
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Filing Dt:
|
03/16/2001
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Publication #:
|
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Pub Dt:
|
09/19/2002
| | | | |
Title:
|
CROSSTALK SUPPRESSION IN DIFFERENTIAL AC COUPLED MULTICHANNEL IC AMPLIFIERS
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|
|
Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
09810236
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Filing Dt:
|
03/16/2001
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Publication #:
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|
Pub Dt:
|
09/19/2002
| | | | |
Title:
|
Body contact in SOI devices by electrically weakening the oxide under the body
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|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
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Application #:
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09810763
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
Title:
|
SUBSTITUTION OF NON-MINIMUM GROUNDRULE CELLS FOR NON-CRITICAL MINIMUM GROUNDRULE CELLS TO INCREASE YIELD
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|
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Patent #:
|
|
Issue Dt:
|
09/09/2003
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Application #:
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09810856
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Filing Dt:
|
03/16/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
Title:
|
METHOD FOR FABRICATING AN EPITAXIAL BASE BIPLOAR TRANSISTOR WITH RAISED EXTRINSIC BASE
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|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09811706
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Filing Dt:
|
03/19/2001
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Publication #:
|
|
Pub Dt:
|
09/19/2002
| | | | |
Title:
|
METHOD FOR FORMING NOTCH GATE HAVING SELF-ALIGNED RAISED SOURCE/DRAIN STRUCTURE
|
|
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Patent #:
|
|
Issue Dt:
|
03/04/2003
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Application #:
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09811707
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Filing Dt:
|
03/19/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
Title:
|
FABRICATION OF NOTCHED GATES BY PASSIVATING PARTIALLY ETCHED GATE SIDEWALLS AND THEN USING AN ISOTROPIC ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
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Application #:
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09811759
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Filing Dt:
|
03/20/2001
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Publication #:
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Pub Dt:
|
08/02/2001
| | | | |
Title:
|
DIODE CONNECTED TO A MAGNETIC TUNNEL JUNCTION AND SELF ALIGNED WITH A METALLIC CONDUCTOR AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
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Application #:
|
09811839
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Filing Dt:
|
03/19/2001
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Publication #:
|
|
Pub Dt:
|
07/26/2001
| | | | |
Title:
|
Methods and systems for self-servowriting including maintaining a reference level within a usable dynamic range
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|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
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Application #:
|
09811884
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Filing Dt:
|
03/19/2001
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Publication #:
|
|
Pub Dt:
|
11/01/2001
| | | | |
Title:
|
THERMAL MODULATION SYSTEM AND METHOD FOR LOCATING A CIRCUIT DEFECT
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|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09811965
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Filing Dt:
|
03/19/2001
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Publication #:
|
|
Pub Dt:
|
09/19/2002
| | | | |
Title:
|
DAMASCENE CAPACITOR HAVING A RECESSED PLATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09811979
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Filing Dt:
|
03/19/2001
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Publication #:
|
|
Pub Dt:
|
09/19/2002
| | | | |
Title:
|
INTERNALLY BALLASTED SILICON GERMANIUM TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09812006
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Filing Dt:
|
03/19/2001
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Publication #:
|
|
Pub Dt:
|
09/19/2002
| | | | |
Title:
|
EFFECTIVE CHANNEL LENGTH CONTROL USING ION IMPLANT FEED FORWARD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09813376
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Filing Dt:
|
03/21/2001
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Publication #:
|
|
Pub Dt:
|
12/13/2001
| | | | |
Title:
|
Method of forming conductive line features for enhanced reliability of multi-layer ceramic substrates
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|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
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Application #:
|
09814418
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Filing Dt:
|
03/21/2001
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Publication #:
|
|
Pub Dt:
|
09/26/2002
| | | | |
Title:
|
HIERARCHICAL BITLINE DRAM ARCHITECTURE SYSTEM
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
09814514
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Filing Dt:
|
03/22/2001
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Publication #:
|
|
Pub Dt:
|
08/30/2001
| | | | |
Title:
|
METHOD OF MAKING A VERTICAL TRANSPORT MOSFET
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|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09814589
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Filing Dt:
|
03/22/2001
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Publication #:
|
|
Pub Dt:
|
09/26/2002
| | | | |
Title:
|
STRESS-RELIEVING HEATSINK STRUCTURE AND METHOD OF ATTACHMENT TO AN ELECTRONIC PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09814766
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Filing Dt:
|
03/23/2001
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Publication #:
|
|
Pub Dt:
|
09/06/2001
| | | | |
Title:
|
STRUCTURE HAVING REFRACTORY METAL FILM ON A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09814789
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Filing Dt:
|
03/22/2001
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Publication #:
|
|
Pub Dt:
|
09/26/2002
| | | | |
Title:
|
APPARATUS TO REDUCE THERMAL FATIGUE STRESS ON FLIP CHIP SOLDER CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
09815540
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Filing Dt:
|
03/22/2001
|
Publication #:
|
|
Pub Dt:
|
09/26/2002
| | | | |
Title:
|
METHOD OF MANUFACTURING HIGH ASPECT RATIO PHOTOLITHOGRAPHIC FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09816278
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Filing Dt:
|
03/23/2001
|
Publication #:
|
|
Pub Dt:
|
09/26/2002
| | | | |
Title:
|
TRI-LAYER DIELECTRIC FUSE CAP FOR LASER DELETION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09816977
|
Filing Dt:
|
03/23/2001
|
Title:
|
DUAL DAMASCENE COPPER INTERCONNECT TO A DAMASCENE TUNGSTEN WIRING LEVEL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
09817120
|
Filing Dt:
|
03/27/2001
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
Title:
|
METHOD FOR MANUFACTURING DEVICE SUBSTRATE WITH METAL BACK-GATE AND STRUCTURE FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09818305
|
Filing Dt:
|
03/27/2001
|
Publication #:
|
|
Pub Dt:
|
08/16/2001
| | | | |
Title:
|
CHIP CARRIERS WITH ENHANCED WIRE BONDABI LITY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09818458
|
Filing Dt:
|
03/27/2001
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
HALOGEN FREE TRIAZINES, BISMALEIMIDE/EPOXY POLYMERS, PREPREGS MADE THEREFROM FOR CIRCUIT BOARDS AND RESIN COATED ARTICLES, AND USE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
09819787
|
Filing Dt:
|
03/28/2001
|
Publication #:
|
|
Pub Dt:
|
08/16/2001
| | | | |
Title:
|
SLURRY AND USE THEREOF FOR POLISHING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09820592
|
Filing Dt:
|
03/29/2001
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
Title:
|
SYSTEM AND METHOD FOR REDUCING NOISE OF CONGESTED DATALINES IN AN EDRAM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09822453
|
Filing Dt:
|
03/30/2001
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
Title:
|
Structures and methods to minimize plasma charging damage in silicon on insulator devices
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
09822587
|
Filing Dt:
|
03/30/2001
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
Title:
|
METHOD FOR FABRICATING HETEROJUNCTION BIPOLAR TRANSISTORS
|
|