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Reel/Frame:036550/0001   Pages: 983
Recorded: 09/03/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14793
Page 25 of 148
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1
Patent #:
6730445
Issue Dt:
05/04/2004
Application #:
10303341
Filing Dt:
11/22/2002
Publication #:
US20030194569
Pub Dt:
10/16/2003
Title:
ATTENUATED EMBEDDED PHASE SHIFT PHOTOMASK BLANKS
2
Patent #:
6803668
Issue Dt:
10/12/2004
Application #:
10303501
Filing Dt:
11/22/2002
Publication #:
US20040099963
Pub Dt:
05/27/2004
Title:
PROCESS-ROBUST ALIGNMENT MARK STRUCTURE FOR SEMICONDUCTOR WAFERS
3
Patent #:
6838695
Issue Dt:
01/04/2005
Application #:
10304163
Filing Dt:
11/25/2002
Publication #:
US20040099860
Pub Dt:
05/27/2004
Title:
CMOS DEVICE STRUCTURE WITH IMPROVED PFET GATE ELECTRODE
4
Patent #:
6841395
Issue Dt:
01/11/2005
Application #:
10304841
Filing Dt:
11/25/2002
Publication #:
US20040101978
Pub Dt:
05/27/2004
Title:
METHOD OF FORMING A BARRIER LAYER OF A TUNNELING MAGNETORESISTIVE SENSOR
5
Patent #:
7339963
Issue Dt:
03/04/2008
Application #:
10305516
Filing Dt:
11/27/2002
Publication #:
US20040101007
Pub Dt:
05/27/2004
Title:
HIGH SPEED DATA CHANNEL INCLUDING A CMOS VCSEL DRIVER AND A HIGH PERFORMANCE PHOTODETECTOR AND CMOS PHOTORECEIVER
6
Patent #:
6699736
Issue Dt:
03/02/2004
Application #:
10305643
Filing Dt:
11/26/2002
Publication #:
US20030082853
Pub Dt:
05/01/2003
Title:
ELECTRICAL COUPLING OF A STIFFENER TO A CHIP CARRIER
7
Patent #:
6992002
Issue Dt:
01/31/2006
Application #:
10305644
Filing Dt:
11/26/2002
Publication #:
US20030080435
Pub Dt:
05/01/2003
Title:
SHAPES-BASED MIGRATION OF ALUMINUM DESIGNS TO COPPER DAMASCENE
8
Patent #:
6888714
Issue Dt:
05/03/2005
Application #:
10305767
Filing Dt:
11/27/2002
Publication #:
US20030112578
Pub Dt:
06/19/2003
Title:
TUNEABLE FERROELECTRIC DECOUPLING CAPACITOR
9
Patent #:
7095620
Issue Dt:
08/22/2006
Application #:
10305822
Filing Dt:
11/27/2002
Publication #:
US20040100781
Pub Dt:
05/27/2004
Title:
OPTICALLY CONNECTABLE CIRCUIT BOARD WITH OPTICAL COMPONENT(S) MOUNTED THEREON
10
Patent #:
7120327
Issue Dt:
10/10/2006
Application #:
10305853
Filing Dt:
11/27/2002
Publication #:
US20040100782
Pub Dt:
05/27/2004
Title:
BACKPLANE ASSEMBLY WITH BOARD TO BOARD OPTICAL INTERCONNECTIONS
11
Patent #:
6963516
Issue Dt:
11/08/2005
Application #:
10306142
Filing Dt:
11/27/2002
Publication #:
US20040103258
Pub Dt:
05/27/2004
Title:
DYNAMIC OPTIMIZATION OF LATENCY AND BANDWIDTH ON DRAM INTERFACES
12
Patent #:
6774734
Issue Dt:
08/10/2004
Application #:
10306200
Filing Dt:
11/27/2002
Publication #:
US20040100336
Pub Dt:
05/27/2004
Title:
RING OSCILLATOR CIRCUIT FOR EDRAM/DRAM PERFORMANCE MONITORING
13
Patent #:
6972209
Issue Dt:
12/06/2005
Application #:
10306534
Filing Dt:
11/27/2002
Publication #:
US20040101663
Pub Dt:
05/27/2004
Title:
STACKED VIA-STUD WITH IMPROVED RELIABILITY IN COPPER METALLURGY
14
Patent #:
6900395
Issue Dt:
05/31/2005
Application #:
10306756
Filing Dt:
11/26/2002
Publication #:
US20040100754
Pub Dt:
05/27/2004
Title:
ENHANCED HIGH-FREQUENCY VIA INTERCONNECTION FOR IMPROVED RELIABILITY
15
Patent #:
6829413
Issue Dt:
12/07/2004
Application #:
10307951
Filing Dt:
12/02/2002
Publication #:
US20040105648
Pub Dt:
06/03/2004
Title:
FERRULE-LESS OPTICAL FIBER APPARATUS FOR OPTICAL BACKPLANE CONNECTOR SYSTEMS
16
Patent #:
6799309
Issue Dt:
09/28/2004
Application #:
10309654
Filing Dt:
12/04/2002
Publication #:
US20040111687
Pub Dt:
06/10/2004
Title:
METHOD FOR OPTIMIZING A VLSI FLOOR PLANNER USING A PATH BASED HYPER-EDGE REPRESENTATION
17
Patent #:
7417315
Issue Dt:
08/26/2008
Application #:
10310532
Filing Dt:
12/05/2002
Publication #:
US20040110322
Pub Dt:
06/10/2004
Title:
NEGATIVE THERMAL EXPANSION SYSTEM (NTES) DEVICE FOR TCE COMPENSATION IN ELASTOMER COMPOSITES AND CONDUCTIVE ELASTOMER INTERCONNECTS IN MICROELECTRONIC PACKAGING
18
Patent #:
6919420
Issue Dt:
07/19/2005
Application #:
10310749
Filing Dt:
12/05/2002
Publication #:
US20040110010
Pub Dt:
06/10/2004
Title:
ACID-CLEAVABLE ACETAL AND KETAL BASED EPOXY OLIGOMERS
19
Patent #:
6967715
Issue Dt:
11/22/2005
Application #:
10310759
Filing Dt:
12/06/2002
Publication #:
US20040109174
Pub Dt:
06/10/2004
Title:
METHOD AND APPARATUS FOR OPTICAL FILM MEASUREMENTS IN A CONTROLLED ENVIRONMENT
20
Patent #:
NONE
Issue Dt:
Application #:
10314497
Filing Dt:
12/06/2002
Publication #:
US20040110388
Pub Dt:
06/10/2004
Title:
Apparatus and method for shielding a wafer from charged particles during plasma etching
21
Patent #:
7030481
Issue Dt:
04/18/2006
Application #:
10314589
Filing Dt:
12/09/2002
Publication #:
US20040108587
Pub Dt:
06/10/2004
Title:
HIGH DENSITY CHIP CARRIER WITH INTEGRATED PASSIVE DEVICES
22
Patent #:
6952352
Issue Dt:
10/04/2005
Application #:
10314599
Filing Dt:
12/09/2002
Publication #:
US20040109283
Pub Dt:
06/10/2004
Title:
INTEGRATED CIRCUIT CHIP PACKAGE WITH FORMABLE INTERMEDIATE 3D WIRING STRUCTURE
23
Patent #:
7176484
Issue Dt:
02/13/2007
Application #:
10314607
Filing Dt:
12/09/2002
Publication #:
US20040110093
Pub Dt:
06/10/2004
Title:
USE OF AN ENERGY SOURCE TO CONVERT PRECURSORS INTO PATTERNED SEMICONDUCTORS
24
Patent #:
6918982
Issue Dt:
07/19/2005
Application #:
10314632
Filing Dt:
12/09/2002
Publication #:
US20040108047
Pub Dt:
06/10/2004
Title:
SYSTEM AND METHOD OF TRANSFER PRINTING AN ORGANIC SEMICONDUCTOR
25
Patent #:
6858532
Issue Dt:
02/22/2005
Application #:
10316211
Filing Dt:
12/10/2002
Publication #:
US20040110354
Pub Dt:
06/10/2004
Title:
LOW DEFECT PRE-EMITTER AND PRE-BASE OXIDE ETCH FOR BIPOLAR TRANSISTORS AND RELATED TOOLING
26
Patent #:
7825516
Issue Dt:
11/02/2010
Application #:
10316484
Filing Dt:
12/11/2002
Publication #:
US20040113277
Pub Dt:
06/17/2004
Title:
FORMATION OF ALIGNED CAPPED METAL LINES AND INTERCONNECTIONS IN MULTILEVEL SEMICONDUCTOR STRUCTURES
27
Patent #:
7007378
Issue Dt:
03/07/2006
Application #:
10317329
Filing Dt:
12/12/2002
Publication #:
US20030102160
Pub Dt:
06/05/2003
Title:
PROCESS FOR MANUFACTURING A PRINTED WIRING BOARD
28
Patent #:
7724759
Issue Dt:
05/25/2010
Application #:
10317421
Filing Dt:
12/12/2002
Publication #:
US20040100988
Pub Dt:
05/27/2004
Title:
METHOD FOR THE ASYNCHRONOUS ARBITRATION OF A HIGH FREQUENCY BUS IN A LONG LATENCY ENVIRONMENT
29
Patent #:
7211816
Issue Dt:
05/01/2007
Application #:
10317585
Filing Dt:
12/12/2002
Publication #:
US20040102084
Pub Dt:
05/27/2004
Title:
METHOD FOR IN-SITU CONTINUITY CHECK ON AN OPTICAL BUS
30
Patent #:
6974981
Issue Dt:
12/13/2005
Application #:
10318600
Filing Dt:
12/12/2002
Publication #:
US20040113174
Pub Dt:
06/17/2004
Title:
ISOLATION STRUCTURES FOR IMPOSING STRESS PATTERNS
31
Patent #:
6717216
Issue Dt:
04/06/2004
Application #:
10318601
Filing Dt:
12/12/2002
Title:
FIELD EFFECT TRANSISTOR WITH STRESSED CHANNEL AND METHOD FOR MAKING SAME
32
Patent #:
6825529
Issue Dt:
11/30/2004
Application #:
10318602
Filing Dt:
12/12/2002
Publication #:
US20040113217
Pub Dt:
06/17/2004
Title:
STRESS INDUCING SPACERS
33
Patent #:
6890413
Issue Dt:
05/10/2005
Application #:
10318607
Filing Dt:
12/11/2002
Publication #:
US20040115932
Pub Dt:
06/17/2004
Title:
METHOD AND APPARATUS FOR CONTROLLING LOCAL CURRENT TO ACHIEVE UNIFORM PLATING THICKNESS
34
Patent #:
6806793
Issue Dt:
10/19/2004
Application #:
10318933
Filing Dt:
12/13/2002
Publication #:
US20040113721
Pub Dt:
06/17/2004
Title:
MLC FREQUENCY SELECTIVE CIRCUIT STRUCTURES
35
Patent #:
6831363
Issue Dt:
12/14/2004
Application #:
10319032
Filing Dt:
12/12/2002
Publication #:
US20040113278
Pub Dt:
06/17/2004
Title:
STRUCTURE AND METHOD FOR REDUCING THERMO-MECHANICAL STRESS IN STACKED VIAS
36
Patent #:
6992344
Issue Dt:
01/31/2006
Application #:
10319724
Filing Dt:
12/13/2002
Publication #:
US20040113235
Pub Dt:
06/17/2004
Title:
DAMASCENE INTEGRATION SCHEME FOR DEVELOPING METAL-INSULATOR-METAL CAPACITORS
37
Patent #:
7252875
Issue Dt:
08/07/2007
Application #:
10320111
Filing Dt:
12/16/2002
Publication #:
US20040115407
Pub Dt:
06/17/2004
Title:
DIFFUSION BARRIER WITH LOW DIELECTRIC CONSTANT AND SEMICONDUCTOR DEVICE CONTAINING SAME
38
Patent #:
6867967
Issue Dt:
03/15/2005
Application #:
10320181
Filing Dt:
12/16/2002
Publication #:
US20040114323
Pub Dt:
06/17/2004
Title:
METHOD OF CONSTRUCTING A MULTICOMPUTER SYSTEM
39
Patent #:
NONE
Issue Dt:
Application #:
10320185
Filing Dt:
12/16/2002
Publication #:
US20030085447
Pub Dt:
05/08/2003
Title:
Beol decoupling capacitor
40
Patent #:
6657864
Issue Dt:
12/02/2003
Application #:
10320845
Filing Dt:
12/16/2002
Title:
HIGH DENSITY THERMAL SOLUTION FOR DIRECT ATTACH MODULES
41
Patent #:
NONE
Issue Dt:
Application #:
10320852
Filing Dt:
12/16/2002
Publication #:
US20040112863
Pub Dt:
06/17/2004
Title:
Method of enhancing surface reactions by local resonant heating
42
Patent #:
7022544
Issue Dt:
04/04/2006
Application #:
10321660
Filing Dt:
12/18/2002
Publication #:
US20040119093
Pub Dt:
06/24/2004
Title:
HIGH SPEED PHOTODIODE WITH A BARRIER LAYER FOR BLOCKING OR ELIMINATING SLOW PHOTONIC CARRIERS AND METHOD FOR FORMING SAME
43
Patent #:
6787783
Issue Dt:
09/07/2004
Application #:
10321942
Filing Dt:
12/17/2002
Publication #:
US20040113097
Pub Dt:
06/17/2004
Title:
APPARATUS AND TECHNIQUES FOR SCANNING ELECTRON BEAM BASED CHIP REPAIR
44
Patent #:
NONE
Issue Dt:
Application #:
10322831
Filing Dt:
12/18/2002
Publication #:
US20030092254
Pub Dt:
05/15/2003
Title:
Common ball-limiting metallurgy for I/O sites
45
Patent #:
6833332
Issue Dt:
12/21/2004
Application #:
10323024
Filing Dt:
12/18/2002
Publication #:
US20030127646
Pub Dt:
07/10/2003
Title:
METHOD FOR FABRICATION OF RELAXED SIGE BUFFER LAYERS ON SILICON-ON-INSULATORS AND STRUCTURES CONTAINING THE SAME
46
Patent #:
6777809
Issue Dt:
08/17/2004
Application #:
10323132
Filing Dt:
12/19/2002
Publication #:
US20030089943
Pub Dt:
05/15/2003
Title:
BEOL DECOUPLING CAPACITOR
47
Patent #:
7053401
Issue Dt:
05/30/2006
Application #:
10323899
Filing Dt:
12/20/2002
Publication #:
US20040119073
Pub Dt:
06/24/2004
Title:
SYNTHESIS AND APPLICATION OF PHOTOSENSITIVE PENTACENE PRECURSOR IN ORGANIC THIN FILM TRANSISTORS
48
Patent #:
7115912
Issue Dt:
10/03/2006
Application #:
10324963
Filing Dt:
12/20/2002
Publication #:
US20030122138
Pub Dt:
07/03/2003
Title:
DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS
49
Patent #:
7183568
Issue Dt:
02/27/2007
Application #:
10326172
Filing Dt:
12/23/2002
Publication #:
US20040120183
Pub Dt:
06/24/2004
Title:
PIEZOELECTRIC ARRAY WITH STRAIN DEPENDENT CONDUCTING ELEMENTS AND METHOD THEREFOR
50
Patent #:
6957404
Issue Dt:
10/18/2005
Application #:
10328112
Filing Dt:
12/20/2002
Publication #:
US20040123254
Pub Dt:
06/24/2004
Title:
MODEL CHECKING WITH LAYERED LOCALIZATION REDUCTION
51
Patent #:
6833569
Issue Dt:
12/21/2004
Application #:
10328234
Filing Dt:
12/23/2002
Publication #:
US20040121549
Pub Dt:
06/24/2004
Title:
SELF-ALIGNED PLANAR DOUBLE-GATE PROCESS BY AMORPHIZATION
52
Patent #:
7078773
Issue Dt:
07/18/2006
Application #:
10328258
Filing Dt:
12/23/2002
Publication #:
US20040119115
Pub Dt:
06/24/2004
Title:
NITRIDE-ENCAPSULATED FET (NNCFET)
53
Patent #:
6946696
Issue Dt:
09/20/2005
Application #:
10328285
Filing Dt:
12/23/2002
Publication #:
US20040119102
Pub Dt:
06/24/2004
Title:
SELF-ALIGNED ISOLATION DOUBLE-GATE FET
54
Patent #:
6789234
Issue Dt:
09/07/2004
Application #:
10328355
Filing Dt:
12/23/2002
Publication #:
US20030126565
Pub Dt:
07/03/2003
Title:
METHOD AND SYSTEM FOR A TIMING BASED LOGIC ENTRY
55
Patent #:
6794721
Issue Dt:
09/21/2004
Application #:
10328650
Filing Dt:
12/23/2002
Publication #:
US20040119128
Pub Dt:
06/24/2004
Title:
INTEGRATION SYSTEM VIA METAL OXIDE CONVERSION
56
Patent #:
6812533
Issue Dt:
11/02/2004
Application #:
10328694
Filing Dt:
12/24/2002
Publication #:
US20040119136
Pub Dt:
06/24/2004
Title:
BIPOLAR TRANSISTOR HAVING A MAJORITY-CARRIER ACCUMULATION LAYER AS SUBCOLLECTOR
57
Patent #:
7276775
Issue Dt:
10/02/2007
Application #:
10329593
Filing Dt:
12/26/2002
Publication #:
US20030109090
Pub Dt:
06/12/2003
Title:
INTRINSIC DUAL GATE OXIDE MOSFET USING A DAMASCENE GATE PROCESS
58
Patent #:
6774482
Issue Dt:
08/10/2004
Application #:
10330742
Filing Dt:
12/27/2002
Publication #:
US20040124525
Pub Dt:
07/01/2004
Title:
CHIP COOLING
59
Patent #:
6930034
Issue Dt:
08/16/2005
Application #:
10331038
Filing Dt:
12/27/2002
Publication #:
US20040127001
Pub Dt:
07/01/2004
Title:
ROBUST ULTRA-LOW K INTERCONNECT STRUCTURES USING BRIDGE-THEN-METALLIZATION FABRICATION SEQUENCE
60
Patent #:
6815343
Issue Dt:
11/09/2004
Application #:
10334178
Filing Dt:
12/30/2002
Publication #:
US20040126939
Pub Dt:
07/01/2004
Title:
GAS TREATMENT OF THIN FILM STRUCTURES WITH CATALYTIC ACTION
61
Patent #:
7160665
Issue Dt:
01/09/2007
Application #:
10334219
Filing Dt:
12/30/2002
Publication #:
US20040126715
Pub Dt:
07/01/2004
Title:
METHOD FOR EMPLOYING VERTICAL ACID TRANSPORT FOR LITHOGRAPHIC IMAGING APPLICATIONS
62
Patent #:
6800518
Issue Dt:
10/05/2004
Application #:
10334220
Filing Dt:
12/30/2002
Publication #:
US20040126985
Pub Dt:
07/01/2004
Title:
FORMATION OF PATTERNED SILICON-ON-INSULATOR (SOI)/SILICON-ON-NOTHING (SON) COMPOSITE STRUCTURE BY POROUS SI ENGINEERING
63
Patent #:
6823293
Issue Dt:
11/23/2004
Application #:
10334312
Filing Dt:
12/31/2002
Publication #:
US20040128115
Pub Dt:
07/01/2004
Title:
HIERARCHICAL POWER SUPPLY NOISE MONITORING DEVICE AND SYSTEM FOR VERY LARGE SCALE INTEGRATED CIRCUITS
64
Patent #:
6818285
Issue Dt:
11/16/2004
Application #:
10334413
Filing Dt:
12/31/2002
Publication #:
US20040126586
Pub Dt:
07/01/2004
Title:
COMPOSITION AND METHOD TO ACHIEVE REDUCED THERMAL EXPANSION IN POLYARYLENE NETWORKS
65
Patent #:
6635543
Issue Dt:
10/21/2003
Application #:
10335652
Filing Dt:
12/31/2002
Publication #:
US20030104658
Pub Dt:
06/05/2003
Title:
SOI HYBRID STRUCTURE WITH SELECTIVE EPITAXIAL GROWTH OF SILICON
66
Patent #:
6791868
Issue Dt:
09/14/2004
Application #:
10335671
Filing Dt:
01/02/2003
Publication #:
US20040130935
Pub Dt:
07/08/2004
Title:
FERROMAGNETIC RESONANCE SWITCHING FOR MAGNETIC RANDOM ACCESS MEMORY
67
Patent #:
6762088
Issue Dt:
07/13/2004
Application #:
10336291
Filing Dt:
01/03/2003
Publication #:
US20030096435
Pub Dt:
05/22/2003
Title:
HIGH Q INDUCTOR WITH FARADAY SHIELD AND DIELECTRIC WELL BURIED IN SUBSTRATE
68
Patent #:
6905961
Issue Dt:
06/14/2005
Application #:
10336579
Filing Dt:
01/03/2003
Publication #:
US20030090000
Pub Dt:
05/15/2003
Title:
LAND GRID ARRAY STIFFENER FOR USE WITH FLEXIBLE CHIP CARRIERS
69
Patent #:
6703274
Issue Dt:
03/09/2004
Application #:
10336988
Filing Dt:
01/03/2003
Title:
BURIED STRAP WITH LIMITED OUTDIFFUSION AND VERTICAL TRANSISTOR DRAM
70
Patent #:
7022246
Issue Dt:
04/04/2006
Application #:
10336992
Filing Dt:
01/06/2003
Publication #:
US20040130434
Pub Dt:
07/08/2004
Title:
METHOD OF FABRICATION OF MIMCAP AND RESISTOR AT SAME LEVEL
71
Patent #:
6764883
Issue Dt:
07/20/2004
Application #:
10338071
Filing Dt:
01/07/2003
Publication #:
US20040129941
Pub Dt:
07/08/2004
Title:
AMORPHOUS AND POLYCRYSTALLINE SILICON NANOLAMINATE
72
Patent #:
NONE
Issue Dt:
Application #:
10338095
Filing Dt:
01/07/2003
Publication #:
US20040132287
Pub Dt:
07/08/2004
Title:
Dry etch process for copper
73
Patent #:
NONE
Issue Dt:
Application #:
10338105
Filing Dt:
01/07/2003
Publication #:
US20040130027
Pub Dt:
07/08/2004
Title:
IMPROVED FORMATION OF POROUS INTERCONNECTION LAYERS
74
Patent #:
6653246
Issue Dt:
11/25/2003
Application #:
10338481
Filing Dt:
01/08/2003
Publication #:
US20030132509
Pub Dt:
07/17/2003
Title:
HIGH DIELECTRIC CONSTANT MATERIALS
75
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Filing Dt:
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Pub Dt:
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Title:
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Issue Dt:
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Filing Dt:
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Title:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Pub Dt:
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Title:
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Filing Dt:
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Title:
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Title:
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Title:
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Title:
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Filing Dt:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
06/29/2015
Assignee
1
GLOBALFOUNDRIES U.S. 2 LLC
2070 ROUTE 52
HOPEWELL JUNCTION, NEW YORK 12533
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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