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Reel/Frame:036550/0001   Pages: 983
Recorded: 09/03/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14793
Page 42 of 148
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
1
Patent #:
7709317
Issue Dt:
05/04/2010
Application #:
11164193
Filing Dt:
11/14/2005
Publication #:
US20070108525
Pub Dt:
05/17/2007
Title:
METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS
2
Patent #:
7250666
Issue Dt:
07/31/2007
Application #:
11164214
Filing Dt:
11/15/2005
Publication #:
US20070108534
Pub Dt:
05/17/2007
Title:
SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
3
Patent #:
7309626
Issue Dt:
12/18/2007
Application #:
11164215
Filing Dt:
11/15/2005
Publication #:
US20070108536
Pub Dt:
05/17/2007
Title:
QUASI SELF-ALIGNED SOURCE/DRAIN FINFET PROCESS
4
Patent #:
7326976
Issue Dt:
02/05/2008
Application #:
11164216
Filing Dt:
11/15/2005
Publication #:
US20070108537
Pub Dt:
05/17/2007
Title:
CORNER DOMINATED TRIGATE FIELD EFFECT TRANSISTOR
5
Patent #:
7378717
Issue Dt:
05/27/2008
Application #:
11164217
Filing Dt:
11/15/2005
Publication #:
US20070108473
Pub Dt:
05/17/2007
Title:
SEMICONDUCTOR OPTICAL SENSORS
6
Patent #:
7279411
Issue Dt:
10/09/2007
Application #:
11164223
Filing Dt:
11/15/2005
Publication #:
US20070111497
Pub Dt:
05/17/2007
Title:
PROCESS FOR FORMING A REDUNDANT STRUCTURE
7
Patent #:
7183613
Issue Dt:
02/27/2007
Application #:
11164224
Filing Dt:
11/15/2005
Title:
METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM
8
Patent #:
7476938
Issue Dt:
01/13/2009
Application #:
11164373
Filing Dt:
11/21/2005
Publication #:
US20070114632
Pub Dt:
05/24/2007
Title:
TRANSISTOR HAVING DIELECTRIC STRESSOR ELEMENTS AT DIFFERENT DEPTHS FROM A SEMICONDUCTOR SURFACE FOR APPLYING SHEAR STRESS
9
Patent #:
7408206
Issue Dt:
08/05/2008
Application #:
11164377
Filing Dt:
11/21/2005
Publication #:
US20070115606
Pub Dt:
05/24/2007
Title:
METHOD AND STRUCTURE FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS
10
Patent #:
7655972
Issue Dt:
02/02/2010
Application #:
11164378
Filing Dt:
11/21/2005
Publication #:
US20070114611
Pub Dt:
05/24/2007
Title:
STRUCTURE AND METHOD FOR MOSFET WITH REDUCED EXTENSION RESISTANCE
11
Patent #:
7427545
Issue Dt:
09/23/2008
Application #:
11164381
Filing Dt:
11/21/2005
Publication #:
US20070117307
Pub Dt:
05/24/2007
Title:
TRENCH MEMORY CELLS WITH BURIED ISOLATION COLLARS, AND METHODS OF FABRICATING SAME
12
Patent #:
7977185
Issue Dt:
07/12/2011
Application #:
11164417
Filing Dt:
11/22/2005
Publication #:
US20070161244
Pub Dt:
07/12/2007
Title:
METHOD AND APPARATUS FOR POST SILICIDE SPACER REMOVAL
13
Patent #:
NONE
Issue Dt:
Application #:
11164437
Filing Dt:
11/22/2005
Publication #:
US20070113950
Pub Dt:
05/24/2007
Title:
METHOD AND APPARATUS FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
14
Patent #:
NONE
Issue Dt:
Application #:
11164511
Filing Dt:
11/28/2005
Publication #:
US20070123042
Pub Dt:
05/31/2007
Title:
METHODS TO FORM HETEROGENEOUS SILICIDES/GERMANIDES IN CMOS TECHNOLOGY
15
Patent #:
7514323
Issue Dt:
04/07/2009
Application #:
11164513
Filing Dt:
11/28/2005
Publication #:
US20070122971
Pub Dt:
05/31/2007
Title:
VERTICAL SOI TRENCH SONOS CELL
16
Patent #:
7564081
Issue Dt:
07/21/2009
Application #:
11164621
Filing Dt:
11/30/2005
Publication #:
US20070120154
Pub Dt:
05/31/2007
Title:
FINFET STRUCTURE WITH MULTIPLY STRESSED GATE ELECTRODE
17
Patent #:
7659581
Issue Dt:
02/09/2010
Application #:
11164632
Filing Dt:
11/30/2005
Publication #:
US20070122956
Pub Dt:
05/31/2007
Title:
TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENT FULLY UNDERLYING THE ACTIVE SEMICONDUCTOR REGION
18
Patent #:
7768055
Issue Dt:
08/03/2010
Application #:
11164634
Filing Dt:
11/30/2005
Publication #:
US20070123015
Pub Dt:
05/31/2007
Title:
PASSIVE COMPONENTS IN THE BACK END OF INTEGRATED CIRCUITS
19
Patent #:
7701035
Issue Dt:
04/20/2010
Application #:
11164640
Filing Dt:
11/30/2005
Publication #:
US20070120232
Pub Dt:
05/31/2007
Title:
LASER FUSE STRUCTURES FOR HIGH POWER APPLICATIONS
20
Patent #:
7816738
Issue Dt:
10/19/2010
Application #:
11164651
Filing Dt:
11/30/2005
Publication #:
US20070122957
Pub Dt:
05/31/2007
Title:
LOW-COST FEOL FOR ULTRA-LOW POWER, NEAR SUB-VTH DEVICE STRUCTURES
21
Patent #:
NONE
Issue Dt:
Application #:
11164656
Filing Dt:
11/30/2005
Publication #:
US20070124538
Pub Dt:
05/31/2007
Title:
POWER-EFFICIENT CACHE MEMORY SYSTEM AND METHOD THEREFOR
22
Patent #:
7871933
Issue Dt:
01/18/2011
Application #:
11164684
Filing Dt:
12/01/2005
Publication #:
US20070128859
Pub Dt:
06/07/2007
Title:
COMBINED STEPPER AND DEPOSITION TOOL
23
Patent #:
7608909
Issue Dt:
10/27/2009
Application #:
11164765
Filing Dt:
12/05/2005
Publication #:
US20060197119
Pub Dt:
09/07/2006
Title:
SUSPENDED TRANSMISSION LINE STRUCTURES IN BACK END OF LINE PROCESSING
24
Patent #:
7605075
Issue Dt:
10/20/2009
Application #:
11164791
Filing Dt:
12/06/2005
Publication #:
US20060226537
Pub Dt:
10/12/2006
Title:
MULTILAYER CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME
25
Patent #:
7368712
Issue Dt:
05/06/2008
Application #:
11164792
Filing Dt:
12/06/2005
Publication #:
US20070125946
Pub Dt:
06/07/2007
Title:
Y-SHAPED CARBON NANOTUBES AS AFM PROBE FOR ANALYZING SUBSTRATES WITH ANGLED TOPOGRAPHY
26
Patent #:
7199309
Issue Dt:
04/03/2007
Application #:
11167662
Filing Dt:
06/27/2005
Publication #:
US20050239347
Pub Dt:
10/27/2005
Title:
STRUCTURE FOR REPAIRING OR MODIFYING SURFACE CONNECTIONS ON CIRCUIT BOARDS
27
Patent #:
NONE
Issue Dt:
Application #:
11168559
Filing Dt:
06/29/2005
Publication #:
US20060017169
Pub Dt:
01/26/2006
Title:
Electroplated interconnection structures on integrated circuit chips
28
Patent #:
7411425
Issue Dt:
08/12/2008
Application #:
11168691
Filing Dt:
06/28/2005
Publication #:
US20060290382
Pub Dt:
12/28/2006
Title:
METHOD FOR POWER CONSUMPTION REDUCTION IN A LIMITED-SWITCH DYNAMIC LOGIC (LSDL) CIRCUIT
29
Patent #:
7336105
Issue Dt:
02/26/2008
Application #:
11168692
Filing Dt:
06/28/2005
Publication #:
US20060290383
Pub Dt:
12/28/2006
Title:
DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC
30
Patent #:
7319608
Issue Dt:
01/15/2008
Application #:
11172473
Filing Dt:
06/30/2005
Publication #:
US20070002608
Pub Dt:
01/04/2007
Title:
NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS
31
Patent #:
7183175
Issue Dt:
02/27/2007
Application #:
11172707
Filing Dt:
07/01/2005
Publication #:
US20050260825
Pub Dt:
11/24/2005
Title:
SHALLOW TRENCH ISOLATION STRUCTURE FOR STRAINED SI ON SIGE
32
Patent #:
NONE
Issue Dt:
Application #:
11172992
Filing Dt:
07/05/2005
Publication #:
US20050269708
Pub Dt:
12/08/2005
Title:
Tungsten encapsulated copper interconnections using electroplating
33
Patent #:
7419907
Issue Dt:
09/02/2008
Application #:
11173038
Filing Dt:
07/01/2005
Publication #:
US20070004205
Pub Dt:
01/04/2007
Title:
ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS NI ALLOY SILICIDE STRUCTURE
34
Patent #:
7546109
Issue Dt:
06/09/2009
Application #:
11174360
Filing Dt:
06/30/2005
Publication #:
US20070004367
Pub Dt:
01/04/2007
Title:
GILBERT MIXERS WITH IMPROVED ISOLATION AND METHODS THEREFOR
35
Patent #:
7348226
Issue Dt:
03/25/2008
Application #:
11174738
Filing Dt:
07/06/2005
Publication #:
US20050266663
Pub Dt:
12/01/2005
Title:
METHOD OF FORMING LATTICE-MATCHED STRUCTURE ON SILICON AND STRUCTURE FORMED THEREBY
36
Patent #:
7300867
Issue Dt:
11/27/2007
Application #:
11174985
Filing Dt:
07/05/2005
Publication #:
US20050245068
Pub Dt:
11/03/2005
Title:
DUAL DAMASCENE INTERCONNECT STRUCTURES HAVING DIFFERENT MATERIALS FOR LINE AND VIA CONDUCTORS
37
Patent #:
7750410
Issue Dt:
07/06/2010
Application #:
11175223
Filing Dt:
07/07/2005
Publication #:
US20050245017
Pub Dt:
11/03/2005
Title:
STRUCTURE AND METHOD TO IMPROVE CHANNEL MOBILITY BY GATE ELECTRODE STRESS MODIFICATION
38
Patent #:
7994575
Issue Dt:
08/09/2011
Application #:
11175582
Filing Dt:
07/06/2005
Publication #:
US20050242378
Pub Dt:
11/03/2005
Title:
METAL-OXIDE-SEMICONDUCTOR DEVICE STRUCTURES WITH TAILORED DOPANT DEPTH PROFILES
39
Patent #:
7473607
Issue Dt:
01/06/2009
Application #:
11175762
Filing Dt:
07/06/2005
Publication #:
US20070020865
Pub Dt:
01/25/2007
Title:
METHOD OF MANUFACTURING A MULTI-WORKFUNCTION GATES FOR A CMOS CIRCUIT
40
Patent #:
7791141
Issue Dt:
09/07/2010
Application #:
11176173
Filing Dt:
07/07/2005
Publication #:
US20060027893
Pub Dt:
02/09/2006
Title:
FIELD-ENHANCED PROGRAMMABLE RESISTANCE MEMORY CELL
41
Patent #:
7346875
Issue Dt:
03/18/2008
Application #:
11176712
Filing Dt:
07/07/2005
Publication #:
US20050262463
Pub Dt:
11/24/2005
Title:
WIRING OPTIMIZATIONS FOR POWER
42
Patent #:
NONE
Issue Dt:
Application #:
11177119
Filing Dt:
07/08/2005
Publication #:
US20060006471
Pub Dt:
01/12/2006
Title:
Resistor with improved switchable resistance and non-volatile memory device
43
Patent #:
7331007
Issue Dt:
02/12/2008
Application #:
11177127
Filing Dt:
07/07/2005
Publication #:
US20070011631
Pub Dt:
01/11/2007
Title:
HARNESSING MACHINE LEARNING TO IMPROVE THE SUCCESS RATE OF STIMULI GENERATION
44
Patent #:
7266737
Issue Dt:
09/04/2007
Application #:
11180416
Filing Dt:
07/13/2005
Publication #:
US20070033459
Pub Dt:
02/08/2007
Title:
METHOD FOR ENABLING SCAN OF DEFECTIVE RAM PRIOR TO REPAIR
45
Patent #:
7376924
Issue Dt:
05/20/2008
Application #:
11180740
Filing Dt:
07/13/2005
Publication #:
US20060010413
Pub Dt:
01/12/2006
Title:
METHODS FOR PLACEMENT WHICH MAINTAIN OPTIMIZED BEHAVIOR, WHILE IMPROVING WIREABILITY POTENTIAL
46
Patent #:
NONE
Issue Dt:
Application #:
11180787
Filing Dt:
07/14/2005
Publication #:
US20070015082
Pub Dt:
01/18/2007
Title:
Process of making a lithographic structure using antireflective materials
47
Patent #:
7326442
Issue Dt:
02/05/2008
Application #:
11180788
Filing Dt:
07/14/2005
Publication #:
US20070015083
Pub Dt:
01/18/2007
Title:
ANTIREFLECTIVE COMPOSITION AND PROCESS OF MAKING A LITHOGRAPHIC STRUCTURE
48
Patent #:
7417453
Issue Dt:
08/26/2008
Application #:
11181053
Filing Dt:
07/14/2005
Publication #:
US20050251778
Pub Dt:
11/10/2005
Title:
SYSTEM AND METHOD FOR DYNAMICALLY EXECUTING A FUNCTION IN A PROGRAMMABLE LOGIC ARRAY
49
Patent #:
7434182
Issue Dt:
10/07/2008
Application #:
11181442
Filing Dt:
07/14/2005
Publication #:
US20070016880
Pub Dt:
01/18/2007
Title:
METHOD FOR TESTING SUB-SYSTEMS OF A SYSTEM-ON-A-CHIP USING A CONFIGURABLE EXTERNAL SYSTEM-ON-A-CHIP
50
Patent #:
7425855
Issue Dt:
09/16/2008
Application #:
11181707
Filing Dt:
07/14/2005
Publication #:
US20070013426
Pub Dt:
01/18/2007
Title:
SET/RESET LATCH WITH MINIMUM SINGLE EVENT UPSET
51
Patent #:
7382162
Issue Dt:
06/03/2008
Application #:
11181954
Filing Dt:
07/14/2005
Publication #:
US20070013413
Pub Dt:
01/18/2007
Title:
HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS
52
Patent #:
7278207
Issue Dt:
10/09/2007
Application #:
11182167
Filing Dt:
07/15/2005
Publication #:
US20050250249
Pub Dt:
11/10/2005
Title:
METHOD OF MAKING AN ELECTRONIC PACKAGE
53
Patent #:
7217629
Issue Dt:
05/15/2007
Application #:
11182381
Filing Dt:
07/15/2005
Publication #:
US20070013001
Pub Dt:
01/18/2007
Title:
EPITAXIAL IMPRINTING
54
Patent #:
7378350
Issue Dt:
05/27/2008
Application #:
11182445
Filing Dt:
07/15/2005
Publication #:
US20050266681
Pub Dt:
12/01/2005
Title:
FORMATION OF LOW RESISTANCE VIA CONTACTS IN INTERCONNECT STRUCTURES
55
Patent #:
7289422
Issue Dt:
10/30/2007
Application #:
11182558
Filing Dt:
07/15/2005
Publication #:
US20050254355
Pub Dt:
11/17/2005
Title:
OPTICAL DEVICES HAVING TRANSMISSION ENHANCED BY SURFACE PLASMON MODE RESONANCE, AND THEIR USE IN DATA RECORDING
56
Patent #:
7405131
Issue Dt:
07/29/2008
Application #:
11182681
Filing Dt:
07/16/2005
Publication #:
US20070020864
Pub Dt:
01/25/2007
Title:
METHOD AND STRUCTURE TO PREVENT SILICIDE STRAPPING OF SOURCE/DRAIN TO BODY IN SEMICONDUCTOR DEVICES WITH SOURCE/DRAIN STRESSOR
57
Patent #:
7442618
Issue Dt:
10/28/2008
Application #:
11182682
Filing Dt:
07/16/2005
Publication #:
US20070020861
Pub Dt:
01/25/2007
Title:
METHOD TO ENGINEER ETCH PROFILES IN SI SUBSTRATE FOR ADVANCED SEMICONDUCTOR DEVICES
58
Patent #:
7381635
Issue Dt:
06/03/2008
Application #:
11183647
Filing Dt:
07/18/2005
Publication #:
US20070013073
Pub Dt:
01/18/2007
Title:
METHOD AND STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS
59
Patent #:
7468320
Issue Dt:
12/23/2008
Application #:
11183773
Filing Dt:
07/19/2005
Publication #:
US20050266673
Pub Dt:
12/01/2005
Title:
REDUCED ELECTROMIGRATION AND STRESSED INDUCED MIGRATION OF COPPER WIRES BY SURFACE COATING
60
Patent #:
7342287
Issue Dt:
03/11/2008
Application #:
11184244
Filing Dt:
07/19/2005
Publication #:
US20070018248
Pub Dt:
01/25/2007
Title:
POWER GATING SCHEMES IN SOI CIRCUITS IN HYBRID SOI-EPITAXIAL CMOS STRUCTURES
61
Patent #:
7354777
Issue Dt:
04/08/2008
Application #:
11184702
Filing Dt:
07/19/2005
Publication #:
US20050255707
Pub Dt:
11/17/2005
Title:
DISCRETE NANO-TEXTURED STRUCTURES IN BIOMOLECULAR ARRAYS, AND METHOD OF USE
62
Patent #:
NONE
Issue Dt:
Application #:
11185646
Filing Dt:
07/20/2005
Publication #:
US20070018239
Pub Dt:
01/25/2007
Title:
SEA-OF-FINS STRUCTURE ON A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION
63
Patent #:
7517806
Issue Dt:
04/14/2009
Application #:
11186748
Filing Dt:
07/21/2005
Publication #:
US20050272195
Pub Dt:
12/08/2005
Title:
INTEGRATED CIRCUIT HAVING PAIRS OF PARALLEL COMPLEMENTARY FINFETS
64
Patent #:
7674521
Issue Dt:
03/09/2010
Application #:
11190360
Filing Dt:
07/27/2005
Publication #:
US20070196639
Pub Dt:
08/23/2007
Title:
MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE
65
Patent #:
7459183
Issue Dt:
12/02/2008
Application #:
11190644
Filing Dt:
07/27/2005
Publication #:
US20070023870
Pub Dt:
02/01/2007
Title:
METHOD OF FORMING LOW-K INTERLEVEL DIELECTRIC LAYERS AND STRUCTURES
66
Patent #:
7572692
Issue Dt:
08/11/2009
Application #:
11191426
Filing Dt:
07/27/2005
Publication #:
US20050263826
Pub Dt:
12/01/2005
Title:
COMPLEMENTARY TRANSISTORS HAVING DIFFERENT SOURCE AND DRAIN EXTENSION SPACING CONTROLLED BY DIFFERENT SPACER SIZES
67
Patent #:
7635884
Issue Dt:
12/22/2009
Application #:
11193660
Filing Dt:
07/29/2005
Publication #:
US20070023806
Pub Dt:
02/01/2007
Title:
METHOD AND STRUCTURE FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES
68
Patent #:
7337420
Issue Dt:
02/26/2008
Application #:
11193711
Filing Dt:
07/29/2005
Publication #:
US20070028195
Pub Dt:
02/01/2007
Title:
METHODOLOGY FOR LAYOUT-BASED MODULATION AND OPTIMIZATION OF NITRIDE LINER STRESS EFFECT IN COMPACT MODELS
69
Patent #:
7602869
Issue Dt:
10/13/2009
Application #:
11193868
Filing Dt:
07/29/2005
Publication #:
US20070025483
Pub Dt:
02/01/2007
Title:
METHODS AND APPARATUS FOR CLOCK SYNCHRONIZATION AND DATA RECOVERY IN A RECEIVER
70
Patent #:
7460389
Issue Dt:
12/02/2008
Application #:
11193878
Filing Dt:
07/29/2005
Publication #:
US20070025144
Pub Dt:
02/01/2007
Title:
WRITE OPERATIONS FOR PHASE-CHANGE-MATERIAL MEMORY
71
Patent #:
7442049
Issue Dt:
10/28/2008
Application #:
11194790
Filing Dt:
08/01/2005
Publication #:
US20070004239
Pub Dt:
01/04/2007
Title:
ELECTRICAL CONNECTING DEVICE AND METHOD OF FORMING SAME
72
Patent #:
7366632
Issue Dt:
04/29/2008
Application #:
11195426
Filing Dt:
08/02/2005
Publication #:
US20070032979
Pub Dt:
02/08/2007
Title:
METHOD AND APPARATUS FOR THREE-DIMENSIONAL MEASUREMENTS
73
Patent #:
7439302
Issue Dt:
10/21/2008
Application #:
11195566
Filing Dt:
08/02/2005
Publication #:
US20060134547
Pub Dt:
06/22/2006
Title:
LOW REFRACTIVE INDEX POLYMERS AS UNDERLAYERS FOR SILICON-CONTAINING PHOTORESISTS
74
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Issue Dt:
09/25/2007
Application #:
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Filing Dt:
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Publication #:
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Pub Dt:
02/08/2007
Title:
FORMATION OF FULLY SILICIDED (FUSI) GATE USING A DUAL SILICIDE PROCESS
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Pub Dt:
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Title:
AUTOMATED MIGRATION OF ANALOG AND MIXED-SIGNAL VLSI DESIGN
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Title:
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Title:
WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE
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Title:
TEMPERATURE STABLE METAL NITRIDE GATE ELECTRODE
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Filing Dt:
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Pub Dt:
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Title:
Voltage controlled oscillator using dual gated asymmetrical FET devices
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Title:
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Title:
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Title:
METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATING SAME
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Title:
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Title:
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Title:
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Pub Dt:
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Title:
Dual trench isolation for CMOS with hybrid orientations
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Title:
ADOPTING FEATURE OF BURIED ELECTRICALLY CONDUCTIVE LAYER IN DIELECTRICS FOR ELECTRICAL ANTI-FUSE APPLICATION
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02/09/2006
Title:
RELAXED, LOW-DEFECT SGOI FOR STRAINED SI CMOS APPLICATIONS
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Title:
METHOD OF FABRICATING SHALLOW TRENCH ISOLATION BY ULTRA-THIN SIMOX PROCESSING
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Title:
METHOD FOR PRODUCING Z-AXIS INTERCONNECTION ASSEMBLY OF PRINTED WIRING BOARD ELEMENTS
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Title:
HIGH PERFORMANCE MOSFET COMPRISING A STRESSED GATE METAL SILICIDE LAYER AND METHOD OF FABRICATING THE SAME
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Title:
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Title:
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Title:
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Title:
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03/01/2007
Title:
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Title:
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100
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7562284
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07/14/2009
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11212208
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08/26/2005
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Pub Dt:
03/01/2007
Title:
APPARATUS, SYSTEM, AND METHOD FOR MANDATORY END TO END INTEGRITY CHECKING IN A STORAGE SYSTEM
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
06/29/2015
Assignee
1
GLOBALFOUNDRIES U.S. 2 LLC
2070 ROUTE 52
HOPEWELL JUNCTION, NEW YORK 12533
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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